[Qemu-devel] [PATCH 00/12] PCI IDE cleanup

[Qemu-devel] [PATCH 00/12] PCI IDE cleanup

[Juan Quintela]

This patch cleans ide/pci.c:
- useless casts
- split piix and cmd646 from pci.c, this allows remove some code
- clean cmd646 to allow th eremoval of pci_dev from BMDMAState.

Later, Juan.

Juan Quintela (12):
  ide: change cast to DO_UPCAST
  ide: Remove cast in pci_register_bar
  ide: Remove duplicated definitions
  ide: remove uselsess casts from void *
  ide: create ide/pci.h for common ide pci definitions
  ide: export needed ide-pci functions for split
  ide: split cmd646 and piix from pci.c
  ide: PCIIDEState type field is not needed anymore
  ide: 'secondary' field is only used by cmd646
  ide: cmd646 we can get the pci device with container_of
  ide: cmd646 ->unit has just the value that we want
  ide: BMDMAState don't need a pci_dev field anymore

 Makefile.target     |    7 +-
 hw/ide/cmd646.c     |  272 ++++++++++++++++++++++++++++++++++++
 hw/ide/internal.h   |    7 -
 hw/ide/microdrive.c |   18 ++--
 hw/ide/mmio.c       |    8 +-
 hw/ide/pci.c        |  378 ++-------------------------------------------------
 hw/ide/pci.h        |   23 +++
 hw/ide/piix.c       |  195 ++++++++++++++++++++++++++
 8 files changed, 518 insertions(+), 390 deletions(-)
 create mode 100644 hw/ide/cmd646.c
 create mode 100644 hw/ide/pci.h
 create mode 100644 hw/ide/piix.c

[Qemu-devel] [PATCH 01/12] ide: change cast to DO_UPCAST

[Juan Quintela]

Signed-off-by: Juan Quintela <quintela@redhat.com>
---
 hw/ide/pci.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/ide/pci.c b/hw/ide/pci.c
index 6d090bc..0e2c7d7 100644
--- a/hw/ide/pci.c
+++ b/hw/ide/pci.c
@@ -62,7 +62,7 @@ static void cmd646_update_irq(PCIIDEState *d);
 static void ide_map(PCIDevice *pci_dev, int region_num,
                     uint32_t addr, uint32_t size, int type)
 {
-    PCIIDEState *d = (PCIIDEState *)pci_dev;
+    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
     IDEBus *bus;

     if (region_num <= 3) {
@@ -247,7 +247,7 @@ static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
 static void bmdma_map(PCIDevice *pci_dev, int region_num,
                     uint32_t addr, uint32_t size, int type)
 {
-    PCIIDEState *d = (PCIIDEState *)pci_dev;
+    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
     int i;

     for(i = 0;i < 2; i++) {
-- 
1.6.2.5

[Qemu-devel] [PATCH 02/12] ide: Remove cast in pci_register_bar

[Juan Quintela]

We already have a PCIDevice at that point

Signed-off-by: Juan Quintela <quintela@redhat.com>
---
 hw/ide/pci.c |   18 ++++++------------
 1 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/hw/ide/pci.c b/hw/ide/pci.c
index 0e2c7d7..9d7fdd4 100644
--- a/hw/ide/pci.c
+++ b/hw/ide/pci.c
@@ -413,16 +413,11 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
         pci_conf[0x51] |= 0x08; /* enable IDE1 */
     }

-    pci_register_bar((PCIDevice *)d, 0, 0x8,
-                     PCI_ADDRESS_SPACE_IO, ide_map);
-    pci_register_bar((PCIDevice *)d, 1, 0x4,
-                     PCI_ADDRESS_SPACE_IO, ide_map);
-    pci_register_bar((PCIDevice *)d, 2, 0x8,
-                     PCI_ADDRESS_SPACE_IO, ide_map);
-    pci_register_bar((PCIDevice *)d, 3, 0x4,
-                     PCI_ADDRESS_SPACE_IO, ide_map);
-    pci_register_bar((PCIDevice *)d, 4, 0x10,
-                     PCI_ADDRESS_SPACE_IO, bmdma_map);
+    pci_register_bar(dev, 0, 0x8, PCI_ADDRESS_SPACE_IO, ide_map);
+    pci_register_bar(dev, 1, 0x4, PCI_ADDRESS_SPACE_IO, ide_map);
+    pci_register_bar(dev, 2, 0x8, PCI_ADDRESS_SPACE_IO, ide_map);
+    pci_register_bar(dev, 3, 0x4, PCI_ADDRESS_SPACE_IO, ide_map);
+    pci_register_bar(dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map);

     pci_conf[0x3d] = 0x01; // interrupt on pin 1

@@ -477,8 +472,7 @@ static int pci_piix_ide_initfn(PCIIDEState *d)
     qemu_register_reset(piix3_reset, d);
     piix3_reset(d);

-    pci_register_bar((PCIDevice *)d, 4, 0x10,
-                     PCI_ADDRESS_SPACE_IO, bmdma_map);
+    pci_register_bar(&d->dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map);

     register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);

-- 
1.6.2.5

[Qemu-devel] [PATCH 03/12] ide: Remove duplicated definitions

[Juan Quintela]

Signed-off-by: Juan Quintela <quintela@redhat.com>
---
 hw/ide/internal.h |    6 ------
 1 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/hw/ide/internal.h b/hw/ide/internal.h
index 029bf80..21319fe 100644
--- a/hw/ide/internal.h
+++ b/hw/ide/internal.h
@@ -20,12 +20,6 @@ typedef struct IDEDeviceInfo IDEDeviceInfo;
 typedef struct IDEState IDEState;
 typedef struct BMDMAState BMDMAState;

-/* debug IDE devices */
-//#define DEBUG_IDE
-//#define DEBUG_IDE_ATAPI
-//#define DEBUG_AIO
-#define USE_DMA_CDROM
-
 /* Bits of HD_STATUS */
 #define ERR_STAT		0x01
 #define INDEX_STAT		0x02
-- 
1.6.2.5

[Qemu-devel] [PATCH 04/12] ide: remove uselsess casts from void *

[Juan Quintela]

Signed-off-by: Juan Quintela <quintela@redhat.com>
---
 hw/ide/microdrive.c |   18 +++++++++---------
 hw/ide/mmio.c       |    8 ++++----
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c
index 887cde3..aeb77a0 100644
--- a/hw/ide/microdrive.c
+++ b/hw/ide/microdrive.c
@@ -94,7 +94,7 @@ static inline void md_interrupt_update(MicroDriveState *s)

 static void md_set_irq(void *opaque, int irq, int level)
 {
-    MicroDriveState *s = (MicroDriveState *) opaque;
+    MicroDriveState *s = opaque;
     if (level)
         s->stat |= STAT_INT;
     else
@@ -115,7 +115,7 @@ static void md_reset(MicroDriveState *s)

 static uint8_t md_attr_read(void *opaque, uint32_t at)
 {
-    MicroDriveState *s = (MicroDriveState *) opaque;
+    MicroDriveState *s = opaque;
     if (at < s->attr_base) {
         if (at < s->card.cis_len)
             return s->card.cis[at];
@@ -148,7 +148,7 @@ static uint8_t md_attr_read(void *opaque, uint32_t at)

 static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
 {
-    MicroDriveState *s = (MicroDriveState *) opaque;
+    MicroDriveState *s = opaque;
     at -= s->attr_base;

     switch (at) {
@@ -179,7 +179,7 @@ static void md_attr_write(void *opaque, uint32_t at, uint8_t value)

 static uint16_t md_common_read(void *opaque, uint32_t at)
 {
-    MicroDriveState *s = (MicroDriveState *) opaque;
+    MicroDriveState *s = opaque;
     IDEState *ifs;
     uint16_t ret;
     at -= s->io_base;
@@ -241,7 +241,7 @@ static uint16_t md_common_read(void *opaque, uint32_t at)

 static void md_common_write(void *opaque, uint32_t at, uint16_t value)
 {
-    MicroDriveState *s = (MicroDriveState *) opaque;
+    MicroDriveState *s = opaque;
     at -= s->io_base;

     switch (s->opt & OPT_MODE) {
@@ -302,7 +302,7 @@ static void md_common_write(void *opaque, uint32_t at, uint16_t value)

 static void md_save(QEMUFile *f, void *opaque)
 {
-    MicroDriveState *s = (MicroDriveState *) opaque;
+    MicroDriveState *s = opaque;
     int i;

     qemu_put_8s(f, &s->opt);
@@ -321,7 +321,7 @@ static void md_save(QEMUFile *f, void *opaque)

 static int md_load(QEMUFile *f, void *opaque, int version_id)
 {
-    MicroDriveState *s = (MicroDriveState *) opaque;
+    MicroDriveState *s = opaque;
     int i;

     if (version_id != 0 && version_id != 3)
@@ -530,7 +530,7 @@ static const uint8_t dscm1xxxx_cis[0x14a] = {

 static int dscm1xxxx_attach(void *opaque)
 {
-    MicroDriveState *md = (MicroDriveState *) opaque;
+    MicroDriveState *md = opaque;
     md->card.attr_read = md_attr_read;
     md->card.attr_write = md_attr_write;
     md->card.common_read = md_common_read;
@@ -550,7 +550,7 @@ static int dscm1xxxx_attach(void *opaque)

 static int dscm1xxxx_detach(void *opaque)
 {
-    MicroDriveState *md = (MicroDriveState *) opaque;
+    MicroDriveState *md = opaque;
     md_reset(md);
     return 0;
 }
diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c
index acaa900..7a6bf32 100644
--- a/hw/ide/mmio.c
+++ b/hw/ide/mmio.c
@@ -43,7 +43,7 @@ typedef struct {

 static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
 {
-    MMIOState *s = (MMIOState*)opaque;
+    MMIOState *s = opaque;
     IDEBus *bus = s->bus;
     addr >>= s->shift;
     if (addr & 7)
@@ -55,7 +55,7 @@ static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
 static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
 	uint32_t val)
 {
-    MMIOState *s = (MMIOState*)opaque;
+    MMIOState *s = opaque;
     IDEBus *bus = s->bus;
     addr >>= s->shift;
     if (addr & 7)
@@ -78,7 +78,7 @@ static CPUWriteMemoryFunc * const mmio_ide_writes[] = {

 static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
 {
-    MMIOState *s= (MMIOState*)opaque;
+    MMIOState *s= opaque;
     IDEBus *bus = s->bus;
     return ide_status_read(bus, 0);
 }
@@ -86,7 +86,7 @@ static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
 static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
 	uint32_t val)
 {
-    MMIOState *s = (MMIOState*)opaque;
+    MMIOState *s = opaque;
     IDEBus *bus = s->bus;
     ide_cmd_write(bus, 0, val);
 }
-- 
1.6.2.5

[Qemu-devel] [PATCH 05/12] ide: create ide/pci.h for common ide pci definitions

[Juan Quintela]

Signed-off-by: Juan Quintela <quintela@redhat.com>
---
 hw/ide/pci.c |   14 +-------------
 hw/ide/pci.h |   18 ++++++++++++++++++
 2 files changed, 19 insertions(+), 13 deletions(-)
 create mode 100644 hw/ide/pci.h

diff --git a/hw/ide/pci.c b/hw/ide/pci.c
index 9d7fdd4..3e1f53b 100644
--- a/hw/ide/pci.c
+++ b/hw/ide/pci.c
@@ -31,7 +31,7 @@
 #include "sysemu.h"
 #include "dma.h"

-#include <hw/ide/internal.h>
+#include <hw/ide/pci.h>

 /***********************************************************/
 /* PCI IDE definitions */
@@ -45,18 +45,6 @@
 #define UDIDETCR0	0x73
 #define UDIDETCR1	0x7B

-#define IDE_TYPE_PIIX3   0
-#define IDE_TYPE_CMD646  1
-#define IDE_TYPE_PIIX4   2
-
-typedef struct PCIIDEState {
-    PCIDevice dev;
-    IDEBus bus[2];
-    BMDMAState bmdma[2];
-    int type; /* see IDE_TYPE_xxx */
-    uint32_t secondary;
-} PCIIDEState;
-
 static void cmd646_update_irq(PCIIDEState *d);

 static void ide_map(PCIDevice *pci_dev, int region_num,
diff --git a/hw/ide/pci.h b/hw/ide/pci.h
new file mode 100644
index 0000000..7f3f297
--- /dev/null
+++ b/hw/ide/pci.h
@@ -0,0 +1,18 @@
+#ifndef HW_IDE_PCI_H
+#define HW_IDE_PCI_H
+
+#include <hw/ide/internal.h>
+
+#define IDE_TYPE_PIIX3   0
+#define IDE_TYPE_CMD646  1
+#define IDE_TYPE_PIIX4   2
+
+typedef struct PCIIDEState {
+    PCIDevice dev;
+    IDEBus bus[2];
+    BMDMAState bmdma[2];
+    int type; /* see IDE_TYPE_xxx */
+    uint32_t secondary;
+} PCIIDEState;
+
+#endif
-- 
1.6.2.5

[Qemu-devel] [PATCH 06/12] ide: export needed ide-pci functions for split

[Juan Quintela]

Signed-off-by: Juan Quintela <quintela@redhat.com>
---
 hw/ide/pci.c |   20 ++++++++++----------
 hw/ide/pci.h |   10 ++++++++++
 2 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/hw/ide/pci.c b/hw/ide/pci.c
index 3e1f53b..27d326c 100644
--- a/hw/ide/pci.c
+++ b/hw/ide/pci.c
@@ -71,7 +71,7 @@ static void ide_map(PCIDevice *pci_dev, int region_num,
     }
 }

-static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
+void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
 {
     BMDMAState *bm = opaque;
 #ifdef DEBUG_IDE
@@ -165,7 +165,7 @@ static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
     }
 }

-static uint32_t bmdma_addr_readb(void *opaque, uint32_t addr)
+uint32_t bmdma_addr_readb(void *opaque, uint32_t addr)
 {
     BMDMAState *bm = opaque;
     uint32_t val;
@@ -176,7 +176,7 @@ static uint32_t bmdma_addr_readb(void *opaque, uint32_t addr)
     return val;
 }

-static void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val)
+void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val)
 {
     BMDMAState *bm = opaque;
     int shift = (addr & 3) * 8;
@@ -188,7 +188,7 @@ static void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val)
     bm->cur_addr = bm->addr;
 }

-static uint32_t bmdma_addr_readw(void *opaque, uint32_t addr)
+uint32_t bmdma_addr_readw(void *opaque, uint32_t addr)
 {
     BMDMAState *bm = opaque;
     uint32_t val;
@@ -199,7 +199,7 @@ static uint32_t bmdma_addr_readw(void *opaque, uint32_t addr)
     return val;
 }

-static void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val)
+void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val)
 {
     BMDMAState *bm = opaque;
     int shift = (addr & 3) * 8;
@@ -211,7 +211,7 @@ static void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val)
     bm->cur_addr = bm->addr;
 }

-static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
+uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
 {
     BMDMAState *bm = opaque;
     uint32_t val;
@@ -222,7 +222,7 @@ static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
     return val;
 }

-static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
+void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
 {
     BMDMAState *bm = opaque;
 #ifdef DEBUG_IDE
@@ -260,7 +260,7 @@ static void bmdma_map(PCIDevice *pci_dev, int region_num,
     }
 }

-static void pci_ide_save(QEMUFile* f, void *opaque)
+void pci_ide_save(QEMUFile* f, void *opaque)
 {
     PCIIDEState *d = opaque;
     int i;
@@ -292,7 +292,7 @@ static void pci_ide_save(QEMUFile* f, void *opaque)
     }
 }

-static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
+int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
 {
     PCIIDEState *d = opaque;
     int ret, i;
@@ -329,7 +329,7 @@ static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
     return 0;
 }

-static void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
+void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
 {
     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
     static const int bus[4]  = { 0, 0, 1, 1 };
diff --git a/hw/ide/pci.h b/hw/ide/pci.h
index 7f3f297..063ae96 100644
--- a/hw/ide/pci.h
+++ b/hw/ide/pci.h
@@ -15,4 +15,14 @@ typedef struct PCIIDEState {
     uint32_t secondary;
 } PCIIDEState;

+void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val);
+uint32_t bmdma_addr_readb(void *opaque, uint32_t addr);
+void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val);
+uint32_t bmdma_addr_readw(void *opaque, uint32_t addr);
+void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val);
+uint32_t bmdma_addr_readl(void *opaque, uint32_t addr);
+void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val);
+void pci_ide_save(QEMUFile* f, void *opaque);
+int pci_ide_load(QEMUFile* f, void *opaque, int version_id);
+void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table);
 #endif
-- 
1.6.2.5

[Qemu-devel] [PATCH 07/12] ide: split cmd646 and piix from pci.c

[Juan Quintela]

This patch splits cmd646 specific code from pci.c.
This patch splits piix4 specific code from pci.c.
And compile new piix.o and cmd646.o when they are needed.
The only change that is not code movemet is removal of cmd646 specific parts
in bmdma_readb/writeb for piix.

Signed-off-by: Juan Quintela <quintela@redhat.com>
---
 Makefile.target |    7 +-
 hw/ide/cmd646.c |  280 +++++++++++++++++++++++++++++++++++++++++++++
 hw/ide/pci.c    |  338 -------------------------------------------------------
 hw/ide/piix.c   |  198 ++++++++++++++++++++++++++++++++
 4 files changed, 482 insertions(+), 341 deletions(-)
 create mode 100644 hw/ide/cmd646.c
 create mode 100644 hw/ide/piix.c

diff --git a/Makefile.target b/Makefile.target
index 1f4518c..8d87cf5 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -179,7 +179,7 @@ obj-y += rtl8139.o
 obj-y += e1000.o

 # Hardware support
-obj-i386-y = ide/core.o ide/qdev.o ide/isa.o ide/pci.o
+obj-i386-y = ide/core.o ide/qdev.o ide/isa.o ide/pci.o ide/piix.o
 obj-i386-y += pckbd.o $(sound-obj-y) dma.o
 obj-i386-y += vga.o vga-pci.o vga-isa.o
 obj-i386-y += fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o
@@ -190,6 +190,7 @@ obj-i386-y += ne2000-isa.o

 # shared objects
 obj-ppc-y = ppc.o ide/core.o ide/qdev.o ide/isa.o ide/pci.o ide/macio.o
+obj-ppc-y += ide/cmd646.o
 obj-ppc-y += vga.o vga-pci.o $(sound-obj-y) dma.o openpic.o
 # PREP target
 obj-ppc-y += pckbd.o serial.o i8259.o i8254.o fdc.o mc146818rtc.o
@@ -212,7 +213,7 @@ obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
 obj-mips-y += mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o rc4030.o
 obj-mips-y += vga-pci.o vga-isa.o vga-isa-mm.o
 obj-mips-y += g364fb.o jazz_led.o dp8393x.o
-obj-mips-y += ide/core.o ide/qdev.o ide/isa.o ide/pci.o
+obj-mips-y += ide/core.o ide/qdev.o ide/isa.o ide/pci.o ide/piix.o
 obj-mips-y += gt64xxx.o pckbd.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
 obj-mips-y += piix4.o parallel.o cirrus_vga.o pcspk.o $(sound-obj-y)
 obj-mips-y += mipsnet.o ne2000-isa.o
@@ -245,7 +246,7 @@ obj-cris-y += pflash_cfi02.o

 ifeq ($(TARGET_ARCH), sparc64)
 obj-sparc-y = sun4u.o pckbd.o apb_pci.o
-obj-sparc-y += ide/core.o ide/qdev.o ide/pci.o
+obj-sparc-y += ide/core.o ide/qdev.o ide/pci.o ide/cmd646.o
 obj-sparc-y += vga.o vga-pci.o
 obj-sparc-y += fdc.o mc146818rtc.o serial.o
 obj-sparc-y += cirrus_vga.o parallel.o
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
new file mode 100644
index 0000000..a700be2
--- /dev/null
+++ b/hw/ide/cmd646.c
@@ -0,0 +1,280 @@
+/*
+ * QEMU IDE Emulation: PCI cmd646 support.
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2006 Openedhand Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include <hw/hw.h>
+#include <hw/pc.h>
+#include <hw/pci.h>
+#include <hw/isa.h>
+#include "block.h"
+#include "block_int.h"
+#include "sysemu.h"
+#include "dma.h"
+
+#include <hw/ide/pci.h>
+
+/* CMD646 specific */
+#define MRDMODE		0x71
+#define   MRDMODE_INTR_CH0	0x04
+#define   MRDMODE_INTR_CH1	0x08
+#define   MRDMODE_BLK_CH0	0x10
+#define   MRDMODE_BLK_CH1	0x20
+#define UDIDETCR0	0x73
+#define UDIDETCR1	0x7B
+
+static void cmd646_update_irq(PCIIDEState *d);
+
+static void ide_map(PCIDevice *pci_dev, int region_num,
+                    uint32_t addr, uint32_t size, int type)
+{
+    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
+    IDEBus *bus;
+
+    if (region_num <= 3) {
+        bus = &d->bus[(region_num >> 1)];
+        if (region_num & 1) {
+            register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
+            register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
+        } else {
+            register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
+            register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
+
+            /* data ports */
+            register_ioport_write(addr, 2, 2, ide_data_writew, bus);
+            register_ioport_read(addr, 2, 2, ide_data_readw, bus);
+            register_ioport_write(addr, 4, 4, ide_data_writel, bus);
+            register_ioport_read(addr, 4, 4, ide_data_readl, bus);
+        }
+    }
+}
+
+static uint32_t bmdma_readb(void *opaque, uint32_t addr)
+{
+    BMDMAState *bm = opaque;
+    PCIIDEState *pci_dev;
+    uint32_t val;
+
+    switch(addr & 3) {
+    case 0:
+        val = bm->cmd;
+        break;
+    case 1:
+        pci_dev = bm->pci_dev;
+        if (pci_dev->type == IDE_TYPE_CMD646) {
+            val = pci_dev->dev.config[MRDMODE];
+        } else {
+            val = 0xff;
+        }
+        break;
+    case 2:
+        val = bm->status;
+        break;
+    case 3:
+        pci_dev = bm->pci_dev;
+        if (pci_dev->type == IDE_TYPE_CMD646) {
+            if (bm == &pci_dev->bmdma[0])
+                val = pci_dev->dev.config[UDIDETCR0];
+            else
+                val = pci_dev->dev.config[UDIDETCR1];
+        } else {
+            val = 0xff;
+        }
+        break;
+    default:
+        val = 0xff;
+        break;
+    }
+#ifdef DEBUG_IDE
+    printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
+#endif
+    return val;
+}
+
+static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+    BMDMAState *bm = opaque;
+    PCIIDEState *pci_dev;
+#ifdef DEBUG_IDE
+    printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
+#endif
+    switch(addr & 3) {
+    case 1:
+        pci_dev = bm->pci_dev;
+        if (pci_dev->type == IDE_TYPE_CMD646) {
+            pci_dev->dev.config[MRDMODE] =
+                (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
+            cmd646_update_irq(pci_dev);
+        }
+        break;
+    case 2:
+        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
+        break;
+    case 3:
+        pci_dev = bm->pci_dev;
+        if (pci_dev->type == IDE_TYPE_CMD646) {
+            if (bm == &pci_dev->bmdma[0])
+                pci_dev->dev.config[UDIDETCR0] = val;
+            else
+                pci_dev->dev.config[UDIDETCR1] = val;
+        }
+        break;
+    }
+}
+
+static void bmdma_map(PCIDevice *pci_dev, int region_num,
+                    uint32_t addr, uint32_t size, int type)
+{
+    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
+    int i;
+
+    for(i = 0;i < 2; i++) {
+        BMDMAState *bm = &d->bmdma[i];
+        d->bus[i].bmdma = bm;
+        bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev);
+        bm->bus = d->bus+i;
+        qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
+
+        register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
+
+        register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
+        register_ioport_read(addr, 4, 1, bmdma_readb, bm);
+
+        register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
+        register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
+        register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
+        register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
+        register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
+        register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
+        addr += 8;
+    }
+}
+
+/* XXX: call it also when the MRDMODE is changed from the PCI config
+   registers */
+static void cmd646_update_irq(PCIIDEState *d)
+{
+    int pci_level;
+    pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
+                 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
+        ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
+         !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
+    qemu_set_irq(d->dev.irq[0], pci_level);
+}
+
+/* the PCI irq level is the logical OR of the two channels */
+static void cmd646_set_irq(void *opaque, int channel, int level)
+{
+    PCIIDEState *d = opaque;
+    int irq_mask;
+
+    irq_mask = MRDMODE_INTR_CH0 << channel;
+    if (level)
+        d->dev.config[MRDMODE] |= irq_mask;
+    else
+        d->dev.config[MRDMODE] &= ~irq_mask;
+    cmd646_update_irq(d);
+}
+
+static void cmd646_reset(void *opaque)
+{
+    PCIIDEState *d = opaque;
+    unsigned int i;
+
+    for (i = 0; i < 2; i++)
+        ide_dma_cancel(&d->bmdma[i]);
+}
+
+/* CMD646 PCI IDE controller */
+static int pci_cmd646_ide_initfn(PCIDevice *dev)
+{
+    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
+    uint8_t *pci_conf = d->dev.config;
+    qemu_irq *irq;
+
+    d->type = IDE_TYPE_CMD646;
+    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD);
+    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646);
+
+    pci_conf[0x08] = 0x07; // IDE controller revision
+    pci_conf[0x09] = 0x8f;
+
+    pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
+    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
+
+    pci_conf[0x51] = 0x04; // enable IDE0
+    if (d->secondary) {
+        /* XXX: if not enabled, really disable the seconday IDE controller */
+        pci_conf[0x51] |= 0x08; /* enable IDE1 */
+    }
+
+    pci_register_bar(dev, 0, 0x8, PCI_ADDRESS_SPACE_IO, ide_map);
+    pci_register_bar(dev, 1, 0x4, PCI_ADDRESS_SPACE_IO, ide_map);
+    pci_register_bar(dev, 2, 0x8, PCI_ADDRESS_SPACE_IO, ide_map);
+    pci_register_bar(dev, 3, 0x4, PCI_ADDRESS_SPACE_IO, ide_map);
+    pci_register_bar(dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map);
+
+    pci_conf[0x3d] = 0x01; // interrupt on pin 1
+
+    irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
+    ide_bus_new(&d->bus[0], &d->dev.qdev);
+    ide_bus_new(&d->bus[1], &d->dev.qdev);
+    ide_init2(&d->bus[0], NULL, NULL, irq[0]);
+    ide_init2(&d->bus[1], NULL, NULL, irq[1]);
+
+    register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
+    qemu_register_reset(cmd646_reset, d);
+    cmd646_reset(d);
+    return 0;
+}
+
+void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
+                         int secondary_ide_enabled)
+{
+    PCIDevice *dev;
+
+    dev = pci_create(bus, -1, "CMD646 IDE");
+    qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
+    qdev_init(&dev->qdev);
+
+    pci_ide_create_devs(dev, hd_table);
+}
+
+static PCIDeviceInfo cmd646_ide_info[] = {
+    {
+        .qdev.name    = "CMD646 IDE",
+        .qdev.size    = sizeof(PCIIDEState),
+        .init         = pci_cmd646_ide_initfn,
+        .qdev.props   = (Property[]) {
+            DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
+            DEFINE_PROP_END_OF_LIST(),
+        },
+    },{
+        /* end of list */
+    }
+};
+
+static void cmd646_ide_register(void)
+{
+    pci_qdev_register_many(cmd646_ide_info);
+}
+device_init(cmd646_ide_register);
diff --git a/hw/ide/pci.c b/hw/ide/pci.c
index 27d326c..dea126a 100644
--- a/hw/ide/pci.c
+++ b/hw/ide/pci.c
@@ -33,44 +33,6 @@

 #include <hw/ide/pci.h>

-/***********************************************************/
-/* PCI IDE definitions */
-
-/* CMD646 specific */
-#define MRDMODE		0x71
-#define   MRDMODE_INTR_CH0	0x04
-#define   MRDMODE_INTR_CH1	0x08
-#define   MRDMODE_BLK_CH0	0x10
-#define   MRDMODE_BLK_CH1	0x20
-#define UDIDETCR0	0x73
-#define UDIDETCR1	0x7B
-
-static void cmd646_update_irq(PCIIDEState *d);
-
-static void ide_map(PCIDevice *pci_dev, int region_num,
-                    uint32_t addr, uint32_t size, int type)
-{
-    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
-    IDEBus *bus;
-
-    if (region_num <= 3) {
-        bus = &d->bus[(region_num >> 1)];
-        if (region_num & 1) {
-            register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
-            register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
-        } else {
-            register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
-            register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
-
-            /* data ports */
-            register_ioport_write(addr, 2, 2, ide_data_writew, bus);
-            register_ioport_read(addr, 2, 2, ide_data_readw, bus);
-            register_ioport_write(addr, 4, 4, ide_data_writel, bus);
-            register_ioport_read(addr, 4, 4, ide_data_readl, bus);
-        }
-    }
-}
-
 void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
 {
     BMDMAState *bm = opaque;
@@ -92,79 +54,6 @@ void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
     }
 }

-static uint32_t bmdma_readb(void *opaque, uint32_t addr)
-{
-    BMDMAState *bm = opaque;
-    PCIIDEState *pci_dev;
-    uint32_t val;
-
-    switch(addr & 3) {
-    case 0:
-        val = bm->cmd;
-        break;
-    case 1:
-        pci_dev = bm->pci_dev;
-        if (pci_dev->type == IDE_TYPE_CMD646) {
-            val = pci_dev->dev.config[MRDMODE];
-        } else {
-            val = 0xff;
-        }
-        break;
-    case 2:
-        val = bm->status;
-        break;
-    case 3:
-        pci_dev = bm->pci_dev;
-        if (pci_dev->type == IDE_TYPE_CMD646) {
-            if (bm == &pci_dev->bmdma[0])
-                val = pci_dev->dev.config[UDIDETCR0];
-            else
-                val = pci_dev->dev.config[UDIDETCR1];
-        } else {
-            val = 0xff;
-        }
-        break;
-    default:
-        val = 0xff;
-        break;
-    }
-#ifdef DEBUG_IDE
-    printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
-#endif
-    return val;
-}
-
-static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
-{
-    BMDMAState *bm = opaque;
-    PCIIDEState *pci_dev;
-#ifdef DEBUG_IDE
-    printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
-#endif
-    switch(addr & 3) {
-    case 1:
-        pci_dev = bm->pci_dev;
-        if (pci_dev->type == IDE_TYPE_CMD646) {
-            pci_dev->dev.config[MRDMODE] =
-                (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
-            cmd646_update_irq(pci_dev);
-        }
-        break;
-    case 2:
-        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
-        break;
-    case 3:
-        pci_dev = bm->pci_dev;
-        if (pci_dev->type == IDE_TYPE_CMD646) {
-            if (bm == &pci_dev->bmdma[0])
-                pci_dev->dev.config[UDIDETCR0] = val;
-            else
-                pci_dev->dev.config[UDIDETCR1] = val;
-        }
-        break;
-    }
-}
-
 uint32_t bmdma_addr_readb(void *opaque, uint32_t addr)
 {
     BMDMAState *bm = opaque;
@@ -232,34 +121,6 @@ void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
     bm->cur_addr = bm->addr;
 }

-static void bmdma_map(PCIDevice *pci_dev, int region_num,
-                    uint32_t addr, uint32_t size, int type)
-{
-    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
-    int i;
-
-    for(i = 0;i < 2; i++) {
-        BMDMAState *bm = &d->bmdma[i];
-        d->bus[i].bmdma = bm;
-        bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev);
-        bm->bus = d->bus+i;
-        qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
-
-        register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
-
-        register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
-        register_ioport_read(addr, 4, 1, bmdma_readb, bm);
-
-        register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
-        register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
-        register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
-        register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
-        register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
-        register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
-        addr += 8;
-    }
-}
-
 void pci_ide_save(QEMUFile* f, void *opaque)
 {
     PCIIDEState *d = opaque;
@@ -342,202 +203,3 @@ void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
         ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
     }
 }
-
-/* XXX: call it also when the MRDMODE is changed from the PCI config
-   registers */
-static void cmd646_update_irq(PCIIDEState *d)
-{
-    int pci_level;
-    pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
-                 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
-        ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
-         !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
-    qemu_set_irq(d->dev.irq[0], pci_level);
-}
-
-/* the PCI irq level is the logical OR of the two channels */
-static void cmd646_set_irq(void *opaque, int channel, int level)
-{
-    PCIIDEState *d = opaque;
-    int irq_mask;
-
-    irq_mask = MRDMODE_INTR_CH0 << channel;
-    if (level)
-        d->dev.config[MRDMODE] |= irq_mask;
-    else
-        d->dev.config[MRDMODE] &= ~irq_mask;
-    cmd646_update_irq(d);
-}
-
-static void cmd646_reset(void *opaque)
-{
-    PCIIDEState *d = opaque;
-    unsigned int i;
-
-    for (i = 0; i < 2; i++)
-        ide_dma_cancel(&d->bmdma[i]);
-}
-
-/* CMD646 PCI IDE controller */
-static int pci_cmd646_ide_initfn(PCIDevice *dev)
-{
-    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
-    uint8_t *pci_conf = d->dev.config;
-    qemu_irq *irq;
-
-    d->type = IDE_TYPE_CMD646;
-    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD);
-    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646);
-
-    pci_conf[0x08] = 0x07; // IDE controller revision
-    pci_conf[0x09] = 0x8f;
-
-    pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
-    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
-
-    pci_conf[0x51] = 0x04; // enable IDE0
-    if (d->secondary) {
-        /* XXX: if not enabled, really disable the seconday IDE controller */
-        pci_conf[0x51] |= 0x08; /* enable IDE1 */
-    }
-
-    pci_register_bar(dev, 0, 0x8, PCI_ADDRESS_SPACE_IO, ide_map);
-    pci_register_bar(dev, 1, 0x4, PCI_ADDRESS_SPACE_IO, ide_map);
-    pci_register_bar(dev, 2, 0x8, PCI_ADDRESS_SPACE_IO, ide_map);
-    pci_register_bar(dev, 3, 0x4, PCI_ADDRESS_SPACE_IO, ide_map);
-    pci_register_bar(dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map);
-
-    pci_conf[0x3d] = 0x01; // interrupt on pin 1
-
-    irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
-    ide_bus_new(&d->bus[0], &d->dev.qdev);
-    ide_bus_new(&d->bus[1], &d->dev.qdev);
-    ide_init2(&d->bus[0], NULL, NULL, irq[0]);
-    ide_init2(&d->bus[1], NULL, NULL, irq[1]);
-
-    register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
-    qemu_register_reset(cmd646_reset, d);
-    cmd646_reset(d);
-    return 0;
-}
-
-void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
-                         int secondary_ide_enabled)
-{
-    PCIDevice *dev;
-
-    dev = pci_create(bus, -1, "CMD646 IDE");
-    qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
-    qdev_init(&dev->qdev);
-
-    pci_ide_create_devs(dev, hd_table);
-}
-
-static void piix3_reset(void *opaque)
-{
-    PCIIDEState *d = opaque;
-    uint8_t *pci_conf = d->dev.config;
-    int i;
-
-    for (i = 0; i < 2; i++)
-        ide_dma_cancel(&d->bmdma[i]);
-
-    pci_conf[0x04] = 0x00;
-    pci_conf[0x05] = 0x00;
-    pci_conf[0x06] = 0x80; /* FBC */
-    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
-    pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
-}
-
-static int pci_piix_ide_initfn(PCIIDEState *d)
-{
-    uint8_t *pci_conf = d->dev.config;
-
-    pci_conf[0x09] = 0x80; // legacy ATA mode
-    pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
-    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
-
-    qemu_register_reset(piix3_reset, d);
-    piix3_reset(d);
-
-    pci_register_bar(&d->dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map);
-
-    register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
-
-    ide_bus_new(&d->bus[0], &d->dev.qdev);
-    ide_bus_new(&d->bus[1], &d->dev.qdev);
-    ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
-    ide_init_ioport(&d->bus[1], 0x170, 0x376);
-
-    ide_init2(&d->bus[0], NULL, NULL, isa_reserve_irq(14));
-    ide_init2(&d->bus[1], NULL, NULL, isa_reserve_irq(15));
-    return 0;
-}
-
-static int pci_piix3_ide_initfn(PCIDevice *dev)
-{
-    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
-
-    d->type = IDE_TYPE_PIIX3;
-    pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
-    pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371SB_1);
-    return pci_piix_ide_initfn(d);
-}
-
-static int pci_piix4_ide_initfn(PCIDevice *dev)
-{
-    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
-
-    d->type = IDE_TYPE_PIIX4;
-    pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
-    pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371AB);
-    return pci_piix_ide_initfn(d);
-}
-
-/* hd_table must contain 4 block drivers */
-/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
-void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
-{
-    PCIDevice *dev;
-
-    dev = pci_create_simple(bus, devfn, "PIIX3 IDE");
-    pci_ide_create_devs(dev, hd_table);
-}
-
-/* hd_table must contain 4 block drivers */
-/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
-void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
-{
-    PCIDevice *dev;
-
-    dev = pci_create_simple(bus, devfn, "PIIX4 IDE");
-    pci_ide_create_devs(dev, hd_table);
-}
-
-static PCIDeviceInfo piix_ide_info[] = {
-    {
-        .qdev.name    = "PIIX3 IDE",
-        .qdev.size    = sizeof(PCIIDEState),
-        .init         = pci_piix3_ide_initfn,
-    },{
-        .qdev.name    = "PIIX4 IDE",
-        .qdev.size    = sizeof(PCIIDEState),
-        .init         = pci_piix4_ide_initfn,
-    },{
-        .qdev.name    = "CMD646 IDE",
-        .qdev.size    = sizeof(PCIIDEState),
-        .init         = pci_cmd646_ide_initfn,
-        .qdev.props   = (Property[]) {
-            DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
-            DEFINE_PROP_END_OF_LIST(),
-        },
-    },{
-        /* end of list */
-    }
-};
-
-static void piix_ide_register(void)
-{
-    pci_qdev_register_many(piix_ide_info);
-}
-device_init(piix_ide_register);
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
new file mode 100644
index 0000000..47d736d
--- /dev/null
+++ b/hw/ide/piix.c
@@ -0,0 +1,198 @@
+/*
+ * QEMU IDE Emulation: PCI PIIX3/4 support.
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2006 Openedhand Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include <hw/hw.h>
+#include <hw/pc.h>
+#include <hw/pci.h>
+#include <hw/isa.h>
+#include "block.h"
+#include "block_int.h"
+#include "sysemu.h"
+#include "dma.h"
+
+#include <hw/ide/pci.h>
+
+static uint32_t bmdma_readb(void *opaque, uint32_t addr)
+{
+    BMDMAState *bm = opaque;
+    uint32_t val;
+
+    switch(addr & 3) {
+    case 0:
+        val = bm->cmd;
+        break;
+    case 2:
+        val = bm->status;
+        break;
+    default:
+        val = 0xff;
+        break;
+    }
+#ifdef DEBUG_IDE
+    printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
+#endif
+    return val;
+}
+
+static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+    BMDMAState *bm = opaque;
+#ifdef DEBUG_IDE
+    printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
+#endif
+    switch(addr & 3) {
+    case 2:
+        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
+        break;
+    }
+}
+
+static void bmdma_map(PCIDevice *pci_dev, int region_num,
+                    uint32_t addr, uint32_t size, int type)
+{
+    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
+    int i;
+
+    for(i = 0;i < 2; i++) {
+        BMDMAState *bm = &d->bmdma[i];
+        d->bus[i].bmdma = bm;
+        bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev);
+        bm->bus = d->bus+i;
+        qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
+
+        register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
+
+        register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
+        register_ioport_read(addr, 4, 1, bmdma_readb, bm);
+
+        register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
+        register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
+        register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
+        register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
+        register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
+        register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
+        addr += 8;
+    }
+}
+
+static void piix3_reset(void *opaque)
+{
+    PCIIDEState *d = opaque;
+    uint8_t *pci_conf = d->dev.config;
+    int i;
+
+    for (i = 0; i < 2; i++)
+        ide_dma_cancel(&d->bmdma[i]);
+
+    pci_conf[0x04] = 0x00;
+    pci_conf[0x05] = 0x00;
+    pci_conf[0x06] = 0x80; /* FBC */
+    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
+    pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
+}
+
+static int pci_piix_ide_initfn(PCIIDEState *d)
+{
+    uint8_t *pci_conf = d->dev.config;
+
+    pci_conf[0x09] = 0x80; // legacy ATA mode
+    pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
+    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
+
+    qemu_register_reset(piix3_reset, d);
+    piix3_reset(d);
+
+    pci_register_bar(&d->dev, 4, 0x10, PCI_ADDRESS_SPACE_IO, bmdma_map);
+
+    register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
+
+    ide_bus_new(&d->bus[0], &d->dev.qdev);
+    ide_bus_new(&d->bus[1], &d->dev.qdev);
+    ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
+    ide_init_ioport(&d->bus[1], 0x170, 0x376);
+
+    ide_init2(&d->bus[0], NULL, NULL, isa_reserve_irq(14));
+    ide_init2(&d->bus[1], NULL, NULL, isa_reserve_irq(15));
+    return 0;
+}
+
+static int pci_piix3_ide_initfn(PCIDevice *dev)
+{
+    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
+
+    d->type = IDE_TYPE_PIIX3;
+    pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
+    pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371SB_1);
+    return pci_piix_ide_initfn(d);
+}
+
+static int pci_piix4_ide_initfn(PCIDevice *dev)
+{
+    PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
+
+    d->type = IDE_TYPE_PIIX4;
+    pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
+    pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371AB);
+    return pci_piix_ide_initfn(d);
+}
+
+/* hd_table must contain 4 block drivers */
+/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
+void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
+{
+    PCIDevice *dev;
+
+    dev = pci_create_simple(bus, devfn, "PIIX3 IDE");
+    pci_ide_create_devs(dev, hd_table);
+}
+
+/* hd_table must contain 4 block drivers */
+/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
+void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
+{
+    PCIDevice *dev;
+
+    dev = pci_create_simple(bus, devfn, "PIIX4 IDE");
+    pci_ide_create_devs(dev, hd_table);
+}
+
+static PCIDeviceInfo piix_ide_info[] = {
+    {
+        .qdev.name    = "PIIX3 IDE",
+        .qdev.size    = sizeof(PCIIDEState),
+        .init         = pci_piix3_ide_initfn,
+    },{
+        .qdev.name    = "PIIX4 IDE",
+        .qdev.size    = sizeof(PCIIDEState),
+        .init         = pci_piix4_ide_initfn,
+    },{
+        /* end of list */
+    }
+};
+
+static void piix_ide_register(void)
+{
+    pci_qdev_register_many(piix_ide_info);
+}
+device_init(piix_ide_register);
-- 
1.6.2.5

[Qemu-devel] [PATCH 08/12] ide: PCIIDEState type field is not needed anymore

[Juan Quintela]

We have split the functions that needed it for cmd646

Signed-off-by: Juan Quintela <quintela@redhat.com>
---
 hw/ide/cmd646.c |   34 +++++++++++-----------------------
 hw/ide/pci.h    |    5 -----
 hw/ide/piix.c   |    2 --
 3 files changed, 11 insertions(+), 30 deletions(-)

diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index a700be2..37cfe01 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -80,24 +80,17 @@ static uint32_t bmdma_readb(void *opaque, uint32_t addr)
         break;
     case 1:
         pci_dev = bm->pci_dev;
-        if (pci_dev->type == IDE_TYPE_CMD646) {
-            val = pci_dev->dev.config[MRDMODE];
-        } else {
-            val = 0xff;
-        }
+        val = pci_dev->dev.config[MRDMODE];
         break;
     case 2:
         val = bm->status;
         break;
     case 3:
         pci_dev = bm->pci_dev;
-        if (pci_dev->type == IDE_TYPE_CMD646) {
-            if (bm == &pci_dev->bmdma[0])
-                val = pci_dev->dev.config[UDIDETCR0];
-            else
-                val = pci_dev->dev.config[UDIDETCR1];
+        if (bm == &pci_dev->bmdma[0]) {
+            val = pci_dev->dev.config[UDIDETCR0];
         } else {
-            val = 0xff;
+            val = pci_dev->dev.config[UDIDETCR1];
         }
         break;
     default:
@@ -120,23 +113,19 @@ static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
     switch(addr & 3) {
     case 1:
         pci_dev = bm->pci_dev;
-        if (pci_dev->type == IDE_TYPE_CMD646) {
-            pci_dev->dev.config[MRDMODE] =
-                (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
-            cmd646_update_irq(pci_dev);
-        }
+        pci_dev->dev.config[MRDMODE] =
+            (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
+        cmd646_update_irq(pci_dev);
         break;
     case 2:
         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
         break;
     case 3:
         pci_dev = bm->pci_dev;
-        if (pci_dev->type == IDE_TYPE_CMD646) {
-            if (bm == &pci_dev->bmdma[0])
-                pci_dev->dev.config[UDIDETCR0] = val;
-            else
-                pci_dev->dev.config[UDIDETCR1] = val;
-        }
+        if (bm == &pci_dev->bmdma[0])
+            pci_dev->dev.config[UDIDETCR0] = val;
+        else
+            pci_dev->dev.config[UDIDETCR1] = val;
         break;
     }
 }
@@ -211,7 +200,6 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)
     uint8_t *pci_conf = d->dev.config;
     qemu_irq *irq;

-    d->type = IDE_TYPE_CMD646;
     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD);
     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646);

diff --git a/hw/ide/pci.h b/hw/ide/pci.h
index 063ae96..690d057 100644
--- a/hw/ide/pci.h
+++ b/hw/ide/pci.h
@@ -3,15 +3,10 @@

 #include <hw/ide/internal.h>

-#define IDE_TYPE_PIIX3   0
-#define IDE_TYPE_CMD646  1
-#define IDE_TYPE_PIIX4   2
-
 typedef struct PCIIDEState {
     PCIDevice dev;
     IDEBus bus[2];
     BMDMAState bmdma[2];
-    int type; /* see IDE_TYPE_xxx */
     uint32_t secondary;
 } PCIIDEState;

diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index 47d736d..4583c42 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -141,7 +141,6 @@ static int pci_piix3_ide_initfn(PCIDevice *dev)
 {
     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);

-    d->type = IDE_TYPE_PIIX3;
     pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
     pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371SB_1);
     return pci_piix_ide_initfn(d);
@@ -151,7 +150,6 @@ static int pci_piix4_ide_initfn(PCIDevice *dev)
 {
     PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);

-    d->type = IDE_TYPE_PIIX4;
     pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
     pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371AB);
     return pci_piix_ide_initfn(d);
-- 
1.6.2.5

[Qemu-devel] [PATCH 09/12] ide: 'secondary' field is only used by cmd646

[Juan Quintela]

Signed-off-by: Juan Quintela <quintela@redhat.com>
---
 hw/ide/pci.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/hw/ide/pci.h b/hw/ide/pci.h
index 690d057..9377503 100644
--- a/hw/ide/pci.h
+++ b/hw/ide/pci.h
@@ -7,7 +7,7 @@ typedef struct PCIIDEState {
     PCIDevice dev;
     IDEBus bus[2];
     BMDMAState bmdma[2];
-    uint32_t secondary;
+    uint32_t secondary; /* used only for cmd646 */
 } PCIIDEState;

 void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val);
-- 
1.6.2.5

[Qemu-devel] [PATCH 10/12] ide: cmd646 we can get the pci device with container_of

[Juan Quintela]

Signed-off-by: Juan Quintela <quintela@redhat.com>
---
 hw/ide/cmd646.c |   17 +++++++++++------
 1 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index 37cfe01..a36c3b5 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -68,10 +68,19 @@ static void ide_map(PCIDevice *pci_dev, int region_num,
     }
 }

+static PCIIDEState *pci_from_bm(BMDMAState *bm)
+{
+    if (bm->unit == 0) {
+        return container_of(bm, PCIIDEState, bmdma[0]);
+    } else {
+        return container_of(bm, PCIIDEState, bmdma[1]);
+    }
+}
+
 static uint32_t bmdma_readb(void *opaque, uint32_t addr)
 {
     BMDMAState *bm = opaque;
-    PCIIDEState *pci_dev;
+    PCIIDEState *pci_dev = pci_from_bm(bm);
     uint32_t val;

     switch(addr & 3) {
@@ -79,14 +88,12 @@ static uint32_t bmdma_readb(void *opaque, uint32_t addr)
         val = bm->cmd;
         break;
     case 1:
-        pci_dev = bm->pci_dev;
         val = pci_dev->dev.config[MRDMODE];
         break;
     case 2:
         val = bm->status;
         break;
     case 3:
-        pci_dev = bm->pci_dev;
         if (bm == &pci_dev->bmdma[0]) {
             val = pci_dev->dev.config[UDIDETCR0];
         } else {
@@ -106,13 +113,12 @@ static uint32_t bmdma_readb(void *opaque, uint32_t addr)
 static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
 {
     BMDMAState *bm = opaque;
-    PCIIDEState *pci_dev;
+    PCIIDEState *pci_dev = pci_from_bm(bm);
 #ifdef DEBUG_IDE
     printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
 #endif
     switch(addr & 3) {
     case 1:
-        pci_dev = bm->pci_dev;
         pci_dev->dev.config[MRDMODE] =
             (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
         cmd646_update_irq(pci_dev);
@@ -121,7 +127,6 @@ static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
         break;
     case 3:
-        pci_dev = bm->pci_dev;
         if (bm == &pci_dev->bmdma[0])
             pci_dev->dev.config[UDIDETCR0] = val;
         else
-- 
1.6.2.5

[Qemu-devel] [PATCH 11/12] ide: cmd646 ->unit has just the value that we want

[Juan Quintela]

Signed-off-by: Juan Quintela <quintela@redhat.com>
---
 hw/ide/cmd646.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index a36c3b5..4af1954 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -94,7 +94,7 @@ static uint32_t bmdma_readb(void *opaque, uint32_t addr)
         val = bm->status;
         break;
     case 3:
-        if (bm == &pci_dev->bmdma[0]) {
+        if (bm->unit == 0) {
             val = pci_dev->dev.config[UDIDETCR0];
         } else {
             val = pci_dev->dev.config[UDIDETCR1];
@@ -127,7 +127,7 @@ static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
         break;
     case 3:
-        if (bm == &pci_dev->bmdma[0])
+        if (bm->unit == 0)
             pci_dev->dev.config[UDIDETCR0] = val;
         else
             pci_dev->dev.config[UDIDETCR1] = val;
-- 
1.6.2.5

[Qemu-devel] [PATCH 12/12] ide: BMDMAState don't need a pci_dev field anymore

[Juan Quintela]

Signed-off-by: Juan Quintela <quintela@redhat.com>
---
 hw/ide/cmd646.c   |    1 -
 hw/ide/internal.h |    1 -
 hw/ide/piix.c     |    1 -
 3 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index 4af1954..e62949e 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -144,7 +144,6 @@ static void bmdma_map(PCIDevice *pci_dev, int region_num,
     for(i = 0;i < 2; i++) {
         BMDMAState *bm = &d->bmdma[i];
         d->bus[i].bmdma = bm;
-        bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev);
         bm->bus = d->bus+i;
         qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);

diff --git a/hw/ide/internal.h b/hw/ide/internal.h
index 21319fe..2e40431 100644
--- a/hw/ide/internal.h
+++ b/hw/ide/internal.h
@@ -473,7 +473,6 @@ struct BMDMAState {
     uint8_t status;
     uint32_t addr;

-    struct PCIIDEState *pci_dev;
     IDEBus *bus;
     /* current transfer state */
     uint32_t cur_addr;
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index 4583c42..ddce684 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -77,7 +77,6 @@ static void bmdma_map(PCIDevice *pci_dev, int region_num,
     for(i = 0;i < 2; i++) {
         BMDMAState *bm = &d->bmdma[i];
         d->bus[i].bmdma = bm;
-        bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev);
         bm->bus = d->bus+i;
         qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);

-- 
1.6.2.5