From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NUQGp-0005IB-1y for qemu-devel@nongnu.org; Mon, 11 Jan 2010 14:49:47 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NUQGm-0005Fn-RW for qemu-devel@nongnu.org; Mon, 11 Jan 2010 14:49:45 -0500 Received: from [199.232.76.173] (port=33986 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NUQGm-0005FP-7n for qemu-devel@nongnu.org; Mon, 11 Jan 2010 14:49:44 -0500 Received: from are.twiddle.net ([75.149.56.221]:34142) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NUQGl-0002z7-IQ for qemu-devel@nongnu.org; Mon, 11 Jan 2010 14:49:43 -0500 Message-Id: From: Richard Henderson Date: Mon, 11 Jan 2010 11:22:06 -0800 Subject: [Qemu-devel] [PATCH 0/5] tcg-sparc improvements List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com As noticed elsewhere on the list mulu2_i32 is missing. Which led me to notice that add2_i32 and sub2_i32 were also missing and also led me to notice that division was incorrectly implemented. My initial implementation of 32-bit division copied the existing practice of using the 64-bit division insns for sparcv9, with proper sign/zero extensions on the input operands. But that required extra temporaries and quickly got ugly. In the end I thought it was clearer to simply use the 32-bit division insns unconditionally. That excercise, however, made me notice that 32-bit extension was not special-cased, leading to the final patch. r~ Richard Henderson (5): tcg-sparc: Add tcg_out_arithc. tcg-sparc: Implement add2, sub2, mulu2. tcg-sparc: Do not remove %o[012] from 'r' constraint. tcg-sparc: Implement division properly. tcg-sparc: Implement ext32[su]_i64 tcg/sparc/tcg-target.c | 206 ++++++++++++++++++++++++++++++++---------------- tcg/sparc/tcg-target.h | 8 ++ 2 files changed, 145 insertions(+), 69 deletions(-)