From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NhWgk-0000oW-9x for qemu-devel@nongnu.org; Tue, 16 Feb 2010 18:18:42 -0500 Received: from [199.232.76.173] (port=53093 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NhWgj-0000nb-Fi for qemu-devel@nongnu.org; Tue, 16 Feb 2010 18:18:41 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NhWgg-0006oW-An for qemu-devel@nongnu.org; Tue, 16 Feb 2010 18:18:41 -0500 Received: from are.twiddle.net ([75.149.56.221]:37885) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NhWgd-0006nu-Vo for qemu-devel@nongnu.org; Tue, 16 Feb 2010 18:18:36 -0500 Message-Id: From: Richard Henderson Date: Tue, 16 Feb 2010 15:15:40 -0800 Subject: [Qemu-devel] [PATCH 0/6] tcg-sparc improvements List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com All of these patches are toward reducing the number of TCG opcodes generated. Three of the patches reduce the number of real insns generated as well. The ANDC and ORC opcodes are already generated by the ARM, PPC, and Alpha translators. I now have remote access to a real debian sparc64 machine, so this has actually been tested on real hardware for a change. ;-) r~ Richard Henderson (6): tcg-sparc: Implement neg. tcg-sparc: Implement not. tcg: Optional target implementation of ANDC. tcg: Optional target implementation of ORC. tcg-sparc: Implement ANDC. tcg-sparc: Implement ORC. tcg/sparc/tcg-target.c | 30 ++++++++++++++++++++++++++++++ tcg/sparc/tcg-target.h | 11 +++++++++-- tcg/tcg-op.h | 22 ++++++++++++++++++++++ tcg/tcg-opc.h | 12 ++++++++++++ 4 files changed, 73 insertions(+), 2 deletions(-)