* [Qemu-devel] [PATCH v2 1/4] SPI: initial support
2012-04-03 5:50 [Qemu-devel] [PATCH v2 0/4] SPI bus support + Xilinx SPI controller Peter A. G. Crosthwaite
@ 2012-04-03 5:50 ` Peter A. G. Crosthwaite
2012-04-03 5:50 ` [Qemu-devel] [PATCH v2 2/4] m25p80: initial verion Peter A. G. Crosthwaite
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Peter A. G. Crosthwaite @ 2012-04-03 5:50 UTC (permalink / raw)
To: qemu-devel, paul, edgar.iglesias, peter.maydell
Cc: peter.crosthwaite, john.williams
Defined SPI bus and SPI slave QOM interfaces. Inspired by and loosely based on
existing I2C framework.
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
---
changed from v1:
minor sylistic changes
converted spi api to modified txrx style
Makefile.objs | 2 +-
hw/spi.c | 148 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/spi.h | 69 ++++++++++++++++++++++++++
3 files changed, 218 insertions(+), 1 deletions(-)
create mode 100644 hw/spi.c
create mode 100644 hw/spi.h
diff --git a/Makefile.objs b/Makefile.objs
index 226b01d..45eb20f 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -116,7 +116,7 @@ common-obj-$(CONFIG_SSD0323) += ssd0323.o
common-obj-$(CONFIG_ADS7846) += ads7846.o
common-obj-$(CONFIG_MAX111X) += max111x.o
common-obj-$(CONFIG_DS1338) += ds1338.o
-common-obj-y += i2c.o smbus.o smbus_eeprom.o
+common-obj-y += i2c.o smbus.o smbus_eeprom.o spi.o
common-obj-y += eeprom93xx.o
common-obj-y += scsi-disk.o cdrom.o
common-obj-y += scsi-generic.o scsi-bus.o
diff --git a/hw/spi.c b/hw/spi.c
new file mode 100644
index 0000000..8955d3e
--- /dev/null
+++ b/hw/spi.c
@@ -0,0 +1,148 @@
+/*
+ * QEMU SPI bus interface.
+ *
+ * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
+ * Copyright (C) 2012 PetaLogix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "spi.h"
+
+static struct BusInfo SPIBus_info = {
+ .name = "SPI",
+ .size = sizeof(SPIBus)
+};
+
+static const VMStateDescription vmstate_SPIBus = {
+ .name = "SPIBus",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(cur_slave, SPIBus),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+SPIBus *spi_init_bus(DeviceState *parent, int num_slaves, const char *name)
+{
+ SPIBus *bus;
+
+ bus = FROM_QBUS(SPIBus, qbus_create(&SPIBus_info, parent, name));
+ if (num_slaves >= SPIBus_NO_CS) {
+ hw_error("too many slaves on spi bus: %d\n", num_slaves);
+ }
+ bus->num_slaves = num_slaves;
+ bus->slaves = g_malloc0(sizeof(*bus->slaves) * num_slaves);
+ vmstate_register(NULL, -1, &vmstate_SPIBus, bus);
+ return bus;
+}
+
+int spi_attach_slave(SPIBus *bus, SPISlave *slave, int cs)
+{
+ if (bus->slaves[cs]) {
+ return 1;
+ }
+ bus->slaves[cs] = slave;
+ return 0;
+}
+
+int spi_set_cs(SPIBus *bus, int cs)
+{
+ SPISlave *dev;
+ SPISlaveClass *klass;
+
+ if (bus->cur_slave == cs) {
+ return 0;
+ }
+
+ if (bus->cur_slave != SPIBus_NO_CS) {
+ dev = bus->slaves[bus->cur_slave];
+ dev->cs = 0;
+ klass = SPI_SLAVE_GET_CLASS(dev);
+ klass->cs(dev, 0);
+ }
+
+ if (cs >= bus->num_slaves && cs != SPIBus_NO_CS) {
+ hw_error("attempted to assert non existent spi CS line: %d\n", cs);
+ }
+
+ bus->cur_slave = (uint8_t)cs;
+
+ if (cs != SPIBus_NO_CS) {
+ dev = bus->slaves[cs];
+ dev->cs = 1;
+ klass = SPI_SLAVE_GET_CLASS(dev);
+ klass->cs(dev, 1);
+ }
+ return 0;
+};
+
+int spi_get_cs(SPIBus *bus)
+{
+ return bus->cur_slave;
+}
+
+int spi_txrx(SPIBus *bus, uint8_t *tx, uint8_t *txz, uint8_t *rx,
+ uint8_t *rxz, int len)
+{
+ SPISlave *dev;
+ SPISlaveClass *klass;
+
+ if (bus->cur_slave == SPIBus_NO_CS) {
+ return 1;
+ }
+ dev = bus->slaves[bus->cur_slave];
+ klass = SPI_SLAVE_GET_CLASS(dev);
+
+ return klass->txrx(dev, tx, txz, rx, rxz, len);
+}
+
+const VMStateDescription vmstate_spi_slave = {
+ .name = "SPISlave",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(cs, SPISlave),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static int spi_slave_qdev_init(DeviceState *dev)
+{
+ SPISlave *s = SPI_SLAVE_FROM_QDEV(dev);
+ SPISlaveClass *sc = SPI_SLAVE_GET_CLASS(s);
+
+ return sc->init(s);
+}
+
+static void spi_slave_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *k = DEVICE_CLASS(klass);
+ k->init = spi_slave_qdev_init;
+ k->bus_info = &SPIBus_info;
+}
+
+static TypeInfo spi_slave_type_info = {
+ .name = TYPE_SPI_SLAVE,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(SPISlave),
+ .abstract = true,
+ .class_size = sizeof(SPISlaveClass),
+ .class_init = spi_slave_class_init,
+};
+
+static void spi_slave_register_types(void)
+{
+ type_register_static(&spi_slave_type_info);
+}
+
+type_init(spi_slave_register_types)
diff --git a/hw/spi.h b/hw/spi.h
new file mode 100644
index 0000000..f8a6226
--- /dev/null
+++ b/hw/spi.h
@@ -0,0 +1,69 @@
+#ifndef QEMU_SPI_H
+#define QEMU_SPI_H
+
+#include "qdev.h"
+
+/* pass to spi_set_cs to deslect all devices on bus */
+
+#define SPIBus_NO_CS 0xFF
+
+typedef struct SPISlave {
+ DeviceState qdev;
+ uint8_t cs;
+} SPISlave;
+
+#define TYPE_SPI_SLAVE "spi-slave"
+#define SPI_SLAVE(obj) \
+ OBJECT_CHECK(SPISlave, (obj), TYPE_SPI_SLAVE)
+#define SPI_SLAVE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(SPISlaveClass, (klass), TYPE_SPI_SLAVE)
+#define SPI_SLAVE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(SPISlaveClass, (obj), TYPE_SPI_SLAVE)
+
+typedef struct SPISlaveClass {
+ DeviceClass parent_class;
+
+ /* Callbacks provided by the device. */
+ int (*init)(SPISlave *s);
+
+ /* change the cs pin state */
+ void (*cs)(SPISlave *s, uint8_t select);
+
+ /* transaction */
+ int (*txrx)(SPISlave *s, uint8_t *tx, uint8_t *txz, uint8_t *rx,
+ uint8_t *rxz, int len);
+
+} SPISlaveClass;
+
+#define SPI_SLAVE_FROM_QDEV(dev) DO_UPCAST(SPISlave, qdev, dev)
+#define FROM_SPI_SLAVE(type, dev) DO_UPCAST(type, spi, dev)
+
+extern const VMStateDescription vmstate_spi_slave;
+
+#define VMSTATE_SPI_SLAVE(_field, _state) { \
+ .name = (stringify(_field)), \
+ .size = sizeof(SPISlave), \
+ .vmsd = &vmstate_spi_slave, \
+ .flags = VMS_STRUCT, \
+ .offset = vmstate_offset_value(_state, _field, SPISlave), \
+}
+
+typedef struct SPIBus {
+ BusState qbus;
+ SPISlave **slaves;
+ uint8_t num_slaves;
+ uint8_t cur_slave;
+} SPIBus;
+
+/* create a new spi bus */
+SPIBus *spi_init_bus(DeviceState *parent, int num_slaves, const char *name);
+int spi_attach_slave(SPIBus *bus, SPISlave *s, int cs);
+
+/* change the chip select. Return 1 on failure. */
+int spi_set_cs(SPIBus *bus, int cs);
+int spi_get_cs(SPIBus *bus);
+
+int spi_txrx(SPIBus *s, uint8_t *tx, uint8_t *txz, uint8_t *rx,
+ uint8_t *rxz, int len);
+
+#endif
--
1.7.3.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [Qemu-devel] [PATCH v2 2/4] m25p80: initial verion
2012-04-03 5:50 [Qemu-devel] [PATCH v2 0/4] SPI bus support + Xilinx SPI controller Peter A. G. Crosthwaite
2012-04-03 5:50 ` [Qemu-devel] [PATCH v2 1/4] SPI: initial support Peter A. G. Crosthwaite
@ 2012-04-03 5:50 ` Peter A. G. Crosthwaite
2012-04-03 5:50 ` [Qemu-devel] [PATCH v2 3/4] xilinx_spi: initial version Peter A. G. Crosthwaite
2012-04-03 5:50 ` [Qemu-devel] [PATCH v2 4/4] petalogix-ml605: added spi controller with m25p80 Peter A. G. Crosthwaite
3 siblings, 0 replies; 5+ messages in thread
From: Peter A. G. Crosthwaite @ 2012-04-03 5:50 UTC (permalink / raw)
To: qemu-devel, paul, edgar.iglesias, peter.maydell
Cc: peter.crosthwaite, john.williams
Added device model for m25p80 SPI flash
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
---
changed from v1:
converted spi api to modified txrx style
factored out lots of common code and inlined overly short single call functions.
undated for txrx style spi interface
Makefile.target | 1 +
hw/m25p80.c | 397 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 398 insertions(+), 0 deletions(-)
create mode 100644 hw/m25p80.c
diff --git a/Makefile.target b/Makefile.target
index 44b2e83..6c568b4 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -320,6 +320,7 @@ obj-mips-$(CONFIG_FULONG) += bonito.o vt82c686.o mips_fulong2e.o
obj-microblaze-y = petalogix_s3adsp1800_mmu.o
obj-microblaze-y += petalogix_ml605_mmu.o
obj-microblaze-y += microblaze_boot.o
+obj-microblaze-y += m25p80.o
obj-microblaze-y += microblaze_pic_cpu.o
obj-microblaze-y += xilinx_intc.o
diff --git a/hw/m25p80.c b/hw/m25p80.c
new file mode 100644
index 0000000..fb88f6f
--- /dev/null
+++ b/hw/m25p80.c
@@ -0,0 +1,397 @@
+/*
+ * ST M25P80 emulator.
+ *
+ * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
+ * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
+ * Copyright (C) 2012 PetaLogix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw.h"
+#include "blockdev.h"
+#include "spi.h"
+#include "devices.h"
+
+#ifdef M25P80_ERR_DEBUG
+#define DB_PRINT(...) do { \
+ fprintf(stderr, ": %s: ", __func__); \
+ fprintf(stderr, ## __VA_ARGS__); \
+ } while (0);
+#else
+ #define DB_PRINT(...)
+#endif
+
+enum FlashCMD {
+ NOP = 0,
+ PP = 0x2,
+ READ = 0x3,
+ WRDI = 0x4,
+ RDSR = 0x5,
+ WREN = 0x6,
+ FAST_READ = 0xb,
+ SECTOR_ERASE = 0x20,
+ BLOCK_ERASE32 = 0x52,
+ JEDEC_READ = 0x9f,
+ CHIP_ERASE = 0xc7,
+};
+
+enum CMDState {
+ STATE_IDLE,
+ STATE_PAGE_PROGRAM,
+ STATE_READ,
+ STATE_COLLECTING_DATA,
+ STATE_READING_DATA,
+};
+
+struct flash {
+ SPISlave spi;
+ uint32_t r;
+
+ BlockDriverState *bdrv;
+ enum CMDState state;
+
+ uint8_t *storage;
+ uint64_t size;
+ int pagesize;
+ int sectorsize;
+ int blocksize;
+
+ uint8_t data[16];
+ int len;
+ int pos;
+ int wrap_read;
+ int needed_bytes;
+ enum FlashCMD cmd_in_progress;
+
+ int64_t dirty_page;
+
+ uint64_t waddr;
+ int write_enable;
+};
+
+static void flash_sync_page(struct flash *s, int page)
+{
+ if (s->bdrv) {
+ int bdrv_sector;
+ int offset;
+
+ bdrv_sector = (page * s->pagesize) / 512;
+ offset = bdrv_sector * 512;
+ bdrv_write(s->bdrv, bdrv_sector,
+ s->storage + offset, (s->pagesize + 511) / 512);
+ }
+}
+
+static inline void flash_sync_area(struct flash *s, int64_t off, int64_t len)
+{
+ int64_t start, end;
+
+ if (!s->bdrv) {
+ return;
+ }
+
+ start = off / 512;
+ end = (off + len) / 512;
+ bdrv_write(s->bdrv, start, s->storage + (start * 512), end - start);
+}
+
+static void flash_sector_erase(struct flash *s, int sector)
+{
+ if (!s->write_enable) {
+ DB_PRINT("write with write protect!\n");
+ }
+ memset(s->storage + sector, 0xff, s->sectorsize);
+ flash_sync_area(s, sector, s->sectorsize);
+}
+
+static void flash_block_erase32k(struct flash *s, int addr)
+{
+ if (!s->write_enable) {
+ DB_PRINT("write with write protect!\n");
+ }
+ memset(s->storage + addr, 0xff, 32 * 1024);
+ flash_sync_area(s, addr, 32 * 1024);
+}
+
+static void flash_chip_erase(struct flash *s)
+{
+ if (!s->write_enable) {
+ DB_PRINT("write with write protect!\n");
+ }
+ memset(s->storage, 0xff, s->size);
+ flash_sync_area(s, 0, s->size);
+}
+
+static inline void flash_sync_dirty(struct flash *s, int64_t newpage)
+{
+ if (s->dirty_page >= 0 && s->dirty_page != newpage) {
+ flash_sync_page(s, s->dirty_page);
+ s->dirty_page = newpage;
+ }
+}
+
+static inline
+void flash_write8(struct flash *s, uint64_t addr, uint8_t data)
+{
+ int64_t page = addr / s->pagesize;
+ uint8_t prev = s->storage[s->waddr];
+
+ if (!s->write_enable) {
+ DB_PRINT("write with write protect!\n");
+ }
+
+ if ((prev ^ data) & data) {
+ DB_PRINT("programming zero to one! addr=%lx %x -> %x\n",
+ addr, prev, data);
+ }
+ s->storage[s->waddr] ^= ~data & s->storage[s->waddr];
+
+ flash_sync_dirty(s, page);
+ s->dirty_page = page;
+}
+
+static void complete_collecting_data(struct flash *s)
+{
+ s->waddr = s->data[0] << 16;
+ s->waddr |= s->data[1] << 8;
+ s->waddr |= s->data[2];
+
+ switch (s->cmd_in_progress) {
+ case PP:
+ s->state = STATE_PAGE_PROGRAM;
+ break;
+ case READ:
+ case FAST_READ:
+ s->state = STATE_READ;
+ break;
+ case SECTOR_ERASE:
+ DB_PRINT("sector_erase sector=%x\n", (uint32_t)s->waddr);
+ flash_sector_erase(s, s->waddr);
+ break;
+ case BLOCK_ERASE32:
+ DB_PRINT("block_erase addr=%x\n", (uint32_t)s->waddr);
+ flash_block_erase32k(s, s->waddr);
+ break;
+ default:
+ break;
+ }
+}
+
+static void decode_new_cmd(struct flash *s, uint32_t value)
+{
+ s->cmd_in_progress = value;
+ DB_PRINT("decoded new command:%d\n", value);
+
+ switch (value) {
+
+ case SECTOR_ERASE:
+ case BLOCK_ERASE32:
+ case READ:
+ case PP:
+ s->needed_bytes = 3;
+ s->pos = 0; s->len = 0;
+ s->state = STATE_COLLECTING_DATA;
+ break;
+ case FAST_READ:
+ s->needed_bytes = 4;
+ s->pos = 0; s->len = 0;
+ s->state = STATE_COLLECTING_DATA;
+ break;
+
+ case WRDI:
+ s->write_enable = 0;
+ break;
+ case WREN:
+ s->write_enable = 1;
+ break;
+
+ case RDSR:
+ s->data[0] = (!!s->write_enable) << 1;
+ s->pos = 0; s->len = 1; s->wrap_read = 0;
+ s->state = STATE_READING_DATA;
+ break;
+
+ case JEDEC_READ:
+ DB_PRINT("populated jedec code\n");
+ s->data[0] = 0xef;
+ s->data[1] = 0x40;
+ s->data[2] = 0x17;
+ s->pos = 0;
+ s->len = 3;
+ s->wrap_read = 0;
+ s->state = STATE_READING_DATA;
+ break;
+
+ case CHIP_ERASE:
+ if (s->write_enable) {
+ DB_PRINT("chip erase\n");
+ flash_chip_erase(s);
+ } else {
+ DB_PRINT("chip erase with write protect!\n");
+ }
+ break;
+ case NOP:
+ break;
+ default:
+ DB_PRINT("Unknown cmd %x\n", value);
+ break;
+ }
+}
+
+static void m25p80_cs(SPISlave *ss, uint8_t select)
+{
+ struct flash *s = FROM_SPI_SLAVE(struct flash, ss);
+
+ if (!select) {
+ s->len = 0;
+ s->pos = 0;
+ s->state = STATE_IDLE;
+ flash_sync_dirty(s, -1);
+ DB_PRINT("deselect\n");
+ }
+}
+
+static int m25p80_txrx8(SPISlave *ss, uint8_t *tx, uint8_t *txz,
+ uint8_t *rx, uint8_t *rxz)
+{
+ struct flash *s = FROM_SPI_SLAVE(struct flash, ss);
+
+ *rxz = 0xFF;
+
+ switch (s->state) {
+
+ case STATE_PAGE_PROGRAM:
+ if (!*txz) {
+ DB_PRINT("page program waddr=%lx data=%x\n", s->waddr, *tx);
+ flash_write8(s, s->waddr, *tx);
+ s->waddr++;
+ }
+ break;
+
+ case STATE_READ:
+ *rx = s->storage[s->waddr];
+ *rxz = 0x00;
+ DB_PRINT("READ 0x%lx=%x\n", s->waddr, *rx);
+ s->waddr = (s->waddr + 1) % s->size;
+ break;
+
+ case STATE_COLLECTING_DATA:
+ if (!*txz) {
+ s->data[s->len] = *tx;
+ s->len++;
+
+ if (s->len == s->needed_bytes) {
+ complete_collecting_data(s);
+ }
+ }
+ break;
+
+ case STATE_READING_DATA:
+ *rx = s->data[s->pos];
+ *rxz = 0x00;
+ s->pos++;
+ if (s->pos == s->len) {
+ s->pos = 0;
+ if (!s->wrap_read) {
+ s->state = STATE_IDLE;
+ }
+ }
+ break;
+
+ default:
+ case STATE_IDLE:
+ if (!*txz) {
+ decode_new_cmd(s, *tx);
+ }
+ break;
+ }
+
+ return 0;
+}
+
+static int m25p80_txrx(SPISlave *ss, uint8_t *tx, uint8_t *txz,
+ uint8_t *rx, uint8_t *rxz, int len)
+{
+ if (len % 8) {
+ hw_error("m25p80: upsupported spi data transfer with partial byte");
+ }
+
+ for (; len; len -= 8) {
+ if (m25p80_txrx8(ss, tx, txz, rx, rxz)) {
+ return 1;
+ }
+ tx++;
+ rx++;
+ txz++;
+ rxz++;
+ }
+ return 0;
+}
+
+static int m25p80_init(SPISlave *ss)
+{
+ DriveInfo *dinfo;
+ struct flash *s = FROM_SPI_SLAVE(struct flash, ss);
+ static int mtdblock_idx;
+ dinfo = drive_get(IF_MTD, 0, mtdblock_idx++);
+
+ DB_PRINT("inited m25p80 device model - dinfo = %p\n", dinfo);
+ /* TODO: parameterize */
+ s->size = 8 * 1024 * 1024;
+ s->pagesize = 256;
+ s->sectorsize = 4 * 1024;
+ s->dirty_page = -1;
+ s->storage = g_malloc0(s->size);
+
+ if (dinfo && dinfo->bdrv) {
+ int rsize;
+
+ s->bdrv = dinfo->bdrv;
+ rsize = MIN(bdrv_getlength(s->bdrv), s->size);
+ if (bdrv_read(s->bdrv, 0, s->storage, (s->size + 511) / 512)) {
+ fprintf(stderr, "Failed to initialize SPI flash!\n");
+ return 1;
+ }
+ } else {
+ s->write_enable = 1;
+ flash_chip_erase(s);
+ s->write_enable = 0;
+ }
+
+ return 0;
+}
+
+static void m25p80_class_init(ObjectClass *klass, void *data)
+{
+ SPISlaveClass *k = SPI_SLAVE_CLASS(klass);
+
+ k->init = m25p80_init;
+ k->txrx = m25p80_txrx;
+ k->cs = m25p80_cs;
+}
+
+static TypeInfo m25p80_info = {
+ .name = "m25p80",
+ .parent = TYPE_SPI_SLAVE,
+ .instance_size = sizeof(struct flash),
+ .class_init = m25p80_class_init,
+};
+
+static void m25p80_register_types(void)
+{
+ type_register_static(&m25p80_info);
+}
+
+type_init(m25p80_register_types)
--
1.7.3.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [Qemu-devel] [PATCH v2 3/4] xilinx_spi: initial version
2012-04-03 5:50 [Qemu-devel] [PATCH v2 0/4] SPI bus support + Xilinx SPI controller Peter A. G. Crosthwaite
2012-04-03 5:50 ` [Qemu-devel] [PATCH v2 1/4] SPI: initial support Peter A. G. Crosthwaite
2012-04-03 5:50 ` [Qemu-devel] [PATCH v2 2/4] m25p80: initial verion Peter A. G. Crosthwaite
@ 2012-04-03 5:50 ` Peter A. G. Crosthwaite
2012-04-03 5:50 ` [Qemu-devel] [PATCH v2 4/4] petalogix-ml605: added spi controller with m25p80 Peter A. G. Crosthwaite
3 siblings, 0 replies; 5+ messages in thread
From: Peter A. G. Crosthwaite @ 2012-04-03 5:50 UTC (permalink / raw)
To: qemu-devel, paul, edgar.iglesias, peter.maydell
Cc: peter.crosthwaite, john.williams
device model for xilinx XPS SPI controller (v2.0)
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
---
changed from v1:
converted spi api to modified txrx style
Makefile.target | 1 +
hw/xilinx_spi.c | 482 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 483 insertions(+), 0 deletions(-)
create mode 100644 hw/xilinx_spi.c
diff --git a/Makefile.target b/Makefile.target
index 6c568b4..be28bfe 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -321,6 +321,7 @@ obj-microblaze-y = petalogix_s3adsp1800_mmu.o
obj-microblaze-y += petalogix_ml605_mmu.o
obj-microblaze-y += microblaze_boot.o
obj-microblaze-y += m25p80.o
+obj-microblaze-y += xilinx_spi.o
obj-microblaze-y += microblaze_pic_cpu.o
obj-microblaze-y += xilinx_intc.o
diff --git a/hw/xilinx_spi.c b/hw/xilinx_spi.c
new file mode 100644
index 0000000..5e40015
--- /dev/null
+++ b/hw/xilinx_spi.c
@@ -0,0 +1,482 @@
+/*
+ * QEMU model of the Xilinx SPI Controller
+ *
+ * Copyright (C) 2010 Edgar E. Iglesias.
+ * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
+ * Copyright (C) 2012 PetaLogix
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "sysbus.h"
+#include "sysemu.h"
+#include "ptimer.h"
+#include "qemu-log.h"
+
+#include "spi.h"
+
+#ifdef XILINX_SPI_ERR_DEBUG
+#define DB_PRINT(...) do { \
+ fprintf(stderr, ": %s: ", __func__); \
+ fprintf(stderr, ## __VA_ARGS__); \
+ } while (0);
+#else
+ #define DB_PRINT(...)
+#endif
+
+#define R_DGIER (0x1c / 4)
+#define R_DGIER_IE (1 << 31)
+
+#define R_IPISR (0x20 / 4)
+#define IRQ_DRR_NOT_EMPTY (1 << (31 - 23))
+#define IRQ_DRR_OVERRUN (1 << (31 - 26))
+#define IRQ_DRR_FULL (1 << (31 - 27))
+#define IRQ_TX_FF_HALF_EMPTY (1 << 6)
+#define IRQ_DTR_UNDERRUN (1 << 3)
+#define IRQ_DTR_EMPTY (1 << (31 - 29))
+
+#define R_IPIER (0x28 / 4)
+#define R_SRR (0x40 / 4)
+#define R_SPICR (0x60 / 4)
+#define R_SPICR_TXFF_RST (1 << 5)
+#define R_SPICR_RXFF_RST (1 << 6)
+#define R_SPICR_MTI (1 << 8)
+
+#define R_SPISR (0x64 / 4)
+#define SR_TX_FULL (1 << 3)
+#define SR_TX_EMPTY (1 << 2)
+#define SR_RX_FULL (1 << 1)
+#define SR_RX_EMPTY (1 << 0)
+
+
+#define R_SPIDTR (0x68 / 4)
+#define R_SPIDRR (0x6C / 4)
+#define R_SPISSR (0x70 / 4)
+#define R_TX_FF_OCY (0x74 / 4)
+#define R_RX_FF_OCY (0x78 / 4)
+#define R_MAX (0x7C / 4)
+
+struct XilinxSPI {
+ SysBusDevice busdev;
+ MemoryRegion mmio;
+ qemu_irq irq;
+ int irqline;
+
+ QEMUBH *bh;
+ ptimer_state *ptimer;
+
+ SPIBus *spi;
+
+ uint32_t c_fifo_exist;
+
+ uint8_t rx_fifo[256];
+ unsigned int rx_fifo_pos;
+ unsigned int rx_fifo_len;
+
+ uint8_t tx_fifo[256];
+ unsigned int tx_fifo_pos;
+ unsigned int tx_fifo_len;
+
+ /* Slave select. */
+ uint8_t num_cs;
+ int cmd_ongoing;
+
+ uint32_t regs[R_MAX];
+};
+
+static void txfifo_reset(struct XilinxSPI *s)
+{
+ s->tx_fifo_pos = 0;
+ s->tx_fifo_len = 0;
+
+ s->regs[R_SPISR] &= ~SR_TX_FULL;
+ s->regs[R_SPISR] |= SR_TX_EMPTY;
+ s->regs[R_SPISR] &= ~SR_TX_FULL;
+ s->regs[R_IPISR] |= IRQ_DTR_EMPTY;
+}
+
+static void rxfifo_reset(struct XilinxSPI *s)
+{
+ s->rx_fifo_pos = 0;
+ s->rx_fifo_len = 0;
+
+ s->regs[R_SPISR] |= SR_RX_EMPTY;
+ s->regs[R_SPISR] &= ~SR_RX_FULL;
+ s->regs[R_IPISR] &= ~IRQ_DRR_NOT_EMPTY;
+ s->regs[R_IPISR] &= ~IRQ_DRR_OVERRUN;
+}
+
+static void xlx_spi_reset(struct XilinxSPI *s)
+{
+ memset(s->regs, 0, sizeof s->regs);
+
+ rxfifo_reset(s);
+ txfifo_reset(s);
+
+ s->regs[R_SPISSR] = 1;
+ spi_set_cs(s->spi, 0);
+}
+
+static void xlx_spi_update_irq(struct XilinxSPI *s)
+{
+ uint32_t pending;
+ pending = s->regs[R_IPISR] & s->regs[R_IPIER];
+
+ pending = pending && (s->regs[R_DGIER] & R_DGIER_IE);
+ pending = !!pending;
+
+ /* This call lies right in the data paths so dont call the
+ irq chain unless things really changed. */
+ if (pending != s->irqline) {
+ s->irqline = pending;
+ DB_PRINT("irq_change_of of state %d\n", pending);
+ qemu_set_irq(s->irq, pending);
+ }
+}
+
+static inline int spi_master_enabled(struct XilinxSPI *s)
+{
+ return !(s->regs[R_SPICR] & R_SPICR_MTI);
+}
+
+static int spi_slave_select(struct XilinxSPI *s, uint32_t v)
+{
+ unsigned int ss;
+
+ ss = ffs(v) - 1;
+ return ss < s->num_cs ? ss : SPIBus_NO_CS;
+}
+
+static inline int txfifo_empty(struct XilinxSPI *s)
+{
+ return s->tx_fifo_len == 0;
+}
+
+static inline int txfifo_full(struct XilinxSPI *s)
+{
+ return s->tx_fifo_len >= ARRAY_SIZE(s->tx_fifo);
+}
+
+static inline int rxfifo_empty(struct XilinxSPI *s)
+{
+ return s->rx_fifo_len == 0;
+}
+
+static inline int rxfifo_full(struct XilinxSPI *s)
+{
+ return s->rx_fifo_len >= ARRAY_SIZE(s->rx_fifo);
+}
+
+static inline void txfifo_put(struct XilinxSPI *s, uint8_t v)
+{
+ s->regs[R_SPISR] &= ~SR_TX_EMPTY;
+ s->regs[R_IPISR] &= ~IRQ_DTR_EMPTY;
+
+ s->tx_fifo[s->tx_fifo_pos] = v;
+ s->tx_fifo_pos++;
+ s->tx_fifo_pos &= ARRAY_SIZE(s->tx_fifo) - 1;
+ s->tx_fifo_len++;
+
+ s->regs[R_SPISR] &= ~SR_TX_FULL;
+ if (txfifo_full(s)) {
+ s->regs[R_SPISR] |= SR_TX_FULL;
+ }
+}
+
+static inline uint8_t txfifo_get(struct XilinxSPI *s)
+{
+ uint8_t r = 0;
+ assert(s->tx_fifo_len);
+
+ r = s->tx_fifo[(s->tx_fifo_pos - s->tx_fifo_len) &
+ (ARRAY_SIZE(s->tx_fifo) - 1)];
+ s->tx_fifo_len--;
+
+ s->regs[R_SPISR] &= ~SR_TX_FULL;
+ if (txfifo_empty(s)) {
+ s->regs[R_SPISR] |= SR_TX_EMPTY;
+ s->regs[R_IPISR] |= IRQ_DTR_EMPTY;
+ }
+
+ return r;
+}
+
+static inline void rxfifo_put(struct XilinxSPI *s, uint8_t v)
+{
+ DB_PRINT("%x\n", v);
+ s->regs[R_SPISR] &= ~SR_RX_EMPTY;
+ s->regs[R_IPISR] |= IRQ_DRR_NOT_EMPTY;
+
+ s->rx_fifo[s->rx_fifo_pos] = v;
+ s->rx_fifo_pos++;
+ s->rx_fifo_pos &= ARRAY_SIZE(s->rx_fifo) - 1;
+ s->rx_fifo_len++;
+
+ s->regs[R_SPISR] &= ~SR_RX_FULL;
+ if (s->rx_fifo_len >= ARRAY_SIZE(s->rx_fifo)) {
+ s->regs[R_SPISR] |= SR_RX_FULL;
+ s->regs[R_IPISR] |= IRQ_DRR_OVERRUN;
+ }
+}
+
+static inline uint32_t rxfifo_get(struct XilinxSPI *s)
+{
+ uint32_t r = 0;
+ assert(s->rx_fifo_len);
+
+ r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) &
+ (ARRAY_SIZE(s->rx_fifo) - 1)];
+ s->rx_fifo_len--;
+
+ s->regs[R_SPISR] &= ~SR_RX_FULL;
+ if (rxfifo_empty(s)) {
+ s->regs[R_SPISR] |= SR_RX_EMPTY;
+ s->regs[R_IPISR] &= ~IRQ_DRR_NOT_EMPTY;
+ }
+
+ return r;
+}
+
+static void spi_timer_run(struct XilinxSPI *s, int delay)
+{
+ ptimer_set_count(s->ptimer, delay);
+ ptimer_run(s->ptimer, 1);
+}
+
+static void
+spi_flush_txfifo(struct XilinxSPI *s)
+{
+ uint8_t tx;
+ uint8_t txz = 0x00;
+ uint8_t rx;
+ uint8_t rxz = 00;
+
+ while (!txfifo_empty(s)) {
+ tx = txfifo_get(s);
+ DB_PRINT("data transfer:%x\n", tx);
+ if (spi_txrx(s->spi, &tx, &txz, &rx, &rxz, 8)) {
+ hw_error("xilinx spi txrx with no device selected");
+ }
+ if (!rxz) {
+ rxfifo_put(s, rx);
+ } else if (!~rxz) {
+ hw_error("xilinx spi does not support partially tristated bytes\n");
+ }
+ }
+}
+
+static uint64_t
+spi_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+{
+ struct XilinxSPI *s = opaque;
+ uint32_t r = 0;
+
+ addr >>= 2;
+ switch (addr) {
+ case R_SPIDRR:
+ if (rxfifo_empty(s)) {
+ DB_PRINT("Read from empty FIFO!\n");
+ return 0xdeadbeef;
+ }
+
+ r = rxfifo_get(s);
+ break;
+
+ case R_SPISR:
+ r = s->regs[addr];
+ if (rxfifo_empty(s)) {
+ spi_timer_run(s, 1);
+ }
+ break;
+
+ default:
+ if (addr < ARRAY_SIZE(s->regs)) {
+ r = s->regs[addr];
+ }
+ break;
+
+ }
+ DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r);
+ xlx_spi_update_irq(s);
+ return r;
+}
+
+static void
+spi_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val64, unsigned int size)
+{
+ struct XilinxSPI *s = opaque;
+ uint32_t value = val64;
+
+ DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
+ addr >>= 2;
+ switch (addr) {
+ case R_SRR:
+ if (value != 0xa) {
+ DB_PRINT("Invalid write to SRR %x\n", value);
+ } else {
+ xlx_spi_reset(s);
+ }
+ break;
+
+ case R_SPIDTR:
+ txfifo_put(s, value);
+
+ if (!spi_master_enabled(s)) {
+ goto done;
+ } else {
+ DB_PRINT("DTR and master enabled?\n");
+ }
+ spi_flush_txfifo(s);
+ break;
+
+ case R_SPISR:
+ DB_PRINT("Invalid write to SPISR %x\n", value);
+ break;
+
+ case R_IPISR:
+ /* Toggle the bits. */
+ s->regs[addr] ^= value;
+ break;
+
+ /* Slave Select Register. */
+ case R_SPISSR:
+ spi_set_cs(s->spi, spi_slave_select(s, ~value));
+ s->regs[addr] = value;
+ break;
+
+ case R_SPICR:
+ /* FIXME: reset irq and sr state to empty queues. */
+ if (value & R_SPICR_RXFF_RST) {
+ rxfifo_reset(s);
+ }
+
+ if (value & R_SPICR_TXFF_RST) {
+ txfifo_reset(s);
+ }
+ value &= ~(R_SPICR_RXFF_RST | R_SPICR_TXFF_RST);
+ s->regs[addr] = value;
+
+ if (!(value & R_SPICR_MTI)) {
+ /*
+ * The linux driver, when issuing READS to a flash memory,
+ * first sets up the tx part, starts the transmition and
+ * waits for the tx part to end. After that it sets up
+ * the rx part, assumeing the CPU is faster than the flash.
+ *
+ * If we simply flush the txfifo and consume all rx data
+ * from the flash, we'll hit a race in the linux driver and
+ * some rx data will be arrive to the linux driver too early.
+ *
+ * That's why we implement this hack. If we are at the start
+ * of a new cmd (i.e s->cmd_ongoing == 0), then we delay
+ * the processing a bit, to give linux time to set things
+ * up.
+ *
+ * FIXME: The mentione hack doesn't work. Investigate why.
+ */
+ if (0 && s->cmd_ongoing) {
+ spi_flush_txfifo(s);
+ } else {
+ /* When releasing the master disable, initiate a timer
+ that eventually will flush the txfifo. */
+ spi_timer_run(s, 1);
+ }
+ }
+ break;
+
+ default:
+ if (addr < ARRAY_SIZE(s->regs)) {
+ s->regs[addr] = value;
+ }
+ break;
+ }
+
+done:
+ xlx_spi_update_irq(s);
+}
+
+static const MemoryRegionOps spi_ops = {
+ .read = spi_read,
+ .write = spi_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+};
+
+static void timer_hit(void *opaque)
+{
+ struct XilinxSPI *s = opaque;
+
+ if (!txfifo_empty(s)) {
+ spi_flush_txfifo(s);
+ s->cmd_ongoing = 1;
+ }
+ xlx_spi_update_irq(s);
+}
+
+static int xilinx_spi_init(SysBusDevice *dev)
+{
+ struct XilinxSPI *s = FROM_SYSBUS(typeof(*s), dev);
+
+ DB_PRINT("\n");
+ sysbus_init_irq(dev, &s->irq);
+
+ memory_region_init_io(&s->mmio, &spi_ops, s, "xilinx-spi", R_MAX * 4);
+ sysbus_init_mmio(dev, &s->mmio);
+
+ s->bh = qemu_bh_new(timer_hit, s);
+ s->ptimer = ptimer_init(s->bh);
+ ptimer_set_freq(s->ptimer, 10 * 1000 * 1000);
+
+ s->spi = spi_init_bus(&dev->qdev, s->num_cs, "spi");
+
+ xlx_spi_reset(s);
+ return 0;
+}
+
+static Property xilinx_spi_properties[] = {
+ DEFINE_PROP_UINT8("num-cs", struct XilinxSPI, num_cs, 1),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void xilinx_spi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = xilinx_spi_init;
+ dc->props = xilinx_spi_properties;
+}
+
+static TypeInfo xilinx_spi_info = {
+ .name = "xilinx,spi",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(struct XilinxSPI),
+ .class_init = xilinx_spi_class_init,
+};
+
+static void xilinx_spi_register_types(void)
+{
+ type_register_static(&xilinx_spi_info);
+}
+
+type_init(xilinx_spi_register_types)
--
1.7.3.2
^ permalink raw reply related [flat|nested] 5+ messages in thread* [Qemu-devel] [PATCH v2 4/4] petalogix-ml605: added spi controller with m25p80
2012-04-03 5:50 [Qemu-devel] [PATCH v2 0/4] SPI bus support + Xilinx SPI controller Peter A. G. Crosthwaite
` (2 preceding siblings ...)
2012-04-03 5:50 ` [Qemu-devel] [PATCH v2 3/4] xilinx_spi: initial version Peter A. G. Crosthwaite
@ 2012-04-03 5:50 ` Peter A. G. Crosthwaite
3 siblings, 0 replies; 5+ messages in thread
From: Peter A. G. Crosthwaite @ 2012-04-03 5:50 UTC (permalink / raw)
To: qemu-devel, paul, edgar.iglesias, peter.maydell
Cc: peter.crosthwaite, john.williams
Added spi controller to the reference design, with a single cs line and a
m25p80 style spi-flash connected
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
---
hw/petalogix_ml605_mmu.c | 19 +++++++++++++++++++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
index 31a4348..58b90cc 100644
--- a/hw/petalogix_ml605_mmu.c
+++ b/hw/petalogix_ml605_mmu.c
@@ -36,6 +36,7 @@
#include "blockdev.h"
#include "pc.h"
#include "exec-memory.h"
+#include "spi.h"
#include "microblaze_boot.h"
#include "microblaze_pic_cpu.h"
@@ -75,6 +76,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
{
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev;
+ SysBusDevice *busdev;
CPUMBState *env;
DriveInfo *dinfo;
int i;
@@ -131,6 +133,23 @@ petalogix_ml605_init(ram_addr_t ram_size,
irq[1], irq[0], 100 * 1000000);
}
+ {
+ SPIBus *spi;
+
+ dev = qdev_create(NULL, "xilinx,spi");
+ qdev_prop_set_uint8(dev, "num-cs", 1);
+ qdev_init_nofail(dev);
+ busdev = sysbus_from_qdev(dev);
+ sysbus_mmio_map(busdev, 0, 0x40a00000);
+ sysbus_connect_irq(busdev, 0, irq[6]);
+
+ spi = FROM_QBUS(SPIBus, qdev_get_child_bus(dev, "spi"));
+
+ dev = qdev_create(NULL, "m25p80");
+ qdev_init_nofail(dev);
+ spi_attach_slave(spi, SPI_SLAVE(dev), 0);
+ }
+
microblaze_load_kernel(env, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE,
machine_cpu_reset);
--
1.7.3.2
^ permalink raw reply related [flat|nested] 5+ messages in thread