From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:48989) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJZ6v-0006Ns-8l for qemu-devel@nongnu.org; Wed, 03 Oct 2012 20:16:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TJZ6u-0004ys-Dk for qemu-devel@nongnu.org; Wed, 03 Oct 2012 20:16:17 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:60832) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJZ6u-0004yD-7P for qemu-devel@nongnu.org; Wed, 03 Oct 2012 20:16:16 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp2so6927pbb.4 for ; Wed, 03 Oct 2012 17:16:14 -0700 (PDT) From: Peter Crosthwaite Date: Thu, 4 Oct 2012 10:16:10 +1000 Message-Id: Subject: [Qemu-devel] [PATCH v2 0/4] Xilinx-Zynq boot process patches List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, edgar.iglesias@gmail.com Cc: linnj@xilinx.com, Peter Crosthwaite , john.williams@petalogix.com Patch 1 is dual core smp support. Patches 2-4 Implement the SLCR reset functionality. changed from v1: Addressed PMM review (P1) Patches 2-4 are completely new. Removed previous patches 2-3 (no bootloader changes anymore) Peter A. G. Crosthwaite (4): xilinx_zynq: added smp support zynq_slcr: Add links to the CPUs zynq_slcr: Fixed ResetValues enum zynq_slcr: Implement CPU reset and halting hw/xilinx_zynq.c | 68 ++++++++++++++++++++++++++++++++++++++++++++--------- hw/zynq_slcr.c | 29 ++++++++++++++++++++++- 2 files changed, 84 insertions(+), 13 deletions(-)