From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:58551) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNFJ5-0002cQ-H6 for qemu-devel@nongnu.org; Wed, 03 Apr 2013 00:28:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UNFJ2-0004Ck-W6 for qemu-devel@nongnu.org; Wed, 03 Apr 2013 00:28:19 -0400 Received: from mail-pd0-f176.google.com ([209.85.192.176]:63308) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNFJ2-0004Cg-QK for qemu-devel@nongnu.org; Wed, 03 Apr 2013 00:28:16 -0400 Received: by mail-pd0-f176.google.com with SMTP id r11so617692pdi.7 for ; Tue, 02 Apr 2013 21:28:16 -0700 (PDT) Sender: Peter Crosthwaite From: Peter Crosthwaite Date: Wed, 3 Apr 2013 14:27:33 +1000 Message-Id: Subject: [Qemu-devel] [PATCH arm-devs v1 00/15] Xilinx SPIPS fixes round 2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: Peter Crosthwaite Updates to the Zynq SPI controller. Some QOMifying cleanup, followed by a number of bugs/incompletnesses found by some (very) rigourous test vectors. Peter Crosthwaite (15): xilinx_spips: seperate SPI and QSPI as two classes xilinx_spips: Make interrupts clear on read xilinx_spips: Inhibit interrupts in LQSPI mode xilinx_spips: Add verbose LQSPI debug output xilinx_spips: lqspi: Dont trash config register xilinx_spips: Fix QSPI FIFO size xilinx_spips: Trash LQ page cache on mode change xilinx_spips: Add automatic start support xilinx_spips: Implement automatic CS xilinx_spips: Fix CTRL register RW bits xilinx_spips: Fix striping behaviour xilinx_spips: Debug msgs for Snoop state xilinx_spips: Multiple debug verbosity levels xilinx_spips: lqspi: Push more data to tx-fifo xilinx_spips: lqspi: Fix byte/misaligned access hw/arm/xilinx_zynq.c | 2 +- hw/xilinx_spips.c | 265 +++++++++++++++++++++++++++++++++++++------------- 2 files changed, 200 insertions(+), 67 deletions(-)