From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:56885) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0h5-0005wB-OA for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UT0h4-0002K2-S7 for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:04:55 -0400 Received: from mail-da0-x230.google.com ([2607:f8b0:400e:c00::230]:41945) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UT0h4-0002Jv-M4 for qemu-devel@nongnu.org; Thu, 18 Apr 2013 22:04:54 -0400 Received: by mail-da0-f48.google.com with SMTP id f10so61034dak.7 for ; Thu, 18 Apr 2013 19:04:53 -0700 (PDT) Sender: Peter Crosthwaite From: peter.crosthwaite@xilinx.com Date: Fri, 19 Apr 2013 12:02:49 +1000 Message-Id: Subject: [Qemu-devel] [PATCH for-1.5 v2 00/15] Xilinx SPIPS fixes round 2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org From: Peter Crosthwaite Updates to the Zynq SPI controller. Some QOMifying cleanup, followed by a number of bugs/incompletnesses found by some (very) rigourous test vectors. Peter Crosthwaite (15): xilinx_spips: seperate SPI and QSPI as two classes xilinx_spips: Make interrupts clear on read xilinx_spips: Inhibit interrupts in LQSPI mode xilinx_spips: Add verbose LQSPI debug output xilinx_spips: Fix QSPI FIFO size xilinx_spips: Trash LQ page cache on mode change xilinx_spips: Add automatic start support xilinx_spips: Implement automatic CS xilinx_spips: lqspi: Dont touch config register xilinx_spips: Fix CTRL register RW bits xilinx_spips: Fix striping behaviour xilinx_spips: Debug msgs for Snoop state xilinx_spips: Multiple debug verbosity levels xilinx_spips: lqspi: Push more data to tx-fifo xilinx_spips: lqspi: Fix byte/misaligned access hw/arm/xilinx_zynq.c | 2 +- hw/ssi/xilinx_spips.c | 321 ++++++++++++++++++++++++++++++++++++++----------- 2 files changed, 250 insertions(+), 73 deletions(-)