* [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller
@ 2013-06-20 10:14 Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 01/15] i440fx: remove unused parameter i440fx_state of i440fx_init Hu Tao
` (14 more replies)
0 siblings, 15 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:14 UTC (permalink / raw)
To: qemu-devel
This series introduces MemoryController, and refactor pc code
about i440fx pmc and q35 mch, and introduces ISAPc to resolve
breakage of isapc.
The memory hotplug patchset will base on this series. Comments
are welcome!
Hu Tao (15):
i440fx: remove unused parameter i440fx_state of i440fx_init.
i440fx: rename i440FX to i440FX-PMC
i440fx: rename i440FX-pcihost to i440FX
i440fx: prepare for composition
i440fx pmc: create pmc through comosition
i440fx-pmc: calculate PCI memory hole directly
i440fx-pmc: create pci address space
q35-mch: create pci address space
i440fx-pmc: move ram initialization into i440fx-pmc
q35-mch: move ram initialization into q35-mch
introduce ISAPc
i440fx pmc: inherit from MemoryController
q35 mch: inherit from MemoryController
move bios loading to MemoryController and ISAPc
hw/i386/pc.c | 214 +++++++++++++++++++++++++++++++---------
hw/i386/pc_piix.c | 52 ++++------
hw/i386/pc_q35.c | 31 ++----
hw/isa/Makefile.objs | 2 +-
hw/isa/isa_pc.c | 53 ++++++++++
hw/pci-host/piix.c | 244 +++++++++++++++++++---------------------------
hw/pci-host/q35.c | 132 +++++++------------------
include/hw/i386/pc.h | 66 ++++++++++---
include/hw/isa/isa_pc.h | 27 +++++
include/hw/pci-host/q35.h | 16 +--
10 files changed, 465 insertions(+), 372 deletions(-)
create mode 100644 hw/isa/isa_pc.c
create mode 100644 include/hw/isa/isa_pc.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 01/15] i440fx: remove unused parameter i440fx_state of i440fx_init.
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 02/15] i440fx: rename i440FX to i440FX-PMC Hu Tao
` (13 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/i386/pc_piix.c | 4 +---
hw/pci-host/piix.c | 10 ++++------
include/hw/i386/pc.h | 2 +-
3 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 97362f2..1e83c1c 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -74,7 +74,6 @@ static void pc_init1(MemoryRegion *system_memory,
ram_addr_t below_4g_mem_size, above_4g_mem_size;
PCIBus *pci_bus;
ISABus *isa_bus;
- PCII440FXState *i440fx_state;
int piix3_devfn = -1;
qemu_irq *cpu_irq;
qemu_irq *gsi;
@@ -137,7 +136,7 @@ static void pc_init1(MemoryRegion *system_memory,
}
if (pci_enabled) {
- pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi,
+ pci_bus = i440fx_init(&piix3_devfn, &isa_bus, gsi,
system_memory, system_io, ram_size,
below_4g_mem_size,
0x100000000ULL - below_4g_mem_size,
@@ -148,7 +147,6 @@ static void pc_init1(MemoryRegion *system_memory,
pci_memory, ram_memory);
} else {
pci_bus = NULL;
- i440fx_state = NULL;
isa_bus = isa_bus_new(NULL, system_io);
no_hpet = 1;
}
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index f9e68c3..0176ae9 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -225,7 +225,6 @@ static int i440fx_initfn(PCIDevice *dev)
}
static PCIBus *i440fx_common_init(const char *device_name,
- PCII440FXState **pi440fx_state,
int *piix3_devfn,
ISABus **isa_bus, qemu_irq *pic,
MemoryRegion *address_space_mem,
@@ -255,8 +254,7 @@ static PCIBus *i440fx_common_init(const char *device_name,
qdev_init_nofail(dev);
d = pci_create_simple(b, 0, device_name);
- *pi440fx_state = I440FX_PCI_DEVICE(d);
- f = *pi440fx_state;
+ f = I440FX_PCI_DEVICE(d);
f->system_memory = address_space_mem;
f->pci_address_space = pci_address_space;
f->ram_memory = ram_memory;
@@ -307,14 +305,14 @@ static PCIBus *i440fx_common_init(const char *device_name,
ram_size = ram_size / 8 / 1024 / 1024;
if (ram_size > 255)
ram_size = 255;
- (*pi440fx_state)->dev.config[0x57]=ram_size;
+ f->dev.config[0x57] = ram_size;
i440fx_update_memory_mappings(f);
return b;
}
-PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
+PCIBus *i440fx_init(int *piix3_devfn,
ISABus **isa_bus, qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
@@ -328,7 +326,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
{
PCIBus *b;
- b = i440fx_common_init(TYPE_I440FX_PCI_DEVICE, pi440fx_state,
+ b = i440fx_common_init(TYPE_I440FX_PCI_DEVICE,
piix3_devfn, isa_bus, pic,
address_space_mem, address_space_io, ram_size,
pci_hole_start, pci_hole_size,
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 7f04967..7c95189 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -126,7 +126,7 @@ extern int no_hpet;
struct PCII440FXState;
typedef struct PCII440FXState PCII440FXState;
-PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
+PCIBus *i440fx_init(int *piix_devfn,
ISABus **isa_bus, qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 02/15] i440fx: rename i440FX to i440FX-PMC
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 01/15] i440fx: remove unused parameter i440fx_state of i440fx_init Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 03/15] i440fx: rename i440FX-pcihost to i440FX Hu Tao
` (12 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/pci-host/piix.c | 60 ++++++++++++++++++++++++++--------------------------
include/hw/i386/pc.h | 6 +++---
2 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 0176ae9..fc955bd 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -82,11 +82,11 @@ typedef struct PIIX3State {
MemoryRegion rcr_mem;
} PIIX3State;
-#define TYPE_I440FX_PCI_DEVICE "i440FX"
-#define I440FX_PCI_DEVICE(obj) \
- OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
+#define TYPE_I440FX_PMC_DEVICE "i440FX-PMC"
+#define I440FX_PMC_DEVICE(obj) \
+ OBJECT_CHECK(I440FXPMCState, (obj), TYPE_I440FX_PMC_DEVICE)
-struct PCII440FXState {
+struct I440FXPMCState {
PCIDevice dev;
MemoryRegion *system_memory;
MemoryRegion *pci_address_space;
@@ -118,7 +118,7 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
return (pci_intx + slot_addend) & 3;
}
-static void i440fx_update_memory_mappings(PCII440FXState *d)
+static void i440fx_pmc_update_memory_mappings(I440FXPMCState *d)
{
int i;
@@ -133,7 +133,7 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
static void i440fx_set_smm(int val, void *arg)
{
- PCII440FXState *d = arg;
+ I440FXPMCState *d = arg;
memory_region_transaction_begin();
smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
@@ -145,25 +145,25 @@ static void i440fx_set_smm(int val, void *arg)
static void i440fx_write_config(PCIDevice *dev,
uint32_t address, uint32_t val, int len)
{
- PCII440FXState *d = I440FX_PCI_DEVICE(dev);
+ I440FXPMCState *d = I440FX_PMC_DEVICE(dev);
/* XXX: implement SMRAM.D_LOCK */
pci_default_write_config(dev, address, val, len);
if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
range_covers_byte(address, len, I440FX_SMRAM)) {
- i440fx_update_memory_mappings(d);
+ i440fx_pmc_update_memory_mappings(d);
}
}
static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
{
- PCII440FXState *d = opaque;
+ I440FXPMCState *d = opaque;
int ret, i;
ret = pci_device_load(&d->dev, f);
if (ret < 0)
return ret;
- i440fx_update_memory_mappings(d);
+ i440fx_pmc_update_memory_mappings(d);
qemu_get_8s(f, &d->smm_enabled);
if (version_id == 2) {
@@ -177,22 +177,22 @@ static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
static int i440fx_post_load(void *opaque, int version_id)
{
- PCII440FXState *d = opaque;
+ I440FXPMCState *d = opaque;
- i440fx_update_memory_mappings(d);
+ i440fx_pmc_update_memory_mappings(d);
return 0;
}
-static const VMStateDescription vmstate_i440fx = {
- .name = "I440FX",
+static const VMStateDescription vmstate_i440fx_pmc = {
+ .name = TYPE_I440FX_PMC_DEVICE,
.version_id = 3,
.minimum_version_id = 3,
.minimum_version_id_old = 1,
.load_state_old = i440fx_load_old,
.post_load = i440fx_post_load,
.fields = (VMStateField []) {
- VMSTATE_PCI_DEVICE(dev, PCII440FXState),
- VMSTATE_UINT8(smm_enabled, PCII440FXState),
+ VMSTATE_PCI_DEVICE(dev, I440FXPMCState),
+ VMSTATE_UINT8(smm_enabled, I440FXPMCState),
VMSTATE_END_OF_LIST()
}
};
@@ -214,9 +214,9 @@ static int i440fx_pcihost_initfn(SysBusDevice *dev)
return 0;
}
-static int i440fx_initfn(PCIDevice *dev)
+static int i440fx_pmc_initfn(PCIDevice *dev)
{
- PCII440FXState *d = I440FX_PCI_DEVICE(dev);
+ I440FXPMCState *d = I440FX_PMC_DEVICE(dev);
d->dev.config[I440FX_SMRAM] = 0x02;
@@ -242,7 +242,7 @@ static PCIBus *i440fx_common_init(const char *device_name,
PCIDevice *d;
PCIHostState *s;
PIIX3State *piix3;
- PCII440FXState *f;
+ I440FXPMCState *f;
unsigned i;
dev = qdev_create(NULL, "i440FX-pcihost");
@@ -254,7 +254,7 @@ static PCIBus *i440fx_common_init(const char *device_name,
qdev_init_nofail(dev);
d = pci_create_simple(b, 0, device_name);
- f = I440FX_PCI_DEVICE(d);
+ f = I440FX_PMC_DEVICE(d);
f->system_memory = address_space_mem;
f->pci_address_space = pci_address_space;
f->ram_memory = ram_memory;
@@ -307,7 +307,7 @@ static PCIBus *i440fx_common_init(const char *device_name,
ram_size = 255;
f->dev.config[0x57] = ram_size;
- i440fx_update_memory_mappings(f);
+ i440fx_pmc_update_memory_mappings(f);
return b;
}
@@ -326,7 +326,7 @@ PCIBus *i440fx_init(int *piix3_devfn,
{
PCIBus *b;
- b = i440fx_common_init(TYPE_I440FX_PCI_DEVICE,
+ b = i440fx_common_init(TYPE_I440FX_PMC_DEVICE,
piix3_devfn, isa_bus, pic,
address_space_mem, address_space_io, ram_size,
pci_hole_start, pci_hole_size,
@@ -603,13 +603,13 @@ static const TypeInfo piix3_xen_info = {
.class_init = piix3_xen_class_init,
};
-static void i440fx_class_init(ObjectClass *klass, void *data)
+static void i440fx_pmc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->no_hotplug = 1;
- k->init = i440fx_initfn;
+ k->init = i440fx_pmc_initfn;
k->config_write = i440fx_write_config;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82441;
@@ -617,14 +617,14 @@ static void i440fx_class_init(ObjectClass *klass, void *data)
k->class_id = PCI_CLASS_BRIDGE_HOST;
dc->desc = "Host bridge";
dc->no_user = 1;
- dc->vmsd = &vmstate_i440fx;
+ dc->vmsd = &vmstate_i440fx_pmc;
}
-static const TypeInfo i440fx_info = {
- .name = TYPE_I440FX_PCI_DEVICE,
+static const TypeInfo i440fx_pmc_info = {
+ .name = TYPE_I440FX_PMC_DEVICE,
.parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(PCII440FXState),
- .class_init = i440fx_class_init,
+ .instance_size = sizeof(I440FXPMCState),
+ .class_init = i440fx_pmc_class_init,
};
static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
@@ -646,7 +646,7 @@ static const TypeInfo i440fx_pcihost_info = {
static void i440fx_register_types(void)
{
- type_register_static(&i440fx_info);
+ type_register_static(&i440fx_pmc_info);
type_register_static(&piix3_info);
type_register_static(&piix3_xen_info);
type_register_static(&i440fx_pcihost_info);
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 7c95189..3950405 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -122,9 +122,9 @@ void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
/* hpet.c */
extern int no_hpet;
-/* piix_pci.c */
-struct PCII440FXState;
-typedef struct PCII440FXState PCII440FXState;
+/* piix.c */
+struct I440FXPMCState;
+typedef struct I440FXPMCState I440FXPMCState;
PCIBus *i440fx_init(int *piix_devfn,
ISABus **isa_bus, qemu_irq *pic,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 03/15] i440fx: rename i440FX-pcihost to i440FX
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 01/15] i440fx: remove unused parameter i440fx_state of i440fx_init Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 02/15] i440fx: rename i440FX to i440FX-PMC Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 04/15] i440fx: prepare for composition Hu Tao
` (11 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/pci-host/piix.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index fc955bd..9c482ec 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -38,6 +38,10 @@
* http://download.intel.com/design/chipsets/datashts/29054901.pdf
*/
+#define TYPE_I440FX_DEVICE "i440FX"
+#define I440FX_DEVICE(obj) \
+ OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_DEVICE)
+
typedef struct I440FXState {
PCIHostState parent_obj;
} I440FXState;
@@ -197,7 +201,7 @@ static const VMStateDescription vmstate_i440fx_pmc = {
}
};
-static int i440fx_pcihost_initfn(SysBusDevice *dev)
+static int i440fx_initfn(SysBusDevice *dev)
{
PCIHostState *s = PCI_HOST_BRIDGE(dev);
@@ -245,7 +249,7 @@ static PCIBus *i440fx_common_init(const char *device_name,
I440FXPMCState *f;
unsigned i;
- dev = qdev_create(NULL, "i440FX-pcihost");
+ dev = qdev_create(NULL, TYPE_I440FX_DEVICE);
s = PCI_HOST_BRIDGE(dev);
b = pci_bus_new(dev, NULL, pci_address_space,
address_space_io, 0, TYPE_PCI_BUS);
@@ -627,21 +631,21 @@ static const TypeInfo i440fx_pmc_info = {
.class_init = i440fx_pmc_class_init,
};
-static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
+static void i440fx_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = i440fx_pcihost_initfn;
+ k->init = i440fx_initfn;
dc->fw_name = "pci";
dc->no_user = 1;
}
-static const TypeInfo i440fx_pcihost_info = {
- .name = "i440FX-pcihost",
+static const TypeInfo i440fx_info = {
+ .name = TYPE_I440FX_DEVICE,
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(I440FXState),
- .class_init = i440fx_pcihost_class_init,
+ .class_init = i440fx_class_init,
};
static void i440fx_register_types(void)
@@ -649,7 +653,7 @@ static void i440fx_register_types(void)
type_register_static(&i440fx_pmc_info);
type_register_static(&piix3_info);
type_register_static(&piix3_xen_info);
- type_register_static(&i440fx_pcihost_info);
+ type_register_static(&i440fx_info);
}
type_init(i440fx_register_types)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 04/15] i440fx: prepare for composition
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
` (2 preceding siblings ...)
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 03/15] i440fx: rename i440FX-pcihost to i440FX Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 05/15] i440fx pmc: create pmc through comosition Hu Tao
` (10 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/pci-host/piix.c | 49 +++++++++++++++++++++++++++++++------------------
1 file changed, 31 insertions(+), 18 deletions(-)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 9c482ec..1c5c761 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -44,6 +44,8 @@
typedef struct I440FXState {
PCIHostState parent_obj;
+ MemoryRegion *address_space_io;
+ MemoryRegion *pci_address_space;
} I440FXState;
#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
@@ -201,9 +203,13 @@ static const VMStateDescription vmstate_i440fx_pmc = {
}
};
-static int i440fx_initfn(SysBusDevice *dev)
+static int i440fx_realize(SysBusDevice *dev)
{
PCIHostState *s = PCI_HOST_BRIDGE(dev);
+ I440FXState *f = I440FX_DEVICE(dev);
+
+ s->bus = pci_bus_new(DEVICE(f), NULL, f->pci_address_space,
+ f->address_space_io, 0, TYPE_PCI_BUS);
memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
"pci-conf-idx", 4);
@@ -218,6 +224,10 @@ static int i440fx_initfn(SysBusDevice *dev)
return 0;
}
+static void i440fx_initfn(Object *obj)
+{
+}
+
static int i440fx_pmc_initfn(PCIDevice *dev)
{
I440FXPMCState *d = I440FX_PMC_DEVICE(dev);
@@ -241,23 +251,25 @@ static PCIBus *i440fx_common_init(const char *device_name,
MemoryRegion *pci_address_space,
MemoryRegion *ram_memory)
{
- DeviceState *dev;
- PCIBus *b;
PCIDevice *d;
PCIHostState *s;
PIIX3State *piix3;
I440FXPMCState *f;
+ I440FXState *i440fx;
unsigned i;
- dev = qdev_create(NULL, TYPE_I440FX_DEVICE);
- s = PCI_HOST_BRIDGE(dev);
- b = pci_bus_new(dev, NULL, pci_address_space,
- address_space_io, 0, TYPE_PCI_BUS);
- s->bus = b;
- object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
- qdev_init_nofail(dev);
+ i440fx = I440FX_DEVICE(object_new(TYPE_I440FX_DEVICE));
+ s = PCI_HOST_BRIDGE(i440fx);
+
+ i440fx->address_space_io = address_space_io;
+ i440fx->pci_address_space = pci_address_space;
- d = pci_create_simple(b, 0, device_name);
+ object_property_add_child(qdev_get_machine(), "i440fx",
+ OBJECT(i440fx), NULL);
+ qdev_set_parent_bus(DEVICE(i440fx), sysbus_get_default());
+ qdev_init_nofail(DEVICE(i440fx));
+
+ d = pci_create_simple(s->bus, 0, device_name);
f = I440FX_PMC_DEVICE(d);
f->system_memory = address_space_mem;
f->pci_address_space = pci_address_space;
@@ -291,15 +303,15 @@ static PCIBus *i440fx_common_init(const char *device_name,
* These additional routes can be discovered through ACPI. */
if (xen_enabled()) {
piix3 = DO_UPCAST(PIIX3State, dev,
- pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
- pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
+ pci_create_simple_multifunction(s->bus, -1, true, "PIIX3-xen"));
+ pci_bus_irqs(s->bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
piix3, XEN_PIIX_NUM_PIRQS);
} else {
piix3 = DO_UPCAST(PIIX3State, dev,
- pci_create_simple_multifunction(b, -1, true, "PIIX3"));
- pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
+ pci_create_simple_multifunction(s->bus, -1, true, "PIIX3"));
+ pci_bus_irqs(s->bus, piix3_set_irq, pci_slot_get_pirq, piix3,
PIIX_NUM_PIRQS);
- pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
+ pci_bus_set_route_irq_fn(s->bus, piix3_route_intx_pin_to_irq);
}
piix3->pic = pic;
*isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
@@ -313,7 +325,7 @@ static PCIBus *i440fx_common_init(const char *device_name,
i440fx_pmc_update_memory_mappings(f);
- return b;
+ return s->bus;
}
PCIBus *i440fx_init(int *piix3_devfn,
@@ -636,7 +648,7 @@ static void i440fx_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = i440fx_initfn;
+ k->init = i440fx_realize;
dc->fw_name = "pci";
dc->no_user = 1;
}
@@ -645,6 +657,7 @@ static const TypeInfo i440fx_info = {
.name = TYPE_I440FX_DEVICE,
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(I440FXState),
+ .instance_init = i440fx_initfn,
.class_init = i440fx_class_init,
};
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 05/15] i440fx pmc: create pmc through comosition
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
` (3 preceding siblings ...)
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 04/15] i440fx: prepare for composition Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 06/15] i440fx-pmc: calculate PCI memory hole directly Hu Tao
` (9 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/pci-host/piix.c | 123 +++++++++++++++++++++++++++++++++--------------------
1 file changed, 76 insertions(+), 47 deletions(-)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 1c5c761..218aca2 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -38,16 +38,6 @@
* http://download.intel.com/design/chipsets/datashts/29054901.pdf
*/
-#define TYPE_I440FX_DEVICE "i440FX"
-#define I440FX_DEVICE(obj) \
- OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_DEVICE)
-
-typedef struct I440FXState {
- PCIHostState parent_obj;
- MemoryRegion *address_space_io;
- MemoryRegion *pci_address_space;
-} I440FXState;
-
#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
#define XEN_PIIX_NUM_PIRQS 128ULL
@@ -102,8 +92,25 @@ struct I440FXPMCState {
PAMMemoryRegion pam_regions[13];
MemoryRegion smram_region;
uint8_t smm_enabled;
+ ram_addr_t ram_size;
+ hwaddr pci_hole_start;
+ hwaddr pci_hole_size;
+ hwaddr pci_hole64_start;
+ hwaddr pci_hole64_size;
};
+#define TYPE_I440FX_DEVICE "i440FX"
+#define I440FX_DEVICE(obj) \
+ OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_DEVICE)
+
+typedef struct I440FXState {
+ PCIHostState parent_obj;
+ MemoryRegion *address_space_io;
+ MemoryRegion *pci_address_space;
+
+ PIIX3State piix3;
+ I440FXPMCState pmc;
+} I440FXState;
#define I440FX_PAM 0x59
#define I440FX_PAM_SIZE 7
@@ -221,16 +228,63 @@ static int i440fx_realize(SysBusDevice *dev)
sysbus_add_io(dev, 0xcfc, &s->data_mem);
sysbus_init_ioports(&s->busdev, 0xcfc, 4);
+ qdev_set_parent_bus(DEVICE(&f->pmc), BUS(s->bus));
+ qdev_init_nofail(DEVICE(&f->pmc));
+
return 0;
}
static void i440fx_initfn(Object *obj)
{
+ I440FXState *f = I440FX_DEVICE(obj);
+
+ object_initialize(&f->pmc, TYPE_I440FX_PMC_DEVICE);
+ object_property_add_child(obj, "pmc", OBJECT(&f->pmc), NULL);
+ qdev_prop_set_uint32(DEVICE(&f->pmc), "addr", PCI_DEVFN(0, 0));
}
static int i440fx_pmc_initfn(PCIDevice *dev)
{
I440FXPMCState *d = I440FX_PMC_DEVICE(dev);
+ ram_addr_t ram_size;
+ int i;
+
+ g_assert(d->system_memory != NULL);
+ g_assert(d->pci_address_space != NULL);
+ g_assert(d->ram_memory != NULL);
+
+ memory_region_init_alias(&d->pci_hole, "pci-hole", d->pci_address_space,
+ d->pci_hole_start, d->pci_hole_size);
+ memory_region_add_subregion(d->system_memory, d->pci_hole_start,
+ &d->pci_hole);
+ memory_region_init_alias(&d->pci_hole_64bit, "pci-hole64",
+ d->pci_address_space,
+ d->pci_hole64_start, d->pci_hole64_size);
+ if (d->pci_hole64_size) {
+ memory_region_add_subregion(d->system_memory, d->pci_hole64_start,
+ &d->pci_hole_64bit);
+ }
+ memory_region_init_alias(&d->smram_region, "smram-region",
+ d->pci_address_space, 0xa0000, 0x20000);
+ memory_region_add_subregion_overlap(d->system_memory, 0xa0000,
+ &d->smram_region, 1);
+ memory_region_set_enabled(&d->smram_region, false);
+
+ init_pam(d->ram_memory, d->system_memory, d->pci_address_space,
+ &d->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
+ for (i = 0; i < 12; ++i) {
+ init_pam(d->ram_memory, d->system_memory, d->pci_address_space,
+ &d->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
+ PAM_EXPAN_SIZE);
+ }
+
+ ram_size = d->ram_size / 8 / 1024 / 1024;
+ if (ram_size > 255) {
+ ram_size = 255;
+ }
+ d->dev.config[0x57] = ram_size;
+
+ i440fx_pmc_update_memory_mappings(d);
d->dev.config[I440FX_SMRAM] = 0x02;
@@ -251,12 +305,10 @@ static PCIBus *i440fx_common_init(const char *device_name,
MemoryRegion *pci_address_space,
MemoryRegion *ram_memory)
{
- PCIDevice *d;
PCIHostState *s;
PIIX3State *piix3;
I440FXPMCState *f;
I440FXState *i440fx;
- unsigned i;
i440fx = I440FX_DEVICE(object_new(TYPE_I440FX_DEVICE));
s = PCI_HOST_BRIDGE(i440fx);
@@ -264,38 +316,22 @@ static PCIBus *i440fx_common_init(const char *device_name,
i440fx->address_space_io = address_space_io;
i440fx->pci_address_space = pci_address_space;
- object_property_add_child(qdev_get_machine(), "i440fx",
- OBJECT(i440fx), NULL);
- qdev_set_parent_bus(DEVICE(i440fx), sysbus_get_default());
- qdev_init_nofail(DEVICE(i440fx));
+ /* FIXME these should be derived */
+ i440fx->pmc.pci_hole_start = pci_hole_start;
+ i440fx->pmc.pci_hole_size = pci_hole_size;
+ i440fx->pmc.pci_hole64_start = pci_hole64_start;
+ i440fx->pmc.pci_hole64_size = pci_hole64_size;
- d = pci_create_simple(s->bus, 0, device_name);
- f = I440FX_PMC_DEVICE(d);
+ f = &i440fx->pmc;
+ f->ram_size = ram_size;
f->system_memory = address_space_mem;
f->pci_address_space = pci_address_space;
f->ram_memory = ram_memory;
- memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
- pci_hole_start, pci_hole_size);
- memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
- memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
- f->pci_address_space,
- pci_hole64_start, pci_hole64_size);
- if (pci_hole64_size) {
- memory_region_add_subregion(f->system_memory, pci_hole64_start,
- &f->pci_hole_64bit);
- }
- memory_region_init_alias(&f->smram_region, "smram-region",
- f->pci_address_space, 0xa0000, 0x20000);
- memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
- &f->smram_region, 1);
- memory_region_set_enabled(&f->smram_region, false);
- init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
- &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
- for (i = 0; i < 12; ++i) {
- init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
- &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
- PAM_EXPAN_SIZE);
- }
+
+ object_property_add_child(qdev_get_machine(), "i440fx",
+ OBJECT(i440fx), NULL);
+ qdev_set_parent_bus(DEVICE(i440fx), sysbus_get_default());
+ qdev_init_nofail(DEVICE(i440fx));
/* Xen supports additional interrupt routes from the PCI devices to
* the IOAPIC: the four pins of each PCI device on the bus are also
@@ -318,13 +354,6 @@ static PCIBus *i440fx_common_init(const char *device_name,
*piix3_devfn = piix3->dev.devfn;
- ram_size = ram_size / 8 / 1024 / 1024;
- if (ram_size > 255)
- ram_size = 255;
- f->dev.config[0x57] = ram_size;
-
- i440fx_pmc_update_memory_mappings(f);
-
return s->bus;
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 06/15] i440fx-pmc: calculate PCI memory hole directly
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
` (4 preceding siblings ...)
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 05/15] i440fx pmc: create pmc through comosition Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 07/15] i440fx-pmc: create pci address space Hu Tao
` (8 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/i386/pc_piix.c | 6 ------
hw/pci-host/piix.c | 49 ++++++++++++++++++++++++-------------------------
include/hw/i386/pc.h | 4 ----
3 files changed, 24 insertions(+), 35 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 1e83c1c..3934754 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -138,12 +138,6 @@ static void pc_init1(MemoryRegion *system_memory,
if (pci_enabled) {
pci_bus = i440fx_init(&piix3_devfn, &isa_bus, gsi,
system_memory, system_io, ram_size,
- below_4g_mem_size,
- 0x100000000ULL - below_4g_mem_size,
- 0x100000000ULL + above_4g_mem_size,
- (sizeof(hwaddr) == 4
- ? 0
- : ((uint64_t)1 << 62)),
pci_memory, ram_memory);
} else {
pci_bus = NULL;
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 218aca2..7b58d56 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -43,6 +43,9 @@
#define XEN_PIIX_NUM_PIRQS 128ULL
#define PIIX_PIRQC 0x60
+#define I440FX_PMC_PCI_HOLE 0xE0000000ULL
+#define I440FX_PMC_PCI_HOLE_END 0x100000000ULL
+
/*
* Reset Control Register: PCI-accessible ISA-Compatible Register at address
* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
@@ -93,10 +96,6 @@ struct I440FXPMCState {
MemoryRegion smram_region;
uint8_t smm_enabled;
ram_addr_t ram_size;
- hwaddr pci_hole_start;
- hwaddr pci_hole_size;
- hwaddr pci_hole64_start;
- hwaddr pci_hole64_size;
};
#define TYPE_I440FX_DEVICE "i440FX"
@@ -247,21 +246,37 @@ static int i440fx_pmc_initfn(PCIDevice *dev)
{
I440FXPMCState *d = I440FX_PMC_DEVICE(dev);
ram_addr_t ram_size;
+ hwaddr pci_hole_start, pci_hole_size;
+ hwaddr pci_hole64_start, pci_hole64_size;
int i;
g_assert(d->system_memory != NULL);
g_assert(d->pci_address_space != NULL);
g_assert(d->ram_memory != NULL);
+ if(d->ram_size > I440FX_PMC_PCI_HOLE) {
+ pci_hole_start = I440FX_PMC_PCI_HOLE;
+ } else {
+ pci_hole_start = d->ram_size;
+ }
+ pci_hole_size = I440FX_PMC_PCI_HOLE_END - pci_hole_start;
+
+ pci_hole64_start = I440FX_PMC_PCI_HOLE_END + d->ram_size - pci_hole_start;
+ if (sizeof(hwaddr) == 4) {
+ pci_hole64_size = 0;
+ } else {
+ pci_hole64_size = (1ULL << 62);
+ }
+
memory_region_init_alias(&d->pci_hole, "pci-hole", d->pci_address_space,
- d->pci_hole_start, d->pci_hole_size);
- memory_region_add_subregion(d->system_memory, d->pci_hole_start,
+ pci_hole_start, pci_hole_size);
+ memory_region_add_subregion(d->system_memory, pci_hole_start,
&d->pci_hole);
memory_region_init_alias(&d->pci_hole_64bit, "pci-hole64",
d->pci_address_space,
- d->pci_hole64_start, d->pci_hole64_size);
- if (d->pci_hole64_size) {
- memory_region_add_subregion(d->system_memory, d->pci_hole64_start,
+ pci_hole64_start, pci_hole64_size);
+ if (pci_hole64_size) {
+ memory_region_add_subregion(d->system_memory, pci_hole64_start,
&d->pci_hole_64bit);
}
memory_region_init_alias(&d->smram_region, "smram-region",
@@ -298,10 +313,6 @@ static PCIBus *i440fx_common_init(const char *device_name,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- hwaddr pci_hole_start,
- hwaddr pci_hole_size,
- hwaddr pci_hole64_start,
- hwaddr pci_hole64_size,
MemoryRegion *pci_address_space,
MemoryRegion *ram_memory)
{
@@ -316,12 +327,6 @@ static PCIBus *i440fx_common_init(const char *device_name,
i440fx->address_space_io = address_space_io;
i440fx->pci_address_space = pci_address_space;
- /* FIXME these should be derived */
- i440fx->pmc.pci_hole_start = pci_hole_start;
- i440fx->pmc.pci_hole_size = pci_hole_size;
- i440fx->pmc.pci_hole64_start = pci_hole64_start;
- i440fx->pmc.pci_hole64_size = pci_hole64_size;
-
f = &i440fx->pmc;
f->ram_size = ram_size;
f->system_memory = address_space_mem;
@@ -362,10 +367,6 @@ PCIBus *i440fx_init(int *piix3_devfn,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- hwaddr pci_hole_start,
- hwaddr pci_hole_size,
- hwaddr pci_hole64_start,
- hwaddr pci_hole64_size,
MemoryRegion *pci_memory, MemoryRegion *ram_memory)
{
@@ -374,8 +375,6 @@ PCIBus *i440fx_init(int *piix3_devfn,
b = i440fx_common_init(TYPE_I440FX_PMC_DEVICE,
piix3_devfn, isa_bus, pic,
address_space_mem, address_space_io, ram_size,
- pci_hole_start, pci_hole_size,
- pci_hole64_start, pci_hole64_size,
pci_memory, ram_memory);
return b;
}
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 3950405..4c1027e 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -131,10 +131,6 @@ PCIBus *i440fx_init(int *piix_devfn,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- hwaddr pci_hole_start,
- hwaddr pci_hole_size,
- hwaddr pci_hole64_start,
- hwaddr pci_hole64_size,
MemoryRegion *pci_memory,
MemoryRegion *ram_memory);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 07/15] i440fx-pmc: create pci address space
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
` (5 preceding siblings ...)
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 06/15] i440fx-pmc: calculate PCI memory hole directly Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 08/15] q35-mch: " Hu Tao
` (7 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/i386/pc_piix.c | 33 +++++++++++++++------------------
hw/pci-host/piix.c | 16 +++++++++-------
include/hw/i386/pc.h | 2 +-
3 files changed, 25 insertions(+), 26 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 3934754..1ca705c 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -109,23 +109,6 @@ static void pc_init1(MemoryRegion *system_memory,
below_4g_mem_size = ram_size;
}
- if (pci_enabled) {
- pci_memory = g_new(MemoryRegion, 1);
- memory_region_init(pci_memory, "pci", INT64_MAX);
- rom_memory = pci_memory;
- } else {
- pci_memory = NULL;
- rom_memory = system_memory;
- }
-
- /* allocate ram and load rom/bios */
- if (!xen_enabled()) {
- fw_cfg = pc_memory_init(system_memory,
- kernel_filename, kernel_cmdline, initrd_filename,
- below_4g_mem_size, above_4g_mem_size,
- rom_memory, &ram_memory);
- }
-
gsi_state = g_malloc0(sizeof(*gsi_state));
if (kvm_irqchip_in_kernel()) {
kvm_pc_setup_irq_routing(pci_enabled);
@@ -138,7 +121,7 @@ static void pc_init1(MemoryRegion *system_memory,
if (pci_enabled) {
pci_bus = i440fx_init(&piix3_devfn, &isa_bus, gsi,
system_memory, system_io, ram_size,
- pci_memory, ram_memory);
+ &pci_memory, ram_memory);
} else {
pci_bus = NULL;
isa_bus = isa_bus_new(NULL, system_io);
@@ -146,6 +129,20 @@ static void pc_init1(MemoryRegion *system_memory,
}
isa_bus_irqs(isa_bus, gsi);
+ if (pci_enabled) {
+ rom_memory = pci_memory;
+ } else {
+ rom_memory = system_memory;
+ }
+
+ /* allocate ram and load rom/bios */
+ if (!xen_enabled()) {
+ fw_cfg = pc_memory_init(system_memory,
+ kernel_filename, kernel_cmdline, initrd_filename,
+ below_4g_mem_size, above_4g_mem_size,
+ rom_memory, &ram_memory);
+ }
+
if (kvm_irqchip_in_kernel()) {
i8259 = kvm_i8259_init(isa_bus);
} else if (xen_enabled()) {
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 7b58d56..604a66e 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -105,7 +105,7 @@ struct I440FXPMCState {
typedef struct I440FXState {
PCIHostState parent_obj;
MemoryRegion *address_space_io;
- MemoryRegion *pci_address_space;
+ MemoryRegion pci_address_space;
PIIX3State piix3;
I440FXPMCState pmc;
@@ -214,7 +214,7 @@ static int i440fx_realize(SysBusDevice *dev)
PCIHostState *s = PCI_HOST_BRIDGE(dev);
I440FXState *f = I440FX_DEVICE(dev);
- s->bus = pci_bus_new(DEVICE(f), NULL, f->pci_address_space,
+ s->bus = pci_bus_new(DEVICE(f), NULL, &f->pci_address_space,
f->address_space_io, 0, TYPE_PCI_BUS);
memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
@@ -227,6 +227,8 @@ static int i440fx_realize(SysBusDevice *dev)
sysbus_add_io(dev, 0xcfc, &s->data_mem);
sysbus_init_ioports(&s->busdev, 0xcfc, 4);
+ f->pmc.pci_address_space = &f->pci_address_space;
+
qdev_set_parent_bus(DEVICE(&f->pmc), BUS(s->bus));
qdev_init_nofail(DEVICE(&f->pmc));
@@ -240,6 +242,8 @@ static void i440fx_initfn(Object *obj)
object_initialize(&f->pmc, TYPE_I440FX_PMC_DEVICE);
object_property_add_child(obj, "pmc", OBJECT(&f->pmc), NULL);
qdev_prop_set_uint32(DEVICE(&f->pmc), "addr", PCI_DEVFN(0, 0));
+
+ memory_region_init(&f->pci_address_space, "pci", INT64_MAX);
}
static int i440fx_pmc_initfn(PCIDevice *dev)
@@ -251,7 +255,6 @@ static int i440fx_pmc_initfn(PCIDevice *dev)
int i;
g_assert(d->system_memory != NULL);
- g_assert(d->pci_address_space != NULL);
g_assert(d->ram_memory != NULL);
if(d->ram_size > I440FX_PMC_PCI_HOLE) {
@@ -313,7 +316,7 @@ static PCIBus *i440fx_common_init(const char *device_name,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- MemoryRegion *pci_address_space,
+ MemoryRegion **pci_address_space,
MemoryRegion *ram_memory)
{
PCIHostState *s;
@@ -325,12 +328,10 @@ static PCIBus *i440fx_common_init(const char *device_name,
s = PCI_HOST_BRIDGE(i440fx);
i440fx->address_space_io = address_space_io;
- i440fx->pci_address_space = pci_address_space;
f = &i440fx->pmc;
f->ram_size = ram_size;
f->system_memory = address_space_mem;
- f->pci_address_space = pci_address_space;
f->ram_memory = ram_memory;
object_property_add_child(qdev_get_machine(), "i440fx",
@@ -358,6 +359,7 @@ static PCIBus *i440fx_common_init(const char *device_name,
*isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
*piix3_devfn = piix3->dev.devfn;
+ *pci_address_space = &i440fx->pci_address_space;
return s->bus;
}
@@ -367,7 +369,7 @@ PCIBus *i440fx_init(int *piix3_devfn,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- MemoryRegion *pci_memory, MemoryRegion *ram_memory)
+ MemoryRegion **pci_memory, MemoryRegion *ram_memory)
{
PCIBus *b;
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 4c1027e..fa14c49 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -131,7 +131,7 @@ PCIBus *i440fx_init(int *piix_devfn,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- MemoryRegion *pci_memory,
+ MemoryRegion **pci_memory,
MemoryRegion *ram_memory);
/* piix4.c */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 08/15] q35-mch: create pci address space
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
` (6 preceding siblings ...)
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 07/15] i440fx-pmc: create pci address space Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 09/15] i440fx-pmc: move ram initialization into i440fx-pmc Hu Tao
` (6 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/i386/pc_q35.c | 13 ++++---------
hw/pci-host/q35.c | 12 +++++++-----
include/hw/pci-host/q35.h | 1 +
3 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index bb0ce6a..109bb64 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -64,7 +64,6 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
BusState *idebus[MAX_SATA_PORTS];
ISADevice *rtc_state;
ISADevice *floppy;
- MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
MemoryRegion *ram_memory;
GSIState *gsi_state;
@@ -87,6 +86,9 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
kvmclock_create();
+ /* create pci host bus */
+ q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
+
if (ram_size >= 0xb0000000) {
above_4g_mem_size = ram_size - 0xb0000000;
below_4g_mem_size = 0xb0000000;
@@ -97,11 +99,8 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
/* pci enabled */
if (pci_enabled) {
- pci_memory = g_new(MemoryRegion, 1);
- memory_region_init(pci_memory, "pci", INT64_MAX);
- rom_memory = pci_memory;
+ rom_memory = &q35_host->pci_address_space;
} else {
- pci_memory = NULL;
rom_memory = get_system_memory();
}
@@ -122,11 +121,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
}
- /* create pci host bus */
- q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
-
q35_host->mch.ram_memory = ram_memory;
- q35_host->mch.pci_address_space = pci_memory;
q35_host->mch.system_memory = get_system_memory();
q35_host->mch.address_space_io = get_system_io();
q35_host->mch.below_4g_mem_size = below_4g_mem_size;
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 24df6b5..3ab5ed8 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -36,8 +36,7 @@
static int q35_host_init(SysBusDevice *dev)
{
- PCIBus *b;
- PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev);
+ PCIHostState *pci = PCI_HOST_BRIDGE(dev);
Q35PCIHost *s = Q35_HOST_DEVICE(&dev->qdev);
memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci,
@@ -53,11 +52,12 @@ static int q35_host_init(SysBusDevice *dev)
if (pcie_host_init(&s->host) < 0) {
return -1;
}
- b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0",
+
+ s->mch.pci_address_space = &s->pci_address_space;
+ pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
s->mch.pci_address_space, s->mch.address_space_io,
0, TYPE_PCIE_BUS);
- s->host.pci.bus = b;
- qdev_set_parent_bus(DEVICE(&s->mch), BUS(b));
+ qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
qdev_init_nofail(DEVICE(&s->mch));
return 0;
@@ -87,6 +87,8 @@ static void q35_host_initfn(Object *obj)
object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
+
+ memory_region_init(&s->pci_address_space, "pci", INT64_MAX);
}
static const TypeInfo q35_host_info = {
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index e182c82..1c02420 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -60,6 +60,7 @@ typedef struct MCHPCIState {
typedef struct Q35PCIHost {
PCIExpressHost host;
MCHPCIState mch;
+ MemoryRegion pci_address_space;
} Q35PCIHost;
#define Q35_MASK(bit, ms_bit, ls_bit) \
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 09/15] i440fx-pmc: move ram initialization into i440fx-pmc
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
` (7 preceding siblings ...)
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 08/15] q35-mch: " Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 10/15] q35-mch: move ram initialization into q35-mch Hu Tao
` (5 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/i386/pc.c | 24 +-----------------------
hw/i386/pc_piix.c | 5 ++---
hw/pci-host/piix.c | 39 +++++++++++++++++++++++++++++++--------
include/hw/i386/pc.h | 3 +--
4 files changed, 35 insertions(+), 36 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 5e8f143..909307e 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1033,33 +1033,11 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
MemoryRegion **ram_memory)
{
int linux_boot, i;
- MemoryRegion *ram, *option_rom_mr;
- MemoryRegion *ram_below_4g, *ram_above_4g;
+ MemoryRegion *option_rom_mr;
FWCfgState *fw_cfg;
linux_boot = (kernel_filename != NULL);
- /* Allocate RAM. We allocate it as a single memory region and use
- * aliases to address portions of it, mostly for backwards compatibility
- * with older qemus that used qemu_ram_alloc().
- */
- ram = g_malloc(sizeof(*ram));
- memory_region_init_ram(ram, "pc.ram",
- below_4g_mem_size + above_4g_mem_size);
- vmstate_register_ram_global(ram);
- *ram_memory = ram;
- ram_below_4g = g_malloc(sizeof(*ram_below_4g));
- memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
- 0, below_4g_mem_size);
- memory_region_add_subregion(system_memory, 0, ram_below_4g);
- if (above_4g_mem_size > 0) {
- ram_above_4g = g_malloc(sizeof(*ram_above_4g));
- memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
- below_4g_mem_size, above_4g_mem_size);
- memory_region_add_subregion(system_memory, 0x100000000ULL,
- ram_above_4g);
- }
-
/* Initialize PC system firmware */
pc_system_firmware_init(rom_memory);
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 1ca705c..4614c07 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -84,7 +84,6 @@ static void pc_init1(MemoryRegion *system_memory,
BusState *idebus[MAX_IDE_BUS];
ISADevice *rtc_state;
ISADevice *floppy;
- MemoryRegion *ram_memory;
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
DeviceState *icc_bridge;
@@ -121,7 +120,7 @@ static void pc_init1(MemoryRegion *system_memory,
if (pci_enabled) {
pci_bus = i440fx_init(&piix3_devfn, &isa_bus, gsi,
system_memory, system_io, ram_size,
- &pci_memory, ram_memory);
+ &pci_memory);
} else {
pci_bus = NULL;
isa_bus = isa_bus_new(NULL, system_io);
@@ -140,7 +139,7 @@ static void pc_init1(MemoryRegion *system_memory,
fw_cfg = pc_memory_init(system_memory,
kernel_filename, kernel_cmdline, initrd_filename,
below_4g_mem_size, above_4g_mem_size,
- rom_memory, &ram_memory);
+ rom_memory, NULL);
}
if (kvm_irqchip_in_kernel()) {
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 604a66e..5318ddc 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -96,6 +96,10 @@ struct I440FXPMCState {
MemoryRegion smram_region;
uint8_t smm_enabled;
ram_addr_t ram_size;
+ MemoryRegion ram;
+ MemoryRegion ram_below_4g;
+ MemoryRegion ram_above_4g;
+
};
#define TYPE_I440FX_DEVICE "i440FX"
@@ -250,18 +254,39 @@ static int i440fx_pmc_initfn(PCIDevice *dev)
{
I440FXPMCState *d = I440FX_PMC_DEVICE(dev);
ram_addr_t ram_size;
+ hwaddr below_4g_mem_size, above_4g_mem_size;
hwaddr pci_hole_start, pci_hole_size;
hwaddr pci_hole64_start, pci_hole64_size;
int i;
g_assert(d->system_memory != NULL);
- g_assert(d->ram_memory != NULL);
if(d->ram_size > I440FX_PMC_PCI_HOLE) {
- pci_hole_start = I440FX_PMC_PCI_HOLE;
+ below_4g_mem_size = I440FX_PMC_PCI_HOLE;
+ above_4g_mem_size = d->ram_size - I440FX_PMC_PCI_HOLE;
} else {
- pci_hole_start = d->ram_size;
+ below_4g_mem_size = d->ram_size;
+ above_4g_mem_size = 0;
}
+
+ /* Allocate RAM. We allocate it as a single memory region and use
+ * aliases to address portions of it, mostly for backwards compatibility
+ * with older qemus that used qemu_ram_alloc().
+ */
+ memory_region_init_ram(&d->ram, "pc.ram",
+ below_4g_mem_size + above_4g_mem_size);
+ vmstate_register_ram_global(&d->ram);
+ memory_region_init_alias(&d->ram_below_4g, "ram-below-4g", &d->ram,
+ 0, below_4g_mem_size);
+ memory_region_add_subregion(d->system_memory, 0, &d->ram_below_4g);
+ if (above_4g_mem_size > 0) {
+ memory_region_init_alias(&d->ram_above_4g, "ram-above-4g", &d->ram,
+ below_4g_mem_size, above_4g_mem_size);
+ memory_region_add_subregion(d->system_memory, I440FX_PMC_PCI_HOLE_END,
+ &d->ram_above_4g);
+ }
+
+ pci_hole_start = below_4g_mem_size;
pci_hole_size = I440FX_PMC_PCI_HOLE_END - pci_hole_start;
pci_hole64_start = I440FX_PMC_PCI_HOLE_END + d->ram_size - pci_hole_start;
@@ -316,8 +341,7 @@ static PCIBus *i440fx_common_init(const char *device_name,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- MemoryRegion **pci_address_space,
- MemoryRegion *ram_memory)
+ MemoryRegion **pci_address_space)
{
PCIHostState *s;
PIIX3State *piix3;
@@ -332,7 +356,6 @@ static PCIBus *i440fx_common_init(const char *device_name,
f = &i440fx->pmc;
f->ram_size = ram_size;
f->system_memory = address_space_mem;
- f->ram_memory = ram_memory;
object_property_add_child(qdev_get_machine(), "i440fx",
OBJECT(i440fx), NULL);
@@ -369,7 +392,7 @@ PCIBus *i440fx_init(int *piix3_devfn,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- MemoryRegion **pci_memory, MemoryRegion *ram_memory)
+ MemoryRegion **pci_memory)
{
PCIBus *b;
@@ -377,7 +400,7 @@ PCIBus *i440fx_init(int *piix3_devfn,
b = i440fx_common_init(TYPE_I440FX_PMC_DEVICE,
piix3_devfn, isa_bus, pic,
address_space_mem, address_space_io, ram_size,
- pci_memory, ram_memory);
+ pci_memory);
return b;
}
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index fa14c49..702a63c 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -131,8 +131,7 @@ PCIBus *i440fx_init(int *piix_devfn,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- MemoryRegion **pci_memory,
- MemoryRegion *ram_memory);
+ MemoryRegion **pci_memory);
/* piix4.c */
extern PCIDevice *piix4_dev;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 10/15] q35-mch: move ram initialization into q35-mch
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
` (8 preceding siblings ...)
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 09/15] i440fx-pmc: move ram initialization into i440fx-pmc Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 11/15] introduce ISAPc Hu Tao
` (4 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/i386/pc.c | 3 +--
hw/i386/pc_piix.c | 2 +-
hw/i386/pc_q35.c | 7 ++-----
hw/pci-host/q35.c | 36 +++++++++++++++++++++++++++++++-----
include/hw/i386/pc.h | 3 +--
include/hw/pci-host/q35.h | 9 +++++++--
6 files changed, 43 insertions(+), 17 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 909307e..398b201 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1029,8 +1029,7 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
const char *initrd_filename,
ram_addr_t below_4g_mem_size,
ram_addr_t above_4g_mem_size,
- MemoryRegion *rom_memory,
- MemoryRegion **ram_memory)
+ MemoryRegion *rom_memory)
{
int linux_boot, i;
MemoryRegion *option_rom_mr;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 4614c07..77d7ef0 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -139,7 +139,7 @@ static void pc_init1(MemoryRegion *system_memory,
fw_cfg = pc_memory_init(system_memory,
kernel_filename, kernel_cmdline, initrd_filename,
below_4g_mem_size, above_4g_mem_size,
- rom_memory, NULL);
+ rom_memory);
}
if (kvm_irqchip_in_kernel()) {
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 109bb64..d7d9703 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -65,7 +65,6 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
ISADevice *rtc_state;
ISADevice *floppy;
MemoryRegion *rom_memory;
- MemoryRegion *ram_memory;
GSIState *gsi_state;
ISABus *isa_bus;
int pci_enabled = 1;
@@ -108,7 +107,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
if (!xen_enabled()) {
pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
initrd_filename, below_4g_mem_size, above_4g_mem_size,
- rom_memory, &ram_memory);
+ rom_memory);
}
/* irq lines */
@@ -121,11 +120,9 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
}
- q35_host->mch.ram_memory = ram_memory;
+ q35_host->mch.ram_size = ram_size;
q35_host->mch.system_memory = get_system_memory();
q35_host->mch.address_space_io = get_system_io();
- q35_host->mch.below_4g_mem_size = below_4g_mem_size;
- q35_host->mch.above_4g_mem_size = above_4g_mem_size;
/* pci */
qdev_init_nofail(DEVICE(q35_host));
host_bus = q35_host->host.pci.bus;
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 3ab5ed8..5f99431 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -244,24 +244,50 @@ static int mch_init(PCIDevice *d)
{
int i;
hwaddr pci_hole64_size;
+ hwaddr below_4g_mem_size, above_4g_mem_size;
MCHPCIState *mch = MCH_PCI_DEVICE(d);
+ if(mch->ram_size > MCH_PCI_HOLE) {
+ below_4g_mem_size = MCH_PCI_HOLE;
+ above_4g_mem_size = mch->ram_size - MCH_PCI_HOLE;
+ } else {
+ below_4g_mem_size = mch->ram_size;
+ above_4g_mem_size = 0;
+ }
+
+ /* Allocate RAM. We allocate it as a single memory region and use
+ * aliases to address portions of it, mostly for backwards compatibility
+ * with older qemus that used qemu_ram_alloc().
+ */
+ memory_region_init_ram(&mch->ram, "pc.ram",
+ below_4g_mem_size + above_4g_mem_size);
+ vmstate_register_ram_global(&mch->ram);
+ memory_region_init_alias(&mch->ram_below_4g, "ram-below-4g", &mch->ram,
+ 0, below_4g_mem_size);
+ memory_region_add_subregion(mch->system_memory, 0, &mch->ram_below_4g);
+ if (above_4g_mem_size > 0) {
+ memory_region_init_alias(&mch->ram_above_4g, "ram-above-4g", &mch->ram,
+ below_4g_mem_size, above_4g_mem_size);
+ memory_region_add_subregion(mch->system_memory, MCH_PCI_HOLE_END,
+ &mch->ram_above_4g);
+ }
+
/* setup pci memory regions */
memory_region_init_alias(&mch->pci_hole, "pci-hole",
mch->pci_address_space,
- mch->below_4g_mem_size,
- 0x100000000ULL - mch->below_4g_mem_size);
- memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size,
+ below_4g_mem_size,
+ 0x100000000ULL - below_4g_mem_size);
+ memory_region_add_subregion(mch->system_memory, below_4g_mem_size,
&mch->pci_hole);
pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 :
((uint64_t)1 << 62));
memory_region_init_alias(&mch->pci_hole_64bit, "pci-hole64",
mch->pci_address_space,
- 0x100000000ULL + mch->above_4g_mem_size,
+ 0x100000000ULL + above_4g_mem_size,
pci_hole64_size);
if (pci_hole64_size) {
memory_region_add_subregion(mch->system_memory,
- 0x100000000ULL + mch->above_4g_mem_size,
+ 0x100000000ULL + above_4g_mem_size,
&mch->pci_hole_64bit);
}
/* smram */
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 702a63c..5f60365 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -91,8 +91,7 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
const char *initrd_filename,
ram_addr_t below_4g_mem_size,
ram_addr_t above_4g_mem_size,
- MemoryRegion *rom_memory,
- MemoryRegion **ram_memory);
+ MemoryRegion *rom_memory);
qemu_irq *pc_allocate_cpu_irq(void);
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index 1c02420..1e985b4 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -53,8 +53,10 @@ typedef struct MCHPCIState {
MemoryRegion pci_hole;
MemoryRegion pci_hole_64bit;
uint8_t smm_enabled;
- ram_addr_t below_4g_mem_size;
- ram_addr_t above_4g_mem_size;
+ ram_addr_t ram_size;
+ MemoryRegion ram;
+ MemoryRegion ram_below_4g;
+ MemoryRegion ram_above_4g;
} MCHPCIState;
typedef struct Q35PCIHost {
@@ -147,4 +149,7 @@ typedef struct Q35PCIHost {
#define MCH_PCIE_DEV 1
#define MCH_PCIE_FUNC 0
+#define MCH_PCI_HOLE 0xB0000000ULL
+#define MCH_PCI_HOLE_END 0x100000000ULL
+
#endif /* HW_Q35_H */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 11/15] introduce ISAPc
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
` (9 preceding siblings ...)
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 10/15] q35-mch: move ram initialization into q35-mch Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 12/15] introduce memory controller Hu Tao
` (3 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Previous refactor breaks isapc. This patch introduces ISAPc and move
isapc initializing code to ISAPc.
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/i386/pc_piix.c | 15 +++++++++++----
hw/isa/Makefile.objs | 2 +-
hw/isa/isa_pc.c | 42 ++++++++++++++++++++++++++++++++++++++++++
include/hw/isa/isa_pc.h | 26 ++++++++++++++++++++++++++
4 files changed, 80 insertions(+), 5 deletions(-)
create mode 100644 hw/isa/isa_pc.c
create mode 100644 include/hw/isa/isa_pc.h
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 77d7ef0..2e84cc2 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -49,6 +49,7 @@
#ifdef CONFIG_XEN
# include <xen/hvm/hvm_info_table.h>
#endif
+#include "hw/isa/isa_pc.h"
#define MAX_IDE_BUS 2
@@ -72,7 +73,7 @@ static void pc_init1(MemoryRegion *system_memory,
{
int i;
ram_addr_t below_4g_mem_size, above_4g_mem_size;
- PCIBus *pci_bus;
+ PCIBus *pci_bus = NULL;
ISABus *isa_bus;
int piix3_devfn = -1;
qemu_irq *cpu_irq;
@@ -88,6 +89,7 @@ static void pc_init1(MemoryRegion *system_memory,
MemoryRegion *rom_memory;
DeviceState *icc_bridge;
FWCfgState *fw_cfg = NULL;
+ ISAPc *isapc = NULL;
icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
object_property_add_child(qdev_get_machine(), "icc-bridge",
@@ -122,8 +124,13 @@ static void pc_init1(MemoryRegion *system_memory,
system_memory, system_io, ram_size,
&pci_memory);
} else {
- pci_bus = NULL;
- isa_bus = isa_bus_new(NULL, system_io);
+ isapc = ISA_PC(object_new(TYPE_ISA_PC));
+ isapc->ram_size = ram_size;
+ isapc->address_space_mem = system_memory;
+ isapc->address_space_io = system_io;
+ qdev_init_nofail(DEVICE(isapc));
+
+ isa_bus = isapc->bus;
no_hpet = 1;
}
isa_bus_irqs(isa_bus, gsi);
@@ -161,7 +168,7 @@ static void pc_init1(MemoryRegion *system_memory,
pc_register_ferr_irq(gsi[13]);
- pc_vga_init(isa_bus, pci_enabled ? pci_bus : NULL);
+ pc_vga_init(isa_bus, pci_bus);
if (xen_enabled()) {
pci_create_simple(pci_bus, -1, "xen-platform");
}
diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs
index 193746a..99e6a4f 100644
--- a/hw/isa/Makefile.objs
+++ b/hw/isa/Makefile.objs
@@ -1,4 +1,4 @@
-common-obj-y += isa-bus.o
+common-obj-y += isa-bus.o isa_pc.o
common-obj-$(CONFIG_APM) += apm.o
common-obj-$(CONFIG_I82378) += i82378.o
common-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o
diff --git a/hw/isa/isa_pc.c b/hw/isa/isa_pc.c
new file mode 100644
index 0000000..f73cddb
--- /dev/null
+++ b/hw/isa/isa_pc.c
@@ -0,0 +1,42 @@
+#include "hw/isa/isa_pc.h"
+
+static void isa_pc_realize(DeviceState *dev, Error **errp)
+{
+ ISAPc *isapc = ISA_PC(dev);
+
+ g_assert(isapc->address_space_mem != NULL);
+ g_assert(isapc->address_space_io != NULL);
+ g_assert(isapc->ram_size > 0);
+
+ isapc->bus = isa_bus_new(NULL, isapc->address_space_io);
+
+ /* Allocate RAM. We allocate it as a single memory region and use
+ * aliases to address portions of it, mostly for backwards compatibility
+ * with older qemus that used qemu_ram_alloc().
+ */
+ memory_region_init_ram(&isapc->ram, "pc.ram", isapc->ram_size);
+ vmstate_register_ram_global(&isapc->ram);
+ memory_region_add_subregion(isapc->address_space_mem, 0, &isapc->ram);
+}
+
+static void isa_pc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = isa_pc_realize;
+ dc->no_user = 1;
+}
+
+static const TypeInfo isa_pc_type_info = {
+ .name = TYPE_ISA_PC,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(ISAPc),
+ .class_init = isa_pc_class_init,
+};
+
+static void isa_pc_register_types(void)
+{
+ type_register_static(&isa_pc_type_info);
+}
+
+type_init(isa_pc_register_types)
diff --git a/include/hw/isa/isa_pc.h b/include/hw/isa/isa_pc.h
new file mode 100644
index 0000000..91a0701
--- /dev/null
+++ b/include/hw/isa/isa_pc.h
@@ -0,0 +1,26 @@
+#ifndef ISA_PC_H
+#define ISA_PC_H
+
+#include "qom/object.h"
+#include "exec/memory.h"
+#include "hw/isa/isa.h"
+
+#define TYPE_ISA_PC "isa-pc"
+#define ISA_PC(obj) OBJECT_CHECK(ISAPc, (obj), TYPE_ISA_PC)
+
+typedef struct ISAPc ISAPc;
+
+struct ISAPc {
+ /*< private >*/
+ Object parent_obj;
+ /*< public >*/
+
+ ISABus *bus;
+
+ MemoryRegion *address_space_mem;
+ MemoryRegion *address_space_io;
+ MemoryRegion ram;
+ ram_addr_t ram_size;
+};
+
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 12/15] introduce memory controller
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
` (10 preceding siblings ...)
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 11/15] introduce ISAPc Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 13/15] i440fx pmc: inherit from MemoryController Hu Tao
` (2 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/i386/pc.c | 156 +++++++++++++++++++++++++++++++++++++++++++++++++++
hw/pci-host/piix.c | 1 -
include/hw/i386/pc.h | 43 ++++++++++++++
3 files changed, 199 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 398b201..c28baa2 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1256,3 +1256,159 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
}
}
+
+void mc_update_pam(MemoryController *d)
+{
+ PCIDevice *pd = PCI_DEVICE(d);
+ MemoryControllerClass *c = MEMORY_CONTROLLER_GET_CLASS(d);
+ int i;
+
+ memory_region_transaction_begin();
+ for (i = 0; i < 13; i++) {
+ pam_update(&d->pam_regions[i], i,
+ pd->config[c->pam0 + ((i + 1) / 2)]);
+ }
+ memory_region_transaction_commit();
+}
+
+void mc_update_smram(MemoryController *d)
+{
+ PCIDevice *pd = PCI_DEVICE(d);
+ MemoryControllerClass *c = MEMORY_CONTROLLER_GET_CLASS(d);
+
+ memory_region_transaction_begin();
+ smram_update(&d->smram_region, pd->config[c->smram],
+ d->smm_enabled);
+ memory_region_transaction_commit();
+}
+
+void mc_update(MemoryController *d)
+{
+ mc_update_pam(d);
+ mc_update_smram(d);
+}
+
+void mc_set_smm(int val, void *arg)
+{
+ MemoryController *d = arg;
+ PCIDevice *pd = PCI_DEVICE(d);
+ MemoryControllerClass *c = MEMORY_CONTROLLER_GET_CLASS(d);
+
+ memory_region_transaction_begin();
+ smram_set_smm(&d->smm_enabled, val, pd->config[c->smram],
+ &d->smram_region);
+ memory_region_transaction_commit();
+}
+
+static int memory_controller_init(PCIDevice *dev)
+{
+ MemoryController *m = MEMORY_CONTROLLER(dev);
+ MemoryControllerClass *c = MEMORY_CONTROLLER_GET_CLASS(dev);
+ ram_addr_t ram_size;
+ hwaddr below_4g_mem_size, above_4g_mem_size;
+ hwaddr pci_hole_start, pci_hole_size;
+ hwaddr pci_hole64_start, pci_hole64_size;
+ int i;
+
+ g_assert(m->system_memory != NULL);
+
+ if(m->ram_size > c->pci_hole_start) {
+ below_4g_mem_size = c->pci_hole_start;
+ above_4g_mem_size = m->ram_size - c->pci_hole_start;
+ } else {
+ below_4g_mem_size = m->ram_size;
+ above_4g_mem_size = 0;
+ }
+
+ /* Allocate RAM. We allocate it as a single memory region and use
+ * aliases to address portions of it, mostly for backwards compatibility
+ * with older qemus that used qemu_ram_alloc().
+ */
+ memory_region_init_ram(&m->ram, "pc.ram", m->ram_size);
+ vmstate_register_ram_global(&m->ram);
+ memory_region_init_alias(&m->ram_below_4g, "ram-below-4g", &m->ram,
+ 0, below_4g_mem_size);
+ memory_region_add_subregion(m->system_memory, 0, &m->ram_below_4g);
+ if (above_4g_mem_size > 0) {
+ memory_region_init_alias(&m->ram_above_4g, "ram-above-4g", &m->ram,
+ below_4g_mem_size, above_4g_mem_size);
+ memory_region_add_subregion(m->system_memory, c->pci_hole_end,
+ &m->ram_above_4g);
+ }
+
+ pci_hole_start = below_4g_mem_size;
+ pci_hole_size = c->pci_hole_end - pci_hole_start;
+
+ pci_hole64_start = c->pci_hole_end + m->ram_size - pci_hole_start;
+ if (sizeof(hwaddr) == 4) {
+ pci_hole64_size = 0;
+ } else {
+ pci_hole64_size = (1ULL << 62);
+ }
+
+ memory_region_init_alias(&m->pci_hole, "pci-hole", m->pci_address_space,
+ pci_hole_start, pci_hole_size);
+ memory_region_add_subregion(m->system_memory, pci_hole_start,
+ &m->pci_hole);
+ memory_region_init_alias(&m->pci_hole_64bit, "pci-hole64",
+ m->pci_address_space,
+ pci_hole64_start, pci_hole64_size);
+ if (pci_hole64_size) {
+ memory_region_add_subregion(m->system_memory, pci_hole64_start,
+ &m->pci_hole_64bit);
+ }
+ memory_region_init_alias(&m->smram_region, "smram-region",
+ m->pci_address_space, 0xa0000, 0x20000);
+ memory_region_add_subregion_overlap(m->system_memory, 0xa0000,
+ &m->smram_region, 1);
+ memory_region_set_enabled(&m->smram_region, false);
+
+ init_pam(m->ram_memory, m->system_memory, m->pci_address_space,
+ &m->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
+ for (i = 0; i < 12; ++i) {
+ init_pam(m->ram_memory, m->system_memory, m->pci_address_space,
+ &m->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
+ PAM_EXPAN_SIZE);
+ }
+
+ ram_size = m->ram_size / 8 / 1024 / 1024;
+ if (ram_size > 255) {
+ ram_size = 255;
+ }
+ dev->config[0x57] = ram_size;
+
+ dev->config[0x72] = 0x02;
+
+ cpu_smm_register(c->set_smm, m);
+ return 0;
+}
+
+static void memory_controller_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ MemoryControllerClass *mc = MEMORY_CONTROLLER_CLASS(klass);
+
+ k->no_hotplug = 1;
+ k->init = memory_controller_init;
+ k->class_id = PCI_CLASS_BRIDGE_HOST;
+ dc->desc = "Host bridge";
+ dc->no_user = 1;
+ mc->set_smm = mc_set_smm;
+ mc->update = mc_update;
+}
+
+static const TypeInfo memory_controller_type_info = {
+ .name = TYPE_MEMORY_CONTROLLER,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(MemoryController),
+ .class_init = memory_controller_class_init,
+ .class_size = sizeof(MemoryControllerClass),
+};
+
+static void memory_controller_register_types(void)
+{
+ type_register_static(&memory_controller_type_info);
+}
+
+type_init(memory_controller_register_types)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 5318ddc..44ebe0f 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -99,7 +99,6 @@ struct I440FXPMCState {
MemoryRegion ram;
MemoryRegion ram_below_4g;
MemoryRegion ram_above_4g;
-
};
#define TYPE_I440FX_DEVICE "i440FX"
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 5f60365..f06008b 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -8,6 +8,49 @@
#include "hw/block/fdc.h"
#include "net/net.h"
#include "hw/i386/ioapic.h"
+#include "hw/pci/pci.h"
+#include "hw/pci-host/pam.h"
+
+#define TYPE_MEMORY_CONTROLLER "memory controller"
+#define MEMORY_CONTROLLER(obj) OBJECT_CHECK(MemoryController, (obj), TYPE_DEVICE)
+#define MEMORY_CONTROLLER_CLASS(klass) OBJECT_CLASS_CHECK(MemoryControllerClass, (klass), TYPE_MEMORY_CONTROLLER)
+#define MEMORY_CONTROLLER_GET_CLASS(obj) OBJECT_GET_CLASS(MemoryControllerClass, (obj), TYPE_MEMORY_CONTROLLER)
+
+typedef struct MemoryController MemoryController;
+typedef struct MemoryControllerClass MemoryControllerClass;
+
+typedef struct MemoryControllerClass {
+ PCIDeviceClass parent_class;
+
+ hwaddr pci_hole_start;
+ hwaddr pci_hole_end;
+ uint16_t pam0;
+ uint16_t smram;
+
+ void (*set_smm)(int val, void *arg);
+ void (*update)(MemoryController *m);
+} MemoryControllerClass;
+
+typedef struct MemoryController {
+ PCIDevice dev;
+ MemoryRegion *system_memory;
+ MemoryRegion *pci_address_space;
+ MemoryRegion *ram_memory;
+ MemoryRegion pci_hole;
+ MemoryRegion pci_hole_64bit;
+ PAMMemoryRegion pam_regions[13];
+ MemoryRegion smram_region;
+ uint8_t smm_enabled;
+ ram_addr_t ram_size;
+ MemoryRegion ram;
+ MemoryRegion ram_below_4g;
+ MemoryRegion ram_above_4g;
+} MemoryController;
+
+void mc_update_pam(MemoryController *d);
+void mc_update_smram(MemoryController *d);
+void mc_update(MemoryController *d);
+void mc_set_smm(int val, void *arg);
/* PC-style peripherals (also used by other machines). */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 13/15] i440fx pmc: inherit from MemoryController
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
` (11 preceding siblings ...)
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 12/15] introduce memory controller Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 14/15] q35 mch: " Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 15/15] move bios loading to MemoryController and ISAPc Hu Tao
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/pci-host/piix.c | 159 ++++++++---------------------------------------------
1 file changed, 22 insertions(+), 137 deletions(-)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 44ebe0f..71a9b8b 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -86,19 +86,7 @@ typedef struct PIIX3State {
OBJECT_CHECK(I440FXPMCState, (obj), TYPE_I440FX_PMC_DEVICE)
struct I440FXPMCState {
- PCIDevice dev;
- MemoryRegion *system_memory;
- MemoryRegion *pci_address_space;
- MemoryRegion *ram_memory;
- MemoryRegion pci_hole;
- MemoryRegion pci_hole_64bit;
- PAMMemoryRegion pam_regions[13];
- MemoryRegion smram_region;
- uint8_t smm_enabled;
- ram_addr_t ram_size;
- MemoryRegion ram;
- MemoryRegion ram_below_4g;
- MemoryRegion ram_above_4g;
+ MemoryController dev;
};
#define TYPE_I440FX_DEVICE "i440FX"
@@ -133,52 +121,32 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
return (pci_intx + slot_addend) & 3;
}
-static void i440fx_pmc_update_memory_mappings(I440FXPMCState *d)
-{
- int i;
-
- memory_region_transaction_begin();
- for (i = 0; i < 13; i++) {
- pam_update(&d->pam_regions[i], i,
- d->dev.config[I440FX_PAM + ((i + 1) / 2)]);
- }
- smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
- memory_region_transaction_commit();
-}
-
-static void i440fx_set_smm(int val, void *arg)
+static void i440fx_pmc_reset(DeviceState *d)
{
- I440FXPMCState *d = arg;
-
- memory_region_transaction_begin();
- smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
- &d->smram_region);
- memory_region_transaction_commit();
+ mc_update(MEMORY_CONTROLLER(d));
}
-
static void i440fx_write_config(PCIDevice *dev,
uint32_t address, uint32_t val, int len)
{
- I440FXPMCState *d = I440FX_PMC_DEVICE(dev);
-
/* XXX: implement SMRAM.D_LOCK */
pci_default_write_config(dev, address, val, len);
if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
range_covers_byte(address, len, I440FX_SMRAM)) {
- i440fx_pmc_update_memory_mappings(d);
+ mc_update(MEMORY_CONTROLLER(dev));
}
}
static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
{
- I440FXPMCState *d = opaque;
+ MemoryController *d = opaque;
int ret, i;
ret = pci_device_load(&d->dev, f);
if (ret < 0)
return ret;
- i440fx_pmc_update_memory_mappings(d);
+
+ mc_update(MEMORY_CONTROLLER(d));
qemu_get_8s(f, &d->smm_enabled);
if (version_id == 2) {
@@ -192,9 +160,9 @@ static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
static int i440fx_post_load(void *opaque, int version_id)
{
- I440FXPMCState *d = opaque;
+ MemoryController *d = opaque;
- i440fx_pmc_update_memory_mappings(d);
+ mc_update(d);
return 0;
}
@@ -206,8 +174,8 @@ static const VMStateDescription vmstate_i440fx_pmc = {
.load_state_old = i440fx_load_old,
.post_load = i440fx_post_load,
.fields = (VMStateField []) {
- VMSTATE_PCI_DEVICE(dev, I440FXPMCState),
- VMSTATE_UINT8(smm_enabled, I440FXPMCState),
+ VMSTATE_PCI_DEVICE(dev.dev, I440FXPMCState),
+ VMSTATE_UINT8(dev.smm_enabled, I440FXPMCState),
VMSTATE_END_OF_LIST()
}
};
@@ -230,7 +198,7 @@ static int i440fx_realize(SysBusDevice *dev)
sysbus_add_io(dev, 0xcfc, &s->data_mem);
sysbus_init_ioports(&s->busdev, 0xcfc, 4);
- f->pmc.pci_address_space = &f->pci_address_space;
+ f->pmc.dev.pci_address_space = &f->pci_address_space;
qdev_set_parent_bus(DEVICE(&f->pmc), BUS(s->bus));
qdev_init_nofail(DEVICE(&f->pmc));
@@ -249,91 +217,6 @@ static void i440fx_initfn(Object *obj)
memory_region_init(&f->pci_address_space, "pci", INT64_MAX);
}
-static int i440fx_pmc_initfn(PCIDevice *dev)
-{
- I440FXPMCState *d = I440FX_PMC_DEVICE(dev);
- ram_addr_t ram_size;
- hwaddr below_4g_mem_size, above_4g_mem_size;
- hwaddr pci_hole_start, pci_hole_size;
- hwaddr pci_hole64_start, pci_hole64_size;
- int i;
-
- g_assert(d->system_memory != NULL);
-
- if(d->ram_size > I440FX_PMC_PCI_HOLE) {
- below_4g_mem_size = I440FX_PMC_PCI_HOLE;
- above_4g_mem_size = d->ram_size - I440FX_PMC_PCI_HOLE;
- } else {
- below_4g_mem_size = d->ram_size;
- above_4g_mem_size = 0;
- }
-
- /* Allocate RAM. We allocate it as a single memory region and use
- * aliases to address portions of it, mostly for backwards compatibility
- * with older qemus that used qemu_ram_alloc().
- */
- memory_region_init_ram(&d->ram, "pc.ram",
- below_4g_mem_size + above_4g_mem_size);
- vmstate_register_ram_global(&d->ram);
- memory_region_init_alias(&d->ram_below_4g, "ram-below-4g", &d->ram,
- 0, below_4g_mem_size);
- memory_region_add_subregion(d->system_memory, 0, &d->ram_below_4g);
- if (above_4g_mem_size > 0) {
- memory_region_init_alias(&d->ram_above_4g, "ram-above-4g", &d->ram,
- below_4g_mem_size, above_4g_mem_size);
- memory_region_add_subregion(d->system_memory, I440FX_PMC_PCI_HOLE_END,
- &d->ram_above_4g);
- }
-
- pci_hole_start = below_4g_mem_size;
- pci_hole_size = I440FX_PMC_PCI_HOLE_END - pci_hole_start;
-
- pci_hole64_start = I440FX_PMC_PCI_HOLE_END + d->ram_size - pci_hole_start;
- if (sizeof(hwaddr) == 4) {
- pci_hole64_size = 0;
- } else {
- pci_hole64_size = (1ULL << 62);
- }
-
- memory_region_init_alias(&d->pci_hole, "pci-hole", d->pci_address_space,
- pci_hole_start, pci_hole_size);
- memory_region_add_subregion(d->system_memory, pci_hole_start,
- &d->pci_hole);
- memory_region_init_alias(&d->pci_hole_64bit, "pci-hole64",
- d->pci_address_space,
- pci_hole64_start, pci_hole64_size);
- if (pci_hole64_size) {
- memory_region_add_subregion(d->system_memory, pci_hole64_start,
- &d->pci_hole_64bit);
- }
- memory_region_init_alias(&d->smram_region, "smram-region",
- d->pci_address_space, 0xa0000, 0x20000);
- memory_region_add_subregion_overlap(d->system_memory, 0xa0000,
- &d->smram_region, 1);
- memory_region_set_enabled(&d->smram_region, false);
-
- init_pam(d->ram_memory, d->system_memory, d->pci_address_space,
- &d->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
- for (i = 0; i < 12; ++i) {
- init_pam(d->ram_memory, d->system_memory, d->pci_address_space,
- &d->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
- PAM_EXPAN_SIZE);
- }
-
- ram_size = d->ram_size / 8 / 1024 / 1024;
- if (ram_size > 255) {
- ram_size = 255;
- }
- d->dev.config[0x57] = ram_size;
-
- i440fx_pmc_update_memory_mappings(d);
-
- d->dev.config[I440FX_SMRAM] = 0x02;
-
- cpu_smm_register(&i440fx_set_smm, d);
- return 0;
-}
-
static PCIBus *i440fx_common_init(const char *device_name,
int *piix3_devfn,
ISABus **isa_bus, qemu_irq *pic,
@@ -353,8 +236,8 @@ static PCIBus *i440fx_common_init(const char *device_name,
i440fx->address_space_io = address_space_io;
f = &i440fx->pmc;
- f->ram_size = ram_size;
- f->system_memory = address_space_mem;
+ f->dev.ram_size = ram_size;
+ f->dev.system_memory = address_space_mem;
object_property_add_child(qdev_get_machine(), "i440fx",
OBJECT(i440fx), NULL);
@@ -675,22 +558,24 @@ static void i440fx_pmc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ MemoryControllerClass *mc = MEMORY_CONTROLLER_CLASS(klass);
- k->no_hotplug = 1;
- k->init = i440fx_pmc_initfn;
k->config_write = i440fx_write_config;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_82441;
k->revision = 0x02;
- k->class_id = PCI_CLASS_BRIDGE_HOST;
- dc->desc = "Host bridge";
- dc->no_user = 1;
dc->vmsd = &vmstate_i440fx_pmc;
+ dc->reset = i440fx_pmc_reset;
+
+ mc->pci_hole_start = 0xE0000000ULL;
+ mc->pci_hole_end = 0x100000000ULL;
+ mc->pam0 = I440FX_PAM;
+ mc->smram = I440FX_SMRAM;
}
static const TypeInfo i440fx_pmc_info = {
.name = TYPE_I440FX_PMC_DEVICE,
- .parent = TYPE_PCI_DEVICE,
+ .parent = TYPE_MEMORY_CONTROLLER,
.instance_size = sizeof(I440FXPMCState),
.class_init = i440fx_pmc_class_init,
};
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 14/15] q35 mch: inherit from MemoryController
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
` (12 preceding siblings ...)
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 13/15] i440fx pmc: inherit from MemoryController Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 15/15] move bios loading to MemoryController and ISAPc Hu Tao
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/i386/pc_q35.c | 4 +-
hw/pci-host/q35.c | 150 +++++++++-------------------------------------
include/hw/pci-host/q35.h | 14 +----
3 files changed, 32 insertions(+), 136 deletions(-)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index d7d9703..fde83b4 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -120,8 +120,8 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
}
- q35_host->mch.ram_size = ram_size;
- q35_host->mch.system_memory = get_system_memory();
+ q35_host->mch.dev.ram_size = ram_size;
+ q35_host->mch.dev.system_memory = get_system_memory();
q35_host->mch.address_space_io = get_system_io();
/* pci */
qdev_init_nofail(DEVICE(q35_host));
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 5f99431..0296550 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -53,10 +53,10 @@ static int q35_host_init(SysBusDevice *dev)
return -1;
}
- s->mch.pci_address_space = &s->pci_address_space;
- pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
- s->mch.pci_address_space, s->mch.address_space_io,
- 0, TYPE_PCIE_BUS);
+ s->mch.dev.pci_address_space = &s->pci_address_space;
+ pci->bus = pci_bus_new(DEVICE(dev), "pcie.0",
+ s->mch.dev.pci_address_space, s->mch.address_space_io,
+ 0, TYPE_PCIE_BUS);
qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
qdev_init_nofail(DEVICE(&s->mch));
@@ -106,8 +106,8 @@ static const TypeInfo q35_host_info = {
/* PCIe MMCFG */
static void mch_update_pciexbar(MCHPCIState *mch)
{
- PCIDevice *pci_dev = &mch->d;
- BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
+ PCIDevice *pci_dev = PCI_DEVICE(mch);
+ BusState *bus = qdev_get_parent_bus(DEVICE(pci_dev));
DeviceState *qdev = bus->parent;
Q35PCIHost *s = Q35_HOST_DEVICE(qdev);
@@ -144,49 +144,18 @@ static void mch_update_pciexbar(MCHPCIState *mch)
pcie_host_mmcfg_update(&s->host, enable, addr, length);
}
-/* PAM */
-static void mch_update_pam(MCHPCIState *mch)
-{
- int i;
-
- memory_region_transaction_begin();
- for (i = 0; i < 13; i++) {
- pam_update(&mch->pam_regions[i], i,
- mch->d.config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
- }
- memory_region_transaction_commit();
-}
-
-/* SMRAM */
-static void mch_update_smram(MCHPCIState *mch)
-{
- memory_region_transaction_begin();
- smram_update(&mch->smram_region, mch->d.config[MCH_HOST_BRDIGE_SMRAM],
- mch->smm_enabled);
- memory_region_transaction_commit();
-}
-
-static void mch_set_smm(int smm, void *arg)
-{
- MCHPCIState *mch = arg;
-
- memory_region_transaction_begin();
- smram_set_smm(&mch->smm_enabled, smm, mch->d.config[MCH_HOST_BRDIGE_SMRAM],
- &mch->smram_region);
- memory_region_transaction_commit();
-}
-
static void mch_write_config(PCIDevice *d,
- uint32_t address, uint32_t val, int len)
+ uint32_t address, uint32_t val, int len)
{
MCHPCIState *mch = MCH_PCI_DEVICE(d);
+ MemoryController *m = MEMORY_CONTROLLER(d);
/* XXX: implement SMRAM.D_LOCK */
pci_default_write_config(d, address, val, len);
if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
MCH_HOST_BRIDGE_PAM_SIZE)) {
- mch_update_pam(mch);
+ mc_update_pam(m);
}
if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
@@ -196,21 +165,23 @@ static void mch_write_config(PCIDevice *d,
if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM,
MCH_HOST_BRDIGE_SMRAM_SIZE)) {
- mch_update_smram(mch);
+ mc_update_smram(m);
}
}
-static void mch_update(MCHPCIState *mch)
+static void mch_update(MemoryController *d)
{
+ MCHPCIState *mch = MCH_PCI_DEVICE(d);
+
mch_update_pciexbar(mch);
- mch_update_pam(mch);
- mch_update_smram(mch);
+ mc_update_pam(d);
+ mc_update_smram(d);
}
static int mch_post_load(void *opaque, int version_id)
{
- MCHPCIState *mch = opaque;
- mch_update(mch);
+ MemoryController *m = opaque;
+ mch_update(m);
return 0;
}
@@ -221,8 +192,8 @@ static const VMStateDescription vmstate_mch = {
.minimum_version_id_old = 1,
.post_load = mch_post_load,
.fields = (VMStateField []) {
- VMSTATE_PCI_DEVICE(d, MCHPCIState),
- VMSTATE_UINT8(smm_enabled, MCHPCIState),
+ VMSTATE_PCI_DEVICE(dev.dev, MCHPCIState),
+ VMSTATE_UINT8(dev.smm_enabled, MCHPCIState),
VMSTATE_END_OF_LIST()
}
};
@@ -230,102 +201,39 @@ static const VMStateDescription vmstate_mch = {
static void mch_reset(DeviceState *qdev)
{
PCIDevice *d = PCI_DEVICE(qdev);
- MCHPCIState *mch = MCH_PCI_DEVICE(d);
+ MemoryController *m = MEMORY_CONTROLLER(d);
pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
- mch_update(mch);
-}
-
-static int mch_init(PCIDevice *d)
-{
- int i;
- hwaddr pci_hole64_size;
- hwaddr below_4g_mem_size, above_4g_mem_size;
- MCHPCIState *mch = MCH_PCI_DEVICE(d);
-
- if(mch->ram_size > MCH_PCI_HOLE) {
- below_4g_mem_size = MCH_PCI_HOLE;
- above_4g_mem_size = mch->ram_size - MCH_PCI_HOLE;
- } else {
- below_4g_mem_size = mch->ram_size;
- above_4g_mem_size = 0;
- }
-
- /* Allocate RAM. We allocate it as a single memory region and use
- * aliases to address portions of it, mostly for backwards compatibility
- * with older qemus that used qemu_ram_alloc().
- */
- memory_region_init_ram(&mch->ram, "pc.ram",
- below_4g_mem_size + above_4g_mem_size);
- vmstate_register_ram_global(&mch->ram);
- memory_region_init_alias(&mch->ram_below_4g, "ram-below-4g", &mch->ram,
- 0, below_4g_mem_size);
- memory_region_add_subregion(mch->system_memory, 0, &mch->ram_below_4g);
- if (above_4g_mem_size > 0) {
- memory_region_init_alias(&mch->ram_above_4g, "ram-above-4g", &mch->ram,
- below_4g_mem_size, above_4g_mem_size);
- memory_region_add_subregion(mch->system_memory, MCH_PCI_HOLE_END,
- &mch->ram_above_4g);
- }
-
- /* setup pci memory regions */
- memory_region_init_alias(&mch->pci_hole, "pci-hole",
- mch->pci_address_space,
- below_4g_mem_size,
- 0x100000000ULL - below_4g_mem_size);
- memory_region_add_subregion(mch->system_memory, below_4g_mem_size,
- &mch->pci_hole);
- pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 :
- ((uint64_t)1 << 62));
- memory_region_init_alias(&mch->pci_hole_64bit, "pci-hole64",
- mch->pci_address_space,
- 0x100000000ULL + above_4g_mem_size,
- pci_hole64_size);
- if (pci_hole64_size) {
- memory_region_add_subregion(mch->system_memory,
- 0x100000000ULL + above_4g_mem_size,
- &mch->pci_hole_64bit);
- }
- /* smram */
- cpu_smm_register(&mch_set_smm, mch);
- memory_region_init_alias(&mch->smram_region, "smram-region",
- mch->pci_address_space, 0xa0000, 0x20000);
- memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
- &mch->smram_region, 1);
- memory_region_set_enabled(&mch->smram_region, false);
- init_pam(mch->ram_memory, mch->system_memory, mch->pci_address_space,
- &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
- for (i = 0; i < 12; ++i) {
- init_pam(mch->ram_memory, mch->system_memory, mch->pci_address_space,
- &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
- PAM_EXPAN_SIZE);
- }
- return 0;
+ mch_update(m);
}
static void mch_class_init(ObjectClass *klass, void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
+ MemoryControllerClass *mc = MEMORY_CONTROLLER_CLASS(klass);
- k->init = mch_init;
k->config_write = mch_write_config;
dc->reset = mch_reset;
- dc->desc = "Host bridge";
dc->vmsd = &vmstate_mch;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT;
- k->class_id = PCI_CLASS_BRIDGE_HOST;
+
+ mc->pci_hole_start = MCH_PCI_HOLE;
+ mc->pci_hole_end = 0x100000000ULL;
+ mc->pam0 = MCH_HOST_BRIDGE_PAM0;
+ mc->smram = MCH_HOST_BRDIGE_SMRAM;
+ mc->update = mch_update;
}
static const TypeInfo mch_info = {
.name = TYPE_MCH_PCI_DEVICE,
- .parent = TYPE_PCI_DEVICE,
+ .parent = TYPE_MEMORY_CONTROLLER,
.instance_size = sizeof(MCHPCIState),
.class_init = mch_class_init,
};
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index 1e985b4..13dc30f 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -43,20 +43,8 @@
OBJECT_CHECK(MCHPCIState, (obj), TYPE_MCH_PCI_DEVICE)
typedef struct MCHPCIState {
- PCIDevice d;
- MemoryRegion *ram_memory;
- MemoryRegion *pci_address_space;
- MemoryRegion *system_memory;
+ MemoryController dev;
MemoryRegion *address_space_io;
- PAMMemoryRegion pam_regions[13];
- MemoryRegion smram_region;
- MemoryRegion pci_hole;
- MemoryRegion pci_hole_64bit;
- uint8_t smm_enabled;
- ram_addr_t ram_size;
- MemoryRegion ram;
- MemoryRegion ram_below_4g;
- MemoryRegion ram_above_4g;
} MCHPCIState;
typedef struct Q35PCIHost {
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH RFC 15/15] move bios loading to MemoryController and ISAPc
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
` (13 preceding siblings ...)
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 14/15] q35 mch: " Hu Tao
@ 2013-06-20 10:15 ` Hu Tao
14 siblings, 0 replies; 16+ messages in thread
From: Hu Tao @ 2013-06-20 10:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
hw/i386/pc.c | 35 ++++++++++++++---------------------
hw/i386/pc_piix.c | 13 ++-----------
hw/i386/pc_q35.c | 13 ++-----------
hw/isa/isa_pc.c | 11 +++++++++++
include/hw/i386/pc.h | 7 +++----
include/hw/isa/isa_pc.h | 1 +
6 files changed, 33 insertions(+), 47 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index c28baa2..5bb4989 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1023,36 +1023,19 @@ void pc_acpi_init(const char *default_dsdt)
}
}
-FWCfgState *pc_memory_init(MemoryRegion *system_memory,
- const char *kernel_filename,
+FWCfgState *pc_memory_init(const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size,
- MemoryRegion *rom_memory)
+ ram_addr_t above_4g_mem_size)
{
- int linux_boot, i;
- MemoryRegion *option_rom_mr;
+ int i;
FWCfgState *fw_cfg;
- linux_boot = (kernel_filename != NULL);
-
-
- /* Initialize PC system firmware */
- pc_system_firmware_init(rom_memory);
-
- option_rom_mr = g_malloc(sizeof(*option_rom_mr));
- memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
- vmstate_register_ram_global(option_rom_mr);
- memory_region_add_subregion_overlap(rom_memory,
- PC_ROM_MIN_VGA,
- option_rom_mr,
- 1);
-
fw_cfg = bochs_bios_init();
rom_set_fw(fw_cfg);
- if (linux_boot) {
+ if (kernel_filename) {
load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
}
@@ -1380,6 +1363,16 @@ static int memory_controller_init(PCIDevice *dev)
dev->config[0x72] = 0x02;
cpu_smm_register(c->set_smm, m);
+
+ pc_system_firmware_init(m->pci_address_space);
+
+ memory_region_init_ram(&m->option_roms, "pc.rom", PC_ROM_SIZE);
+ vmstate_register_ram_global(&m->option_roms);
+ memory_region_add_subregion_overlap(m->pci_address_space,
+ PC_ROM_MIN_VGA,
+ &m->option_roms,
+ 1);
+
return 0;
}
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 2e84cc2..fb056df 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -86,7 +86,6 @@ static void pc_init1(MemoryRegion *system_memory,
ISADevice *rtc_state;
ISADevice *floppy;
MemoryRegion *pci_memory;
- MemoryRegion *rom_memory;
DeviceState *icc_bridge;
FWCfgState *fw_cfg = NULL;
ISAPc *isapc = NULL;
@@ -135,18 +134,10 @@ static void pc_init1(MemoryRegion *system_memory,
}
isa_bus_irqs(isa_bus, gsi);
- if (pci_enabled) {
- rom_memory = pci_memory;
- } else {
- rom_memory = system_memory;
- }
-
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
- fw_cfg = pc_memory_init(system_memory,
- kernel_filename, kernel_cmdline, initrd_filename,
- below_4g_mem_size, above_4g_mem_size,
- rom_memory);
+ fw_cfg = pc_memory_init(kernel_filename, kernel_cmdline, initrd_filename,
+ below_4g_mem_size, above_4g_mem_size);
}
if (kvm_irqchip_in_kernel()) {
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index fde83b4..5fe14bb 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -64,7 +64,6 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
BusState *idebus[MAX_SATA_PORTS];
ISADevice *rtc_state;
ISADevice *floppy;
- MemoryRegion *rom_memory;
GSIState *gsi_state;
ISABus *isa_bus;
int pci_enabled = 1;
@@ -96,18 +95,10 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
below_4g_mem_size = ram_size;
}
- /* pci enabled */
- if (pci_enabled) {
- rom_memory = &q35_host->pci_address_space;
- } else {
- rom_memory = get_system_memory();
- }
-
/* allocate ram and load rom/bios */
if (!xen_enabled()) {
- pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
- initrd_filename, below_4g_mem_size, above_4g_mem_size,
- rom_memory);
+ pc_memory_init(kernel_filename, kernel_cmdline,
+ initrd_filename, below_4g_mem_size, above_4g_mem_size);
}
/* irq lines */
diff --git a/hw/isa/isa_pc.c b/hw/isa/isa_pc.c
index f73cddb..ae9f2c8 100644
--- a/hw/isa/isa_pc.c
+++ b/hw/isa/isa_pc.c
@@ -1,4 +1,6 @@
+#include "hw/i386/pc.h"
#include "hw/isa/isa_pc.h"
+#include "hw/loader.h"
static void isa_pc_realize(DeviceState *dev, Error **errp)
{
@@ -17,6 +19,15 @@ static void isa_pc_realize(DeviceState *dev, Error **errp)
memory_region_init_ram(&isapc->ram, "pc.ram", isapc->ram_size);
vmstate_register_ram_global(&isapc->ram);
memory_region_add_subregion(isapc->address_space_mem, 0, &isapc->ram);
+
+ pc_system_firmware_init(isapc->address_space_mem);
+
+ memory_region_init_ram(&isapc->option_roms, "pc.rom", PC_ROM_SIZE);
+ vmstate_register_ram_global(&isapc->option_roms);
+ memory_region_add_subregion_overlap(isapc->address_space_mem,
+ PC_ROM_MIN_VGA,
+ &isapc->option_roms,
+ 1);
}
static void isa_pc_class_init(ObjectClass *klass, void *data)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index f06008b..5d36558 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -36,6 +36,7 @@ typedef struct MemoryController {
MemoryRegion *system_memory;
MemoryRegion *pci_address_space;
MemoryRegion *ram_memory;
+ MemoryRegion option_roms;
MemoryRegion pci_hole;
MemoryRegion pci_hole_64bit;
PAMMemoryRegion pam_regions[13];
@@ -128,13 +129,11 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
void pc_hot_add_cpu(const int64_t id, Error **errp);
void pc_acpi_init(const char *default_dsdt);
-FWCfgState *pc_memory_init(MemoryRegion *system_memory,
- const char *kernel_filename,
+FWCfgState *pc_memory_init(const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size,
- MemoryRegion *rom_memory);
+ ram_addr_t above_4g_mem_size);
qemu_irq *pc_allocate_cpu_irq(void);
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
diff --git a/include/hw/isa/isa_pc.h b/include/hw/isa/isa_pc.h
index 91a0701..33a2e95 100644
--- a/include/hw/isa/isa_pc.h
+++ b/include/hw/isa/isa_pc.h
@@ -19,6 +19,7 @@ struct ISAPc {
MemoryRegion *address_space_mem;
MemoryRegion *address_space_io;
+ MemoryRegion option_roms;
MemoryRegion ram;
ram_addr_t ram_size;
};
--
1.8.3.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2013-06-20 10:17 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-06-20 10:14 [Qemu-devel] [PATCH RFC 00/15] pc refactor about memory controller Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 01/15] i440fx: remove unused parameter i440fx_state of i440fx_init Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 02/15] i440fx: rename i440FX to i440FX-PMC Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 03/15] i440fx: rename i440FX-pcihost to i440FX Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 04/15] i440fx: prepare for composition Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 05/15] i440fx pmc: create pmc through comosition Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 06/15] i440fx-pmc: calculate PCI memory hole directly Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 07/15] i440fx-pmc: create pci address space Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 08/15] q35-mch: " Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 09/15] i440fx-pmc: move ram initialization into i440fx-pmc Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 10/15] q35-mch: move ram initialization into q35-mch Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 11/15] introduce ISAPc Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 12/15] introduce memory controller Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 13/15] i440fx pmc: inherit from MemoryController Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 14/15] q35 mch: " Hu Tao
2013-06-20 10:15 ` [Qemu-devel] [PATCH RFC 15/15] move bios loading to MemoryController and ISAPc Hu Tao
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