[Qemu-devel] [PATCH arm-devs v2 0/8] Fix Support for ARM A9 CBAR

[Qemu-devel] [PATCH arm-devs v2 0/8] Fix Support for ARM A9 CBAR

[Peter Crosthwaite]

Hi Peter,

This patch series fixed the Configuration base address init logic for
ARM CPUs, most notably for A9. Fixes both Zynq and Highbank which both
had broken CBAR.

Regards,
Peter

Changed since v1:
Fix QOM to support writeable dynamic properties
Use dynamic props instead (PMM/AF discussion)
Use error_report (AF reivew)
Use reset- prefix on propname (AF reivew)
Fix machine model namings or the MPCore PERIPHBASE


Peter Crosthwaite (8):
  qom/object: Make uintXX added properties writable
  target-arm: Define and use ARM_FEATURE_CBAR
  target-arm/cpu: Convert reset CBAR to a property
  arm/highbank: Use object_new() rather than cpu_arm_init()
  arm/highbank: Fix CBAR intialisation
  arm/xilinx_zynq: Use object_new() rather than cpu_arm_init()
  arm/xilinx_zynq: Implement CBAR intialisation
  arm/highbank.c: Fix MPCore periphbase name

 hw/arm/highbank.c    | 33 +++++++++++++++++++++------------
 hw/arm/xilinx_zynq.c | 21 +++++++++++++++++----
 qom/object.c         | 44 ++++++++++++++++++++++++++++++++++++++++----
 target-arm/cpu.c     | 25 ++++++++++++++++---------
 target-arm/cpu.h     |  1 +
 target-arm/helper.c  |  9 +++++++++
 6 files changed, 104 insertions(+), 29 deletions(-)

-- 
1.8.4.4

[Qemu-devel] [PATCH arm-devs v2 1/8] qom/object: Make uintXX added properties writable

[Peter Crosthwaite]

Currently the uintXX property adders make a read only property. This
is not useful for devices that want to create board (or container)
configurable dynamic device properties. Fix by trivally adding property
setters to object_property_add_uintXX.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 qom/object.c | 44 ++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 40 insertions(+), 4 deletions(-)

diff --git a/qom/object.c b/qom/object.c
index fc19cf6..07b454b 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -1353,6 +1353,15 @@ static void property_get_uint8_ptr(Object *obj, Visitor *v,
     visit_type_uint8(v, &value, name, errp);
 }
 
+static void property_set_uint8_ptr(Object *obj, Visitor *v,
+                                   void *opaque, const char *name,
+                                   Error **errp)
+{
+    uint8_t value;
+    visit_type_uint8(v, &value, name, errp);
+    *(uint8_t *)opaque = value;
+}
+
 static void property_get_uint16_ptr(Object *obj, Visitor *v,
                                    void *opaque, const char *name,
                                    Error **errp)
@@ -1361,6 +1370,15 @@ static void property_get_uint16_ptr(Object *obj, Visitor *v,
     visit_type_uint16(v, &value, name, errp);
 }
 
+static void property_set_uint16_ptr(Object *obj, Visitor *v,
+                                    void *opaque, const char *name,
+                                    Error **errp)
+{
+    uint16_t value;
+    visit_type_uint16(v, &value, name, errp);
+    *(uint16_t *)opaque = value;
+}
+
 static void property_get_uint32_ptr(Object *obj, Visitor *v,
                                    void *opaque, const char *name,
                                    Error **errp)
@@ -1369,6 +1387,15 @@ static void property_get_uint32_ptr(Object *obj, Visitor *v,
     visit_type_uint32(v, &value, name, errp);
 }
 
+static void property_set_uint32_ptr(Object *obj, Visitor *v,
+                                    void *opaque, const char *name,
+                                    Error **errp)
+{
+    uint32_t value;
+    visit_type_uint32(v, &value, name, errp);
+    *(uint32_t *)opaque = value;
+}
+
 static void property_get_uint64_ptr(Object *obj, Visitor *v,
                                    void *opaque, const char *name,
                                    Error **errp)
@@ -1377,32 +1404,41 @@ static void property_get_uint64_ptr(Object *obj, Visitor *v,
     visit_type_uint64(v, &value, name, errp);
 }
 
+static void property_set_uint64_ptr(Object *obj, Visitor *v,
+                                    void *opaque, const char *name,
+                                    Error **errp)
+{
+    uint64_t value;
+    visit_type_uint64(v, &value, name, errp);
+    *(uint64_t *)opaque = value;
+}
+
 void object_property_add_uint8_ptr(Object *obj, const char *name,
                                    const uint8_t *v, Error **errp)
 {
     object_property_add(obj, name, "uint8", property_get_uint8_ptr,
-                        NULL, NULL, (void *)v, errp);
+                        property_set_uint8_ptr, NULL, (void *)v, errp);
 }
 
 void object_property_add_uint16_ptr(Object *obj, const char *name,
                                     const uint16_t *v, Error **errp)
 {
     object_property_add(obj, name, "uint16", property_get_uint16_ptr,
-                        NULL, NULL, (void *)v, errp);
+                        property_set_uint16_ptr, NULL, (void *)v, errp);
 }
 
 void object_property_add_uint32_ptr(Object *obj, const char *name,
                                     const uint32_t *v, Error **errp)
 {
     object_property_add(obj, name, "uint32", property_get_uint32_ptr,
-                        NULL, NULL, (void *)v, errp);
+                        property_set_uint32_ptr, NULL, (void *)v, errp);
 }
 
 void object_property_add_uint64_ptr(Object *obj, const char *name,
                                     const uint64_t *v, Error **errp)
 {
     object_property_add(obj, name, "uint64", property_get_uint64_ptr,
-                        NULL, NULL, (void *)v, errp);
+                        property_set_uint64_ptr, NULL, (void *)v, errp);
 }
 
 static void object_instance_init(Object *obj)
-- 
1.8.4.4

[Qemu-devel] [PATCH arm-devs v2 2/8] target-arm: Define and use ARM_FEATURE_CBAR

[Peter Crosthwaite]

Some processors (notably A9 within Highbank) define and use the
CP15 configuration base address (CBAR). This is vendor specific
so its best implemented as a CPU property (otherwise we would need
vendor specific child classes for every ARM implementation).

This patch prepares support for converting CBAR reset value to
a CPU property by moving the CP registration out of the CPU
init fn, as registration will need to happen at realize time
to pick up any property updates. The easiest way to do this
is via definition of a new ARM_FEATURE to flag the existance
of the register.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 target-arm/cpu.c    | 11 ++---------
 target-arm/cpu.h    |  1 +
 target-arm/helper.c |  9 +++++++++
 3 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index d40f2a7..a82fa61 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -585,6 +585,7 @@ static void cortex_a9_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR);
     /* Note that A9 supports the MP extensions even for
      * A9UP and single-core A9MP (which are both different
      * and valid configurations; we don't model A9UP).
@@ -612,15 +613,7 @@ static void cortex_a9_initfn(Object *obj)
     cpu->clidr = (1 << 27) | (1 << 24) | 3;
     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
-    {
-        ARMCPRegInfo cbar = {
-            .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,
-            .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
-            .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
-        };
-        define_one_arm_cp_reg(cpu, &cbar);
-        define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
-    }
+    define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 }
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 9f110f1..859750a 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -461,6 +461,7 @@ enum arm_features {
     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
+    ARM_FEATURE_CBAR, /* has cp15 CBAR */
     ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
     ARM_FEATURE_V8,
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3445813..1bf0305 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1744,6 +1744,15 @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_one_arm_cp_reg(cpu, &auxcr);
     }
 
+    if (arm_feature(env, ARM_FEATURE_CBAR)) {
+        ARMCPRegInfo cbar = {
+            .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
+            .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
+            .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
+        };
+        define_one_arm_cp_reg(cpu, &cbar);
+    }
+
     /* Generic registers whose values depend on the implementation */
     {
         ARMCPRegInfo sctlr = {
-- 
1.8.4.4

[Qemu-devel] [PATCH arm-devs v2 3/8] target-arm/cpu: Convert reset CBAR to a property

[Peter Crosthwaite]

The reset Value of the CP15 CBAR is a vendor (machine) configurable
property. If ARM_FEATURE_CBAR is set, add it as a property at
post_init time.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
Change since v1:
Re-implement as dynamic property

 target-arm/cpu.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index a82fa61..7ad2496 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -20,6 +20,7 @@
 
 #include "cpu.h"
 #include "qemu-common.h"
+#include "qapi/qmp/qerror.h"
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #endif
@@ -223,6 +224,18 @@ static void arm_cpu_initfn(Object *obj)
     }
 }
 
+static void arm_cpu_post_init(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    Error *err = NULL;
+
+    if (arm_feature(&cpu->env, ARM_FEATURE_CBAR)) {
+        object_property_add_uint32_ptr(obj, "reset-cbar", &cpu->reset_cbar,
+                                       &err);
+        assert_no_error(err);
+    }
+}
+
 static void arm_cpu_finalizefn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -933,6 +946,7 @@ static const TypeInfo arm_cpu_type_info = {
     .parent = TYPE_CPU,
     .instance_size = sizeof(ARMCPU),
     .instance_init = arm_cpu_initfn,
+    .instance_post_init = arm_cpu_post_init,
     .instance_finalize = arm_cpu_finalizefn,
     .abstract = true,
     .class_size = sizeof(ARMCPUClass),
-- 
1.8.4.4

[Qemu-devel] [PATCH arm-devs v2 4/8] arm/highbank: Use object_new() rather than cpu_arm_init()

[Peter Crosthwaite]

To allow the machine model to set device properties before CPU
realization.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
changed since v1:
use error_report rather than fprintf(stderr

 hw/arm/highbank.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index fe98ef1..1d19d8f 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -26,6 +26,7 @@
 #include "hw/boards.h"
 #include "sysemu/blockdev.h"
 #include "exec/address-spaces.h"
+#include "qemu/error-report.h"
 
 #define SMP_BOOT_ADDR 0x100
 #define SMP_BOOT_REG  0x40
@@ -229,10 +230,15 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
     }
 
     for (n = 0; n < smp_cpus; n++) {
+        ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
         ARMCPU *cpu;
-        cpu = cpu_arm_init(cpu_model);
-        if (cpu == NULL) {
-            fprintf(stderr, "Unable to find CPU definition\n");
+        Error *err = NULL;
+
+        cpu = ARM_CPU(object_new(object_class_get_name(oc)));
+
+        object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+        if (err) {
+            error_report("%s", error_get_pretty(err));
             exit(1);
         }
 
-- 
1.8.4.4

[Qemu-devel] [PATCH arm-devs v2 5/8] arm/highbank: Fix CBAR intialisation

[Peter Crosthwaite]

Fix the CBAR initialisation by using the newly defined static property.
CBAR is now set before realization, so the intended value is now
actually used.

So I have kinda tested this. I booted an ARM kernel on Highbank with the
stock Highbank DTB. It doesnt boot (and I will be doing something
wrong), but before this patch I got this:

------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at /workspaces/pcrost/public/linux2.git/arch/arm/mm/ioremap.c:301 __arm_ioremap_pfn_caller+0x180/0x198()
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W 3.13.0-rc1-next-20131126-dirty #2
[<c0015164>] (unwind_backtrace) from [<c00118c0>] (show_stack+0x10/0x14)
[<c00118c0>] (show_stack) from [<c02bd5fc>] (dump_stack+0x78/0x90)
[<c02bd5fc>] (dump_stack) from [<c001f110>] (warn_slowpath_common+0x68/0x84)
[<c001f110>] (warn_slowpath_common) from [<c001f1f4>] (warn_slowpath_null+0x1c/0x24)
[<c001f1f4>] (warn_slowpath_null) from [<c0017c6c>] (__arm_ioremap_pfn_caller+0x180/0x198)
[<c0017c6c>] (__arm_ioremap_pfn_caller) from [<c0017cd8>] (__arm_ioremap_caller+0x54/0x5c)
[<c0017cd8>] (__arm_ioremap_caller) from [<c0017d10>] (__arm_ioremap+0x18/0x1c)
[<c0017d10>] (__arm_ioremap) from [<c03913c0>] (highbank_init_irq+0x34/0x8c)
[<c03913c0>] (highbank_init_irq) from [<c038c228>] (init_IRQ+0x28/0x2c)
[<c038c228>] (init_IRQ) from [<c03899ec>] (start_kernel+0x234/0x398)
[<c03899ec>] (start_kernel) from [<00008074>] (0x8074)
---[ end trace 3406ff24bd97382f ]---

Which dissappears with this patch.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
changed since v1:
use error report rather than fprintf(stderr

 hw/arm/highbank.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 1d19d8f..cb32325 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -236,14 +236,16 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
 
         cpu = ARM_CPU(object_new(object_class_get_name(oc)));
 
+        object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar", &err);
+        if (err) {
+            error_report("%s", error_get_pretty(err));
+            exit(1);
+        }
         object_property_set_bool(OBJECT(cpu), true, "realized", &err);
         if (err) {
             error_report("%s", error_get_pretty(err));
             exit(1);
         }
-
-        /* This will become a QOM property eventually */
-        cpu->reset_cbar = GIC_BASE_ADDR;
         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
     }
 
-- 
1.8.4.4

Re: [Qemu-devel] [PATCH arm-devs v2 5/8] arm/highbank: Fix CBAR intialisation

[Peter Maydell]

On 28 November 2013 03:29, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> Fix the CBAR initialisation by using the newly defined static property.
> CBAR is now set before realization, so the intended value is now
> actually used.
>
> So I have kinda tested this. I booted an ARM kernel on Highbank with the
> stock Highbank DTB. It doesnt boot (and I will be doing something
> wrong), but before this patch I got this:
>
> ------------[ cut here ]------------
> WARNING: CPU: 0 PID: 0 at /workspaces/pcrost/public/linux2.git/arch/arm/mm/ioremap.c:301 __arm_ioremap_pfn_caller+0x180/0x198()
> CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W 3.13.0-rc1-next-20131126-dirty #2
> [<c0015164>] (unwind_backtrace) from [<c00118c0>] (show_stack+0x10/0x14)
> [<c00118c0>] (show_stack) from [<c02bd5fc>] (dump_stack+0x78/0x90)
> [<c02bd5fc>] (dump_stack) from [<c001f110>] (warn_slowpath_common+0x68/0x84)
> [<c001f110>] (warn_slowpath_common) from [<c001f1f4>] (warn_slowpath_null+0x1c/0x24)
> [<c001f1f4>] (warn_slowpath_null) from [<c0017c6c>] (__arm_ioremap_pfn_caller+0x180/0x198)
> [<c0017c6c>] (__arm_ioremap_pfn_caller) from [<c0017cd8>] (__arm_ioremap_caller+0x54/0x5c)
> [<c0017cd8>] (__arm_ioremap_caller) from [<c0017d10>] (__arm_ioremap+0x18/0x1c)
> [<c0017d10>] (__arm_ioremap) from [<c03913c0>] (highbank_init_irq+0x34/0x8c)
> [<c03913c0>] (highbank_init_irq) from [<c038c228>] (init_IRQ+0x28/0x2c)
> [<c038c228>] (init_IRQ) from [<c03899ec>] (start_kernel+0x234/0x398)
> [<c03899ec>] (start_kernel) from [<00008074>] (0x8074)
> ---[ end trace 3406ff24bd97382f ]---
>
> Which dissappears with this patch.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> ---
> changed since v1:
> use error report rather than fprintf(stderr
>
>  hw/arm/highbank.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
> index 1d19d8f..cb32325 100644
> --- a/hw/arm/highbank.c
> +++ b/hw/arm/highbank.c
> @@ -236,14 +236,16 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
>
>          cpu = ARM_CPU(object_new(object_class_get_name(oc)));
>
> +        object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar", &err);
> +        if (err) {
> +            error_report("%s", error_get_pretty(err));
> +            exit(1);
> +        }

It's kind of sad that we need five lines of code just to
say "set this property on this object which we should
know at compile time to exist" . (I was about to argue we
should just assert, but since we don't refuse to start with
wacky user-provided cpu-model strings we can't quite get
away with that.)

More significantly, this will break midway, because
cortex-a15 doesn't have this property. Fortunately, the
actual A15 does have a CBAR register so you can just
add a patch to set the feature bit for it.

Caution, this means our semantics for reset-cbar
are "actual reset value of register", which is not
the same as "base address of peripherals", because
for A15 the register has
 [31:15] bits 31:15 of base-addr
 [14:8] reserved, zero
 [7:0] bits 39:32 of base-addr

which makes a difference if you were nutty enough to
put the GIC above the 4GB boundary.

(As with the real hardware, setting this config property
doesn't actually change where the GIC & friends live
in the address space, incidentally.)

>          object_property_set_bool(OBJECT(cpu), true, "realized", &err);
>          if (err) {
>              error_report("%s", error_get_pretty(err));
>              exit(1);
>          }
> -
> -        /* This will become a QOM property eventually */
> -        cpu->reset_cbar = GIC_BASE_ADDR;
>          cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
>      }

thanks
-- PMM

Re: [Qemu-devel] [PATCH arm-devs v2 5/8] arm/highbank: Fix CBAR intialisation

[Peter Crosthwaite]

On Fri, Nov 29, 2013 at 5:34 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 28 November 2013 03:29, Peter Crosthwaite
> <peter.crosthwaite@xilinx.com> wrote:
>> Fix the CBAR initialisation by using the newly defined static property.
>> CBAR is now set before realization, so the intended value is now
>> actually used.
>>
>> So I have kinda tested this. I booted an ARM kernel on Highbank with the
>> stock Highbank DTB. It doesnt boot (and I will be doing something
>> wrong), but before this patch I got this:
>>
>> ------------[ cut here ]------------
>> WARNING: CPU: 0 PID: 0 at /workspaces/pcrost/public/linux2.git/arch/arm/mm/ioremap.c:301 __arm_ioremap_pfn_caller+0x180/0x198()
>> CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W 3.13.0-rc1-next-20131126-dirty #2
>> [<c0015164>] (unwind_backtrace) from [<c00118c0>] (show_stack+0x10/0x14)
>> [<c00118c0>] (show_stack) from [<c02bd5fc>] (dump_stack+0x78/0x90)
>> [<c02bd5fc>] (dump_stack) from [<c001f110>] (warn_slowpath_common+0x68/0x84)
>> [<c001f110>] (warn_slowpath_common) from [<c001f1f4>] (warn_slowpath_null+0x1c/0x24)
>> [<c001f1f4>] (warn_slowpath_null) from [<c0017c6c>] (__arm_ioremap_pfn_caller+0x180/0x198)
>> [<c0017c6c>] (__arm_ioremap_pfn_caller) from [<c0017cd8>] (__arm_ioremap_caller+0x54/0x5c)
>> [<c0017cd8>] (__arm_ioremap_caller) from [<c0017d10>] (__arm_ioremap+0x18/0x1c)
>> [<c0017d10>] (__arm_ioremap) from [<c03913c0>] (highbank_init_irq+0x34/0x8c)
>> [<c03913c0>] (highbank_init_irq) from [<c038c228>] (init_IRQ+0x28/0x2c)
>> [<c038c228>] (init_IRQ) from [<c03899ec>] (start_kernel+0x234/0x398)
>> [<c03899ec>] (start_kernel) from [<00008074>] (0x8074)
>> ---[ end trace 3406ff24bd97382f ]---
>>
>> Which dissappears with this patch.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> ---
>> changed since v1:
>> use error report rather than fprintf(stderr
>>
>>  hw/arm/highbank.c | 8 +++++---
>>  1 file changed, 5 insertions(+), 3 deletions(-)
>>
>> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
>> index 1d19d8f..cb32325 100644
>> --- a/hw/arm/highbank.c
>> +++ b/hw/arm/highbank.c
>> @@ -236,14 +236,16 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
>>
>>          cpu = ARM_CPU(object_new(object_class_get_name(oc)));
>>
>> +        object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar", &err);
>> +        if (err) {
>> +            error_report("%s", error_get_pretty(err));
>> +            exit(1);
>> +        }
>
> It's kind of sad that we need five lines of code just to
> say "set this property on this object which we should
> know at compile time to exist" . (I was about to argue we
> should just assert, but since we don't refuse to start with
> wacky user-provided cpu-model strings we can't quite get
> away with that.)
>
> More significantly, this will break midway, because
> cortex-a15 doesn't have this property. Fortunately, the
> actual A15 does have a CBAR register so you can just
> add a patch to set the feature bit for it.
>

Ok will fix - thanks. Should I just feature CBAR for all the CPU
families you listed in v1 discussion?

> Caution, this means our semantics for reset-cbar
> are "actual reset value of register", which is not
> the same as "base address of peripherals",

That was the intended semantic.

> because
> for A15 the register has
>  [31:15] bits 31:15 of base-addr
>  [14:8] reserved, zero
>  [7:0] bits 39:32 of base-addr
>

Yes, so I i'm still of the opinion that this stuff is the
responsibility of MPCore not ARM_CPU. Ideally, we move the ARM cpus
into MPCore. Then boards set periphbase of mpcores and mpcores set
CBARs. Keeps CPUs unaware of periphbase mangling complications like
this. And keeps boards unaware of CBARs.

Regards,
Peter

> which makes a difference if you were nutty enough to
> put the GIC above the 4GB boundary.
>
> (As with the real hardware, setting this config property
> doesn't actually change where the GIC & friends live
> in the address space, incidentally.)
>
>>          object_property_set_bool(OBJECT(cpu), true, "realized", &err);
>>          if (err) {
>>              error_report("%s", error_get_pretty(err));
>>              exit(1);
>>          }
>> -
>> -        /* This will become a QOM property eventually */
>> -        cpu->reset_cbar = GIC_BASE_ADDR;
>>          cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
>>      }
>
> thanks
> -- PMM
>

Re: [Qemu-devel] [PATCH arm-devs v2 5/8] arm/highbank: Fix CBAR intialisation

[Peter Maydell]

On 28 November 2013 23:55, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> On Fri, Nov 29, 2013 at 5:34 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>> More significantly, this will break midway, because
>> cortex-a15 doesn't have this property. Fortunately, the
>> actual A15 does have a CBAR register so you can just
>> add a patch to set the feature bit for it.
>>
>
> Ok will fix - thanks. Should I just feature CBAR for all the CPU
> families you listed in v1 discussion?

I'm pretty sure the only two cores with CBAR that we
implement are A15 and A9. NB that the permissions on
the two registers are not the same, though -- check the
TRMs. (A15's is always r/o).

>> Caution, this means our semantics for reset-cbar
>> are "actual reset value of register", which is not
>> the same as "base address of peripherals",
>
> That was the intended semantic.
>
>> because
>> for A15 the register has
>>  [31:15] bits 31:15 of base-addr
>>  [14:8] reserved, zero
>>  [7:0] bits 39:32 of base-addr
>>
>
> Yes, so I i'm still of the opinion that this stuff is the
> responsibility of MPCore not ARM_CPU. Ideally, we move the ARM cpus
> into MPCore. Then boards set periphbase of mpcores and mpcores set
> CBARs. Keeps CPUs unaware of periphbase mangling complications like
> this. And keeps boards unaware of CBARs.

I'm in favour of eventually moving the cores
themselves into the *mpcore containers, though
I'm not entirely sure that the CBAR setting and
periphbase locations are a single setting on real
hardware config (as opposed to two different
settings that are supposed to be the same).

-- PMM

[Qemu-devel] [PATCH arm-devs v2 6/8] arm/xilinx_zynq: Use object_new() rather than cpu_arm_init()

[Peter Crosthwaite]

To allow the machine model to set device properties before CPU
realization.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
changed since v1:
use error report rather than fprintf(stderr

 hw/arm/xilinx_zynq.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 46924a0..1c954a3 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -25,6 +25,7 @@
 #include "sysemu/blockdev.h"
 #include "hw/loader.h"
 #include "hw/ssi.h"
+#include "qemu/error-report.h"
 
 #define NUM_SPI_FLASHES 4
 #define NUM_QSPI_FLASHES 2
@@ -102,6 +103,7 @@ static void zynq_init(QEMUMachineInitArgs *args)
     const char *kernel_filename = args->kernel_filename;
     const char *kernel_cmdline = args->kernel_cmdline;
     const char *initrd_filename = args->initrd_filename;
+    ObjectClass *cpu_oc;
     ARMCPU *cpu;
     MemoryRegion *address_space_mem = get_system_memory();
     MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
@@ -110,15 +112,19 @@ static void zynq_init(QEMUMachineInitArgs *args)
     SysBusDevice *busdev;
     qemu_irq pic[64];
     NICInfo *nd;
+    Error *err = NULL;
     int n;
 
     if (!cpu_model) {
         cpu_model = "cortex-a9";
     }
+    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 
-    cpu = cpu_arm_init(cpu_model);
-    if (!cpu) {
-        fprintf(stderr, "Unable to find CPU definition\n");
+    cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
+
+    object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+    if (err) {
+        error_report("%s", error_get_pretty(err));
         exit(1);
     }
 
-- 
1.8.4.4

[Qemu-devel] [PATCH arm-devs v2 7/8] arm/xilinx_zynq: Implement CBAR intialisation

[Peter Crosthwaite]

Fix the CBAR initialisation by using the newly defined static property.
Zynq will now correctly init the CBAR to the SCU base address.

Needed to boot Linux on the xilinx_zynq machine model.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
changed since v1:
use error report rather than fprintf(stderr
rename SCU_BASE_ADDR to MPCORE_PERIPHBASE

 hw/arm/xilinx_zynq.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 1c954a3..17251c7 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -36,6 +36,8 @@
 
 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
 
+#define MPCORE_PERIPHBASE 0xF8F00000
+
 static const int dma_irqs[8] = {
     46, 47, 48, 49, 72, 73, 74, 75
 };
@@ -122,6 +124,11 @@ static void zynq_init(QEMUMachineInitArgs *args)
 
     cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
 
+    object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", &err);
+    if (err) {
+        error_report("%s", error_get_pretty(err));
+        exit(1);
+    }
     object_property_set_bool(OBJECT(cpu), true, "realized", &err);
     if (err) {
         error_report("%s", error_get_pretty(err));
@@ -160,7 +167,7 @@ static void zynq_init(QEMUMachineInitArgs *args)
     qdev_prop_set_uint32(dev, "num-cpu", 1);
     qdev_init_nofail(dev);
     busdev = SYS_BUS_DEVICE(dev);
-    sysbus_mmio_map(busdev, 0, 0xF8F00000);
+    sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
     sysbus_connect_irq(busdev, 0,
                        qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
 
-- 
1.8.4.4

Re: [Qemu-devel] [PATCH arm-devs v2 7/8] arm/xilinx_zynq: Implement CBAR intialisation

[Peter Maydell]

On 28 November 2013 03:30, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> Fix the CBAR initialisation by using the newly defined static property.
> Zynq will now correctly init the CBAR to the SCU base address.
>
> Needed to boot Linux on the xilinx_zynq machine model.

Typo in subject: "initialization".


thanks
-- PMM

[Qemu-devel] [PATCH arm-devs v2 8/8] arm/highbank.c: Fix MPCore periphbase name

[Peter Crosthwaite]

GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore. Rename to
MPCORE_PERIPHBASE accordingly.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 hw/arm/highbank.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index cb32325..be2cc20 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -28,11 +28,11 @@
 #include "exec/address-spaces.h"
 #include "qemu/error-report.h"
 
-#define SMP_BOOT_ADDR 0x100
-#define SMP_BOOT_REG  0x40
-#define GIC_BASE_ADDR 0xfff10000
+#define SMP_BOOT_ADDR           0x100
+#define SMP_BOOT_REG            0x40
+#define MPCORE_PERIPHBASE       0xfff10000
 
-#define NIRQ_GIC      160
+#define NIRQ_GIC                160
 
 /* Board init.  */
 
@@ -55,7 +55,7 @@ static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
         0xe1110001, /* tst     r1, r1 */
         0x0afffffb, /* beq     <wfi> */
         0xe12fff11, /* bx      r1 */
-        GIC_BASE_ADDR      /* privbase: gic address.  */
+        MPCORE_PERIPHBASE   /* privbase: gic address.  */
     };
     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
         smpboot[n] = tswap32(smpboot[n]);
@@ -236,7 +236,8 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
 
         cpu = ARM_CPU(object_new(object_class_get_name(oc)));
 
-        object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar", &err);
+        object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
+                                &err);
         if (err) {
             error_report("%s", error_get_pretty(err));
             exit(1);
@@ -287,7 +288,7 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
     qdev_init_nofail(dev);
     busdev = SYS_BUS_DEVICE(dev);
-    sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
+    sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
     for (n = 0; n < smp_cpus; n++) {
         sysbus_connect_irq(busdev, n, cpu_irq[n]);
     }
-- 
1.8.4.4

Re: [Qemu-devel] [PATCH arm-devs v2 8/8] arm/highbank.c: Fix MPCore periphbase name

[Peter Maydell]

On 28 November 2013 03:31, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
> code that this is the base address of the MPCore. Rename to
> MPCORE_PERIPHBASE accordingly.

"MPCore" is one of those terms I dislike because it
doesn't actually match up with the documentation's
terminology...

> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> ---
>
>  hw/arm/highbank.c | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
> index cb32325..be2cc20 100644
> --- a/hw/arm/highbank.c
> +++ b/hw/arm/highbank.c
> @@ -28,11 +28,11 @@
>  #include "exec/address-spaces.h"
>  #include "qemu/error-report.h"
>
> -#define SMP_BOOT_ADDR 0x100
> -#define SMP_BOOT_REG  0x40
> -#define GIC_BASE_ADDR 0xfff10000
> +#define SMP_BOOT_ADDR           0x100
> +#define SMP_BOOT_REG            0x40
> +#define MPCORE_PERIPHBASE       0xfff10000
>
> -#define NIRQ_GIC      160
> +#define NIRQ_GIC                160
>
>  /* Board init.  */
>
> @@ -55,7 +55,7 @@ static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
>          0xe1110001, /* tst     r1, r1 */
>          0x0afffffb, /* beq     <wfi> */
>          0xe12fff11, /* bx      r1 */
> -        GIC_BASE_ADDR      /* privbase: gic address.  */
> +        MPCORE_PERIPHBASE   /* privbase: gic address.  */

Comment no longer matches code.

More seriously, this secondary-boot code has a bunch
of hardcoded offsets for GIC registers which are
correct for the A9 but wrong for A15. Andre, did you
test Midway with an SMP boot config?

The generic hw/arm/boot code dealt with this problem
by feeding the boot code the GIC CPU interface base
address rather than the generic peripheral base address;
the offsets within the CPU i/f are the same for both
cores.

>      };
>      for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
>          smpboot[n] = tswap32(smpboot[n]);
> @@ -236,7 +236,8 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
>
>          cpu = ARM_CPU(object_new(object_class_get_name(oc)));
>
> -        object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar", &err);
> +        object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
> +                                &err);
>          if (err) {
>              error_report("%s", error_get_pretty(err));
>              exit(1);
> @@ -287,7 +288,7 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
>      qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
>      qdev_init_nofail(dev);
>      busdev = SYS_BUS_DEVICE(dev);
> -    sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
> +    sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
>      for (n = 0; n < smp_cpus; n++) {
>          sysbus_connect_irq(busdev, n, cpu_irq[n]);
>      }
> --
> 1.8.4.4
>

thanks
-- PMM

Re: [Qemu-devel] [PATCH arm-devs v2 8/8] arm/highbank.c: Fix MPCore periphbase name

[Peter Crosthwaite]

On Fri, Nov 29, 2013 at 5:41 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 28 November 2013 03:31, Peter Crosthwaite
> <peter.crosthwaite@xilinx.com> wrote:
>> GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
>> code that this is the base address of the MPCore. Rename to
>> MPCORE_PERIPHBASE accordingly.
>
> "MPCore" is one of those terms I dislike because it
> doesn't actually match up with the documentation's
> terminology...
>

What entity ultimately owns PERIPHBASE and whats its symbolic name? I
felt like PERIPHBASE on its own was wrong. GIC_BASE_ADDR seems very
wrong though. Open to suggestion.

>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> ---
>>
>>  hw/arm/highbank.c | 15 ++++++++-------
>>  1 file changed, 8 insertions(+), 7 deletions(-)
>>
>> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
>> index cb32325..be2cc20 100644
>> --- a/hw/arm/highbank.c
>> +++ b/hw/arm/highbank.c
>> @@ -28,11 +28,11 @@
>>  #include "exec/address-spaces.h"
>>  #include "qemu/error-report.h"
>>
>> -#define SMP_BOOT_ADDR 0x100
>> -#define SMP_BOOT_REG  0x40
>> -#define GIC_BASE_ADDR 0xfff10000
>> +#define SMP_BOOT_ADDR           0x100
>> +#define SMP_BOOT_REG            0x40
>> +#define MPCORE_PERIPHBASE       0xfff10000
>>
>> -#define NIRQ_GIC      160
>> +#define NIRQ_GIC                160
>>
>>  /* Board init.  */
>>
>> @@ -55,7 +55,7 @@ static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
>>          0xe1110001, /* tst     r1, r1 */
>>          0x0afffffb, /* beq     <wfi> */
>>          0xe12fff11, /* bx      r1 */
>> -        GIC_BASE_ADDR      /* privbase: gic address.  */
>> +        MPCORE_PERIPHBASE   /* privbase: gic address.  */
>
> Comment no longer matches code.
>

Will fix.

Regards,
Peter

> More seriously, this secondary-boot code has a bunch
> of hardcoded offsets for GIC registers which are
> correct for the A9 but wrong for A15. Andre, did you
> test Midway with an SMP boot config?
>
> The generic hw/arm/boot code dealt with this problem
> by feeding the boot code the GIC CPU interface base
> address rather than the generic peripheral base address;
> the offsets within the CPU i/f are the same for both
> cores.
>
>>      };
>>      for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
>>          smpboot[n] = tswap32(smpboot[n]);
>> @@ -236,7 +236,8 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
>>
>>          cpu = ARM_CPU(object_new(object_class_get_name(oc)));
>>
>> -        object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar", &err);
>> +        object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
>> +                                &err);
>>          if (err) {
>>              error_report("%s", error_get_pretty(err));
>>              exit(1);
>> @@ -287,7 +288,7 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
>>      qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
>>      qdev_init_nofail(dev);
>>      busdev = SYS_BUS_DEVICE(dev);
>> -    sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
>> +    sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
>>      for (n = 0; n < smp_cpus; n++) {
>>          sysbus_connect_irq(busdev, n, cpu_irq[n]);
>>      }
>> --
>> 1.8.4.4
>>
>
> thanks
> -- PMM
>

Re: [Qemu-devel] [PATCH arm-devs v2 8/8] arm/highbank.c: Fix MPCore periphbase name

[Peter Crosthwaite]

Hi Peter,

On Fri, Nov 29, 2013 at 10:09 AM, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> On Fri, Nov 29, 2013 at 5:41 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>> On 28 November 2013 03:31, Peter Crosthwaite
>> <peter.crosthwaite@xilinx.com> wrote:
>>> GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
>>> code that this is the base address of the MPCore. Rename to
>>> MPCORE_PERIPHBASE accordingly.
>>
>> "MPCore" is one of those terms I dislike because it
>> doesn't actually match up with the documentation's
>> terminology...
>>
>

Which documentation are you specifically referring too? "MPCore" seems
to very much be a part of ARM top level documentation with document
names such as:

"ARM Cortex-A15 MPCore Processor Technical Reference Manual"

Regards,
Peter

> What entity ultimately owns PERIPHBASE and whats its symbolic name? I
> felt like PERIPHBASE on its own was wrong. GIC_BASE_ADDR seems very
> wrong though. Open to suggestion.
>

Re: [Qemu-devel] [PATCH arm-devs v2 8/8] arm/highbank.c: Fix MPCore periphbase name

[Andre Przywara]

On 11/28/2013 08:41 PM, Peter Maydell wrote:

(CCing Rob)

> On 28 November 2013 03:31, Peter Crosthwaite
> <peter.crosthwaite@xilinx.com> wrote:
>> GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
>> code that this is the base address of the MPCore. Rename to
>> MPCORE_PERIPHBASE accordingly.
>
> "MPCore" is one of those terms I dislike because it
> doesn't actually match up with the documentation's
> terminology...
>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> ---
>>
>>   hw/arm/highbank.c | 15 ++++++++-------
>>   1 file changed, 8 insertions(+), 7 deletions(-)
>>
>> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
>> index cb32325..be2cc20 100644
>> --- a/hw/arm/highbank.c
>> +++ b/hw/arm/highbank.c
>> @@ -28,11 +28,11 @@
>>   #include "exec/address-spaces.h"
>>   #include "qemu/error-report.h"
>>
>> -#define SMP_BOOT_ADDR 0x100
>> -#define SMP_BOOT_REG  0x40
>> -#define GIC_BASE_ADDR 0xfff10000
>> +#define SMP_BOOT_ADDR           0x100
>> +#define SMP_BOOT_REG            0x40
>> +#define MPCORE_PERIPHBASE       0xfff10000
>>
>> -#define NIRQ_GIC      160
>> +#define NIRQ_GIC                160
>>
>>   /* Board init.  */
>>
>> @@ -55,7 +55,7 @@ static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
>>           0xe1110001, /* tst     r1, r1 */
>>           0x0afffffb, /* beq     <wfi> */
>>           0xe12fff11, /* bx      r1 */
>> -        GIC_BASE_ADDR      /* privbase: gic address.  */
>> +        MPCORE_PERIPHBASE   /* privbase: gic address.  */
>
> Comment no longer matches code.
>
> More seriously, this secondary-boot code has a bunch
> of hardcoded offsets for GIC registers which are
> correct for the A9 but wrong for A15. Andre, did you
> test Midway with an SMP boot config?

Obviously not ;-)
In the moment I cannot care about this, but it looks like we need 
different SMP stubs for Highbank and Midway.
Thanks for the hint,

Andre.

>
> The generic hw/arm/boot code dealt with this problem
> by feeding the boot code the GIC CPU interface base
> address rather than the generic peripheral base address;
> the offsets within the CPU i/f are the same for both
> cores.
>
>>       };
>>       for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
>>           smpboot[n] = tswap32(smpboot[n]);
>> @@ -236,7 +236,8 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
>>
>>           cpu = ARM_CPU(object_new(object_class_get_name(oc)));
>>
>> -        object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar", &err);
>> +        object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
>> +                                &err);
>>           if (err) {
>>               error_report("%s", error_get_pretty(err));
>>               exit(1);
>> @@ -287,7 +288,7 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
>>       qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
>>       qdev_init_nofail(dev);
>>       busdev = SYS_BUS_DEVICE(dev);
>> -    sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
>> +    sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
>>       for (n = 0; n < smp_cpus; n++) {
>>           sysbus_connect_irq(busdev, n, cpu_irq[n]);
>>       }
>> --
>> 1.8.4.4
>>
>
> thanks
> -- PMM
>