[Qemu-devel] [PATCH target-arm v5 00/10] Fix Support for ARM CBAR and reset-hivecs

[Qemu-devel] [PATCH target-arm v5 00/10] Fix Support for ARM CBAR and reset-hivecs

[Peter Crosthwaite]

Hi All,

This patch series adds support for two board configurable ARM CPU
properties - Configuration Base Address Register and the
hivecs-on-reset.

The CBAR is needed to fix Zynq and Highbank which both were broken for
linux boot. This series provides the fixes.

I have added these properties as qdev properties rather than object
properties to pick up the desired writable-until-realize semantic.

To test the semantics of these new qdev properties I hacked Highbank
to illegally set the property after realize:

diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index c75b425..905483d 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -236,13 +236,13 @@ static void calxeda_init(QEMUMachineInitArgs
*args, enum cxmachines machine)

         cpu = ARM_CPU(object_new(object_class_get_name(oc)));

-        object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
-                                &err);
+        object_property_set_bool(OBJECT(cpu), true, "realized", &err);
         if (err) {
             error_report("%s", error_get_pretty(err));
             exit(1);
         }
-        object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+        object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
+                                &err);
         if (err) {
             error_report("%s", error_get_pretty(err));
             exit(1);

Booting with this bug I now get:

$ qemu-system-arm -M highbank ...
qemu-system-arm: Attempt to set property 'reset-cbar' on anonymous device (type 'cortex-a9-arm-cpu') after it was realized

whereas the previous versions would have silent failed.

Regards,
Peter

changed since v4:
Reimplemented using qdev properties
dropped QOM patches
rebased against mainline
changed since v3:
Rebased against target-arm patch queue (2013/12/11)
Added Antonys reset hivecs patches
changed since v2:
Fixed comment in p8 (PMM review)
Enabled CBAR for a15 (PMM review)
Typo sweep
Changed since v1:
Fix QOM to support writeable dynamic properties
Use dynamic props instead (PMM/AF discussion)
Use error_report (AF reivew)
Use reset- prefix on propname (AF review)
Fix machine model namings or the MPCore PERIPHBASE


Antony Pavlov (2):
  ARM: cpu: add "reset_hivecs" property
  ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc

Peter Crosthwaite (8):
  target-arm/helper.c: Allow cp15.c15 dummy override
  target-arm: Define and use ARM_FEATURE_CBAR
  target-arm/cpu: Convert reset CBAR to a property
  arm/highbank: Use object_new() rather than cpu_arm_init()
  arm/highbank: Fix CBAR initialisation
  arm/xilinx_zynq: Use object_new() rather than cpu_arm_init()
  arm/xilinx_zynq: Implement CBAR initialisation
  arm/highbank.c: Fix MPCore periphbase name

 hw/arm/highbank.c    | 33 +++++++++++++++++++++------------
 hw/arm/xilinx_zynq.c | 21 +++++++++++++++++----
 target-arm/cpu-qom.h |  1 +
 target-arm/cpu.c     | 47 ++++++++++++++++++++++++++++++++++++++---------
 target-arm/cpu.h     |  1 +
 target-arm/helper.c  | 12 +++++++++++-
 6 files changed, 89 insertions(+), 26 deletions(-)

-- 
1.8.5.1

[Qemu-devel] [PATCH target-arm v5 01/10] target-arm/helper.c: Allow cp15.c15 dummy override

[Peter Crosthwaite]

The cp15.c15 space is implementation defined. Currently there is a
dummy placeholder register RAZing it. Allow overriding of this RAZ
so implementations of specific registers can take precedence.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---

 target-arm/helper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5e5e5aa..71d6be3 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1338,7 +1338,8 @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
      */
     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
-      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
+      .access = PL1_RW,
+      .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
       .resetvalue = 0 },
     REGINFO_SENTINEL
 };
-- 
1.8.5.1

[Qemu-devel] [PATCH target-arm v5 02/10] target-arm: Define and use ARM_FEATURE_CBAR

[Peter Crosthwaite]

Some processors (notably A9 within Highbank) define and use the
CP15 configuration base address (CBAR). This is vendor specific
so its best implemented as a CPU property (otherwise we would need
vendor specific child classes for every ARM implementation).

This patch prepares support for converting CBAR reset value to
a CPU property by moving the CP registration out of the CPU
init fn, as registration will need to happen at realize time
to pick up any property updates. The easiest way to do this
is via definition of a new ARM_FEATURE to flag the existence
of the register.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
changed since v3:
Move new feature to end of list
changed since v2:
msg typo: existence
Enable CBAR for a15 as well

 target-arm/cpu.c    | 12 +++---------
 target-arm/cpu.h    |  1 +
 target-arm/helper.c |  9 +++++++++
 3 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 0635e78..4725892 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -616,6 +616,7 @@ static void cortex_a9_initfn(Object *obj)
      * and valid configurations; we don't model A9UP).
      */
     set_feature(&cpu->env, ARM_FEATURE_V7MP);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR);
     cpu->midr = 0x410fc090;
     cpu->reset_fpsid = 0x41033090;
     cpu->mvfr0 = 0x11110222;
@@ -638,15 +639,7 @@ static void cortex_a9_initfn(Object *obj)
     cpu->clidr = (1 << 27) | (1 << 24) | 3;
     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
-    {
-        ARMCPRegInfo cbar = {
-            .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,
-            .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
-            .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
-        };
-        define_one_arm_cp_reg(cpu, &cbar);
-        define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
-    }
+    define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 }
 
 #ifndef CONFIG_USER_ONLY
@@ -685,6 +678,7 @@ static void cortex_a15_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR);
     set_feature(&cpu->env, ARM_FEATURE_LPAE);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
     cpu->midr = 0x412fc0f1;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c3f007f..947a1e7 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -467,6 +467,7 @@ enum arm_features {
     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
     ARM_FEATURE_V8,
     ARM_FEATURE_AARCH64, /* supports 64 bit mode */
+    ARM_FEATURE_CBAR, /* has cp15 CBAR */
 };
 
 static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 71d6be3..cfbb14c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1745,6 +1745,15 @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_one_arm_cp_reg(cpu, &auxcr);
     }
 
+    if (arm_feature(env, ARM_FEATURE_CBAR)) {
+        ARMCPRegInfo cbar = {
+            .name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
+            .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
+            .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
+        };
+        define_one_arm_cp_reg(cpu, &cbar);
+    }
+
     /* Generic registers whose values depend on the implementation */
     {
         ARMCPRegInfo sctlr = {
-- 
1.8.5.1

[Qemu-devel] [PATCH target-arm v5 03/10] target-arm/cpu: Convert reset CBAR to a property

[Peter Crosthwaite]

The reset value of the CP15 CBAR is a vendor (machine) configurable
property. If ARM_FEATURE_CBAR is set, add it as a property at
post_init time.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
Changed since v4:
Re-implemented as qdev property.
Removed PMM reviewed-by (major implementation changes)
Changed since v3:
typo s/Value/value (PMM review)
Change since v1:
Re-implement as dynamic property

 target-arm/cpu.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 4725892..eb9e6da 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -21,6 +21,7 @@
 #include "cpu.h"
 #include "qemu-common.h"
 #include "hw/qdev-properties.h"
+#include "qapi/qmp/qerror.h"
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #endif
@@ -231,6 +232,21 @@ static void arm_cpu_initfn(Object *obj)
     }
 }
 
+static Property arm_cpu_reset_cbar_property =
+            DEFINE_PROP_UINT32("reset-cbar", ARMCPU, reset_cbar, 0);
+
+static void arm_cpu_post_init(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    Error *err = NULL;
+
+    if (arm_feature(&cpu->env, ARM_FEATURE_CBAR)) {
+        qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
+                                 &err);
+        assert_no_error(err);
+    }
+}
+
 static void arm_cpu_finalizefn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -993,6 +1009,7 @@ static const TypeInfo arm_cpu_type_info = {
     .parent = TYPE_CPU,
     .instance_size = sizeof(ARMCPU),
     .instance_init = arm_cpu_initfn,
+    .instance_post_init = arm_cpu_post_init,
     .instance_finalize = arm_cpu_finalizefn,
     .abstract = true,
     .class_size = sizeof(ARMCPUClass),
-- 
1.8.5.1

[Qemu-devel] [PATCH target-arm v5 04/10] arm/highbank: Use object_new() rather than cpu_arm_init()

[Peter Crosthwaite]

To allow the machine model to set device properties before CPU
realization.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
changed since v1:
use error_report rather than fprintf(stderr

 hw/arm/highbank.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index fe98ef1..1d19d8f 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -26,6 +26,7 @@
 #include "hw/boards.h"
 #include "sysemu/blockdev.h"
 #include "exec/address-spaces.h"
+#include "qemu/error-report.h"
 
 #define SMP_BOOT_ADDR 0x100
 #define SMP_BOOT_REG  0x40
@@ -229,10 +230,15 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
     }
 
     for (n = 0; n < smp_cpus; n++) {
+        ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
         ARMCPU *cpu;
-        cpu = cpu_arm_init(cpu_model);
-        if (cpu == NULL) {
-            fprintf(stderr, "Unable to find CPU definition\n");
+        Error *err = NULL;
+
+        cpu = ARM_CPU(object_new(object_class_get_name(oc)));
+
+        object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+        if (err) {
+            error_report("%s", error_get_pretty(err));
             exit(1);
         }
 
-- 
1.8.5.1

[Qemu-devel] [PATCH target-arm v5 05/10] arm/highbank: Fix CBAR initialisation

[Peter Crosthwaite]

Fix the CBAR initialisation by using the newly defined static property.
CBAR is now set before realization, so the intended value is now
actually used.

So I have kind of tested this. I booted an ARM kernel on Highbank with
the stock Highbank DTB. It doesn't boot (and I will be doing something
wrong), but before this patch I got this:

------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at /workspaces/pcrost/public/linux2.git/arch/arm/mm/ioremap.c:301 __arm_ioremap_pfn_caller+0x180/0x198()
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W 3.13.0-rc1-next-20131126-dirty #2
[<c0015164>] (unwind_backtrace) from [<c00118c0>] (show_stack+0x10/0x14)
[<c00118c0>] (show_stack) from [<c02bd5fc>] (dump_stack+0x78/0x90)
[<c02bd5fc>] (dump_stack) from [<c001f110>] (warn_slowpath_common+0x68/0x84)
[<c001f110>] (warn_slowpath_common) from [<c001f1f4>] (warn_slowpath_null+0x1c/0x24)
[<c001f1f4>] (warn_slowpath_null) from [<c0017c6c>] (__arm_ioremap_pfn_caller+0x180/0x198)
[<c0017c6c>] (__arm_ioremap_pfn_caller) from [<c0017cd8>] (__arm_ioremap_caller+0x54/0x5c)
[<c0017cd8>] (__arm_ioremap_caller) from [<c0017d10>] (__arm_ioremap+0x18/0x1c)
[<c0017d10>] (__arm_ioremap) from [<c03913c0>] (highbank_init_irq+0x34/0x8c)
[<c03913c0>] (highbank_init_irq) from [<c038c228>] (init_IRQ+0x28/0x2c)
[<c038c228>] (init_IRQ) from [<c03899ec>] (start_kernel+0x234/0x398)
[<c03899ec>] (start_kernel) from [<00008074>] (0x8074)
---[ end trace 3406ff24bd97382f ]---

Which disappears with this patch.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
changed since v2:
Fix msg typos
changed since v1:
use error report rather than fprintf(stderr

 hw/arm/highbank.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 1d19d8f..cb32325 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -236,14 +236,16 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
 
         cpu = ARM_CPU(object_new(object_class_get_name(oc)));
 
+        object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar", &err);
+        if (err) {
+            error_report("%s", error_get_pretty(err));
+            exit(1);
+        }
         object_property_set_bool(OBJECT(cpu), true, "realized", &err);
         if (err) {
             error_report("%s", error_get_pretty(err));
             exit(1);
         }
-
-        /* This will become a QOM property eventually */
-        cpu->reset_cbar = GIC_BASE_ADDR;
         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
     }
 
-- 
1.8.5.1

[Qemu-devel] [PATCH target-arm v5 06/10] arm/xilinx_zynq: Use object_new() rather than cpu_arm_init()

[Peter Crosthwaite]

To allow the machine model to set device properties before CPU
realization.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
changed since v1:
use error report rather than fprintf(stderr

 hw/arm/xilinx_zynq.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 46924a0..1c954a3 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -25,6 +25,7 @@
 #include "sysemu/blockdev.h"
 #include "hw/loader.h"
 #include "hw/ssi.h"
+#include "qemu/error-report.h"
 
 #define NUM_SPI_FLASHES 4
 #define NUM_QSPI_FLASHES 2
@@ -102,6 +103,7 @@ static void zynq_init(QEMUMachineInitArgs *args)
     const char *kernel_filename = args->kernel_filename;
     const char *kernel_cmdline = args->kernel_cmdline;
     const char *initrd_filename = args->initrd_filename;
+    ObjectClass *cpu_oc;
     ARMCPU *cpu;
     MemoryRegion *address_space_mem = get_system_memory();
     MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
@@ -110,15 +112,19 @@ static void zynq_init(QEMUMachineInitArgs *args)
     SysBusDevice *busdev;
     qemu_irq pic[64];
     NICInfo *nd;
+    Error *err = NULL;
     int n;
 
     if (!cpu_model) {
         cpu_model = "cortex-a9";
     }
+    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 
-    cpu = cpu_arm_init(cpu_model);
-    if (!cpu) {
-        fprintf(stderr, "Unable to find CPU definition\n");
+    cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
+
+    object_property_set_bool(OBJECT(cpu), true, "realized", &err);
+    if (err) {
+        error_report("%s", error_get_pretty(err));
         exit(1);
     }
 
-- 
1.8.5.1

[Qemu-devel] [PATCH target-arm v5 07/10] arm/xilinx_zynq: Implement CBAR initialisation

[Peter Crosthwaite]

Fix the CBAR initialisation by using the newly defined static property.
Zynq will now correctly init the CBAR to the SCU base address.

Needed to boot Linux on the xilinx_zynq machine model.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
changed since v1:
use error report rather than fprintf(stderr
rename SCU_BASE_ADDR to MPCORE_PERIPHBASE

 hw/arm/xilinx_zynq.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 1c954a3..17251c7 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -36,6 +36,8 @@
 
 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
 
+#define MPCORE_PERIPHBASE 0xF8F00000
+
 static const int dma_irqs[8] = {
     46, 47, 48, 49, 72, 73, 74, 75
 };
@@ -122,6 +124,11 @@ static void zynq_init(QEMUMachineInitArgs *args)
 
     cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
 
+    object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", &err);
+    if (err) {
+        error_report("%s", error_get_pretty(err));
+        exit(1);
+    }
     object_property_set_bool(OBJECT(cpu), true, "realized", &err);
     if (err) {
         error_report("%s", error_get_pretty(err));
@@ -160,7 +167,7 @@ static void zynq_init(QEMUMachineInitArgs *args)
     qdev_prop_set_uint32(dev, "num-cpu", 1);
     qdev_init_nofail(dev);
     busdev = SYS_BUS_DEVICE(dev);
-    sysbus_mmio_map(busdev, 0, 0xF8F00000);
+    sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
     sysbus_connect_irq(busdev, 0,
                        qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
 
-- 
1.8.5.1

[Qemu-devel] [PATCH target-arm v5 08/10] arm/highbank.c: Fix MPCore periphbase name

[Peter Crosthwaite]

GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore. Rename to
MPCORE_PERIPHBASE accordingly.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
changed since v2: Fixed broken comment (PMM review)

 hw/arm/highbank.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index cb32325..c75b425 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -28,11 +28,11 @@
 #include "exec/address-spaces.h"
 #include "qemu/error-report.h"
 
-#define SMP_BOOT_ADDR 0x100
-#define SMP_BOOT_REG  0x40
-#define GIC_BASE_ADDR 0xfff10000
+#define SMP_BOOT_ADDR           0x100
+#define SMP_BOOT_REG            0x40
+#define MPCORE_PERIPHBASE       0xfff10000
 
-#define NIRQ_GIC      160
+#define NIRQ_GIC                160
 
 /* Board init.  */
 
@@ -55,7 +55,7 @@ static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
         0xe1110001, /* tst     r1, r1 */
         0x0afffffb, /* beq     <wfi> */
         0xe12fff11, /* bx      r1 */
-        GIC_BASE_ADDR      /* privbase: gic address.  */
+        MPCORE_PERIPHBASE   /* privbase: MPCore peripheral base address.  */
     };
     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
         smpboot[n] = tswap32(smpboot[n]);
@@ -236,7 +236,8 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
 
         cpu = ARM_CPU(object_new(object_class_get_name(oc)));
 
-        object_property_set_int(OBJECT(cpu), GIC_BASE_ADDR, "reset-cbar", &err);
+        object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
+                                &err);
         if (err) {
             error_report("%s", error_get_pretty(err));
             exit(1);
@@ -287,7 +288,7 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
     qdev_init_nofail(dev);
     busdev = SYS_BUS_DEVICE(dev);
-    sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
+    sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
     for (n = 0; n < smp_cpus; n++) {
         sysbus_connect_irq(busdev, n, cpu_irq[n]);
     }
-- 
1.8.5.1

[Qemu-devel] [PATCH target-arm v5 09/10] ARM: cpu: add "reset_hivecs" property

[Peter Crosthwaite]

From: Antony Pavlov <antonynpavlov@gmail.com>

Add an ARM CPU property for the reset value of hivecs as it is a
board/SoC configurable setting.

The existence of the property is conditional on the ARM CPU not being M
class.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
[ PC Changes:
 * Elaborated commit message
 * refactored to use qdev_property_add_static
]
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
changed since v4:
Re-implemented using qdev_property_add_static

 target-arm/cpu-qom.h |  1 +
 target-arm/cpu.c     | 13 +++++++++++++
 2 files changed, 14 insertions(+)

diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index f32178a..afbd422 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -139,6 +139,7 @@ typedef struct ARMCPU {
     uint32_t ccsidr[16];
     uint32_t reset_cbar;
     uint32_t reset_auxcr;
+    bool reset_hivecs;
 } ARMCPU;
 
 #define TYPE_AARCH64_CPU "aarch64-cpu"
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index eb9e6da..9c96a9e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -235,6 +235,9 @@ static void arm_cpu_initfn(Object *obj)
 static Property arm_cpu_reset_cbar_property =
             DEFINE_PROP_UINT32("reset-cbar", ARMCPU, reset_cbar, 0);
 
+static Property arm_cpu_reset_hivecs_property =
+            DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
+
 static void arm_cpu_post_init(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -245,6 +248,12 @@ static void arm_cpu_post_init(Object *obj)
                                  &err);
         assert_no_error(err);
     }
+
+    if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
+        qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
+                                 &err);
+        assert_no_error(err);
+    }
 }
 
 static void arm_cpu_finalizefn(Object *obj)
@@ -306,6 +315,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         set_feature(env, ARM_FEATURE_PXN);
     }
 
+    if (cpu->reset_hivecs) {
+            cpu->reset_sctlr |= (1 << 13);
+    }
+
     register_cp_regs_for_features(cpu);
     arm_cpu_register_gdb_regs_for_features(cpu);
 
-- 
1.8.5.1

[Qemu-devel] [PATCH target-arm v5 10/10] ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc

[Peter Crosthwaite]

From: Antony Pavlov <antonynpavlov@gmail.com>

If hivecs are being used on reset, the CPU should come out of reset at
the hivecs reset vector (0xFFFF0000)

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
[ PC Changes:
 * Fixed Grammar error in commit message
 * Elaborated commit message.
]
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 target-arm/cpu.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 9c96a9e..4c61b0a 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -121,6 +121,11 @@ static void arm_cpu_reset(CPUState *s)
             env->regs[15] = pc & ~1;
         }
     }
+
+    if (env->cp15.c1_sys & (1 << 13)) {
+            env->regs[15] = 0xFFFF0000;
+    }
+
     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 #endif
     set_flush_to_zero(1, &env->vfp.standard_fp_status);
-- 
1.8.5.1

Re: [Qemu-devel] [PATCH target-arm v5 00/10] Fix Support for ARM CBAR and reset-hivecs

[Peter Maydell]

On 16 December 2013 02:28, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
> Hi All,
>
> This patch series adds support for two board configurable ARM CPU
> properties - Configuration Base Address Register and the
> hivecs-on-reset.
>
> The CBAR is needed to fix Zynq and Highbank which both were broken for
> linux boot. This series provides the fixes.
>
> I have added these properties as qdev properties rather than object
> properties to pick up the desired writable-until-realize semantic.

Looks good to me, thanks. Applied all to target-arm.next.

thanks
-- PMM