From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51834) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VsNvO-0007Gq-Bc for qemu-devel@nongnu.org; Sun, 15 Dec 2013 21:28:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VsNvH-0006nR-1x for qemu-devel@nongnu.org; Sun, 15 Dec 2013 21:28:50 -0500 Received: from mail-pa0-f41.google.com ([209.85.220.41]:51110) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VsNvG-0006nD-SZ for qemu-devel@nongnu.org; Sun, 15 Dec 2013 21:28:42 -0500 Received: by mail-pa0-f41.google.com with SMTP id lf10so2324373pab.28 for ; Sun, 15 Dec 2013 18:28:41 -0800 (PST) Sender: Peter Crosthwaite From: Peter Crosthwaite Date: Sun, 15 Dec 2013 18:28:09 -0800 Message-Id: Subject: [Qemu-devel] [PATCH target-arm v5 00/10] Fix Support for ARM CBAR and reset-hivecs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: peter.crosthwaite@xilinx.com, antonynpavlov@gmail.com, afaerber@suse.de, mark.langsdorf@calxeda.com, mst@redhat.com Hi All, This patch series adds support for two board configurable ARM CPU properties - Configuration Base Address Register and the hivecs-on-reset. The CBAR is needed to fix Zynq and Highbank which both were broken for linux boot. This series provides the fixes. I have added these properties as qdev properties rather than object properties to pick up the desired writable-until-realize semantic. To test the semantics of these new qdev properties I hacked Highbank to illegally set the property after realize: diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index c75b425..905483d 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -236,13 +236,13 @@ static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine) cpu = ARM_CPU(object_new(object_class_get_name(oc))); - object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", - &err); + object_property_set_bool(OBJECT(cpu), true, "realized", &err); if (err) { error_report("%s", error_get_pretty(err)); exit(1); } - object_property_set_bool(OBJECT(cpu), true, "realized", &err); + object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", + &err); if (err) { error_report("%s", error_get_pretty(err)); exit(1); Booting with this bug I now get: $ qemu-system-arm -M highbank ... qemu-system-arm: Attempt to set property 'reset-cbar' on anonymous device (type 'cortex-a9-arm-cpu') after it was realized whereas the previous versions would have silent failed. Regards, Peter changed since v4: Reimplemented using qdev properties dropped QOM patches rebased against mainline changed since v3: Rebased against target-arm patch queue (2013/12/11) Added Antonys reset hivecs patches changed since v2: Fixed comment in p8 (PMM review) Enabled CBAR for a15 (PMM review) Typo sweep Changed since v1: Fix QOM to support writeable dynamic properties Use dynamic props instead (PMM/AF discussion) Use error_report (AF reivew) Use reset- prefix on propname (AF review) Fix machine model namings or the MPCore PERIPHBASE Antony Pavlov (2): ARM: cpu: add "reset_hivecs" property ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc Peter Crosthwaite (8): target-arm/helper.c: Allow cp15.c15 dummy override target-arm: Define and use ARM_FEATURE_CBAR target-arm/cpu: Convert reset CBAR to a property arm/highbank: Use object_new() rather than cpu_arm_init() arm/highbank: Fix CBAR initialisation arm/xilinx_zynq: Use object_new() rather than cpu_arm_init() arm/xilinx_zynq: Implement CBAR initialisation arm/highbank.c: Fix MPCore periphbase name hw/arm/highbank.c | 33 +++++++++++++++++++++------------ hw/arm/xilinx_zynq.c | 21 +++++++++++++++++---- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 47 ++++++++++++++++++++++++++++++++++++++--------- target-arm/cpu.h | 1 + target-arm/helper.c | 12 +++++++++++- 6 files changed, 89 insertions(+), 26 deletions(-) -- 1.8.5.1