From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36251) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W3MXB-0003qH-N2 for qemu-devel@nongnu.org; Wed, 15 Jan 2014 04:13:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W3MX2-0004hH-CA for qemu-devel@nongnu.org; Wed, 15 Jan 2014 04:13:13 -0500 Received: from mail-qc0-f178.google.com ([209.85.216.178]:57249) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W3MX2-0004gx-8e for qemu-devel@nongnu.org; Wed, 15 Jan 2014 04:13:04 -0500 Received: by mail-qc0-f178.google.com with SMTP id m20so709889qcx.23 for ; Wed, 15 Jan 2014 01:13:04 -0800 (PST) Sender: Peter Crosthwaite From: Peter Crosthwaite Date: Wed, 15 Jan 2014 01:12:31 -0800 Message-Id: Subject: [Qemu-devel] [PATCH target-arm v5 0/5] Reset and Halting modifications + Zynq SMP List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com Hi All, The clock controller module in the Zynq platform has the ability to halt and reset arbitrary devices, including the CPU. We use this feature to implement SMP Linux - the kernel halts CPU1 then rewrites the vector table to the secondary entry point and the resets+unhalts. This series adds SMP support to the Zynq machine, and patches the Zynq SLCR (the clock controller) to have GPIOs connected to the CPUs. The GPIOs cause and ARM CPU reset. Only the reset side is implemented (which is good enough for SMP linux as it stands). Future work is to implement the halting behaviour as well. changed since v4 (PMM review): Convert to GPIO scheme Implemented custom secondary cpu reset OCM Macro cleanup changed since v3: Removed halting patches Reduced to minimal change needed for SMP Zynq Peter Crosthwaite (5): arm: zynq: Macroify OCM Base and Size arm: zynq: added SMP support zynq_slcr: Implement CPU reset arm: Implement reset GPIO. arm: zynq: Connect CPU resets to SLCR hw/arm/xilinx_zynq.c | 87 ++++++++++++++++++++++++++++++++++++++++------------ hw/misc/zynq_slcr.c | 16 ++++++++++ target-arm/cpu.c | 23 ++++++++++++++ target-arm/cpu.h | 8 +++-- 4 files changed, 112 insertions(+), 22 deletions(-) -- 1.8.5.3