* [Qemu-devel] [RFC/RFT v1 1/2] arm: tosa: QOMify NAND/display/irq controller
2014-02-12 1:12 [Qemu-devel] [RFC/RFT v1 0/2] NAND QOMification - Round 1 Peter Crosthwaite
@ 2014-02-12 1:13 ` Peter Crosthwaite
2014-02-12 1:13 ` [Qemu-devel] [RFC/RFT v1 2/2] cris: axis_dev88: QOMify NAND controller Peter Crosthwaite
1 sibling, 0 replies; 3+ messages in thread
From: Peter Crosthwaite @ 2014-02-12 1:13 UTC (permalink / raw)
To: afaerber, qemu-devel; +Cc: peter.maydell, edgari
First step QOMficiation of the tosa IO controller (NAND display and
interrupts. Setup the memory regions and IRQ properly as per sysbus.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
hw/arm/tosa.c | 12 ++++++++++--
hw/display/tc6393xb.c | 36 +++++++++++++++++++++++++++++-------
include/hw/devices.h | 2 --
3 files changed, 39 insertions(+), 11 deletions(-)
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index c00d8c2..941ab4d 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -227,8 +227,16 @@ static void tosa_init(QEMUMachineInitArgs *args)
memory_region_set_readonly(rom, true);
memory_region_add_subregion(address_space_mem, 0, rom);
- tmio = tc6393xb_init(address_space_mem, 0x10000000,
- qdev_get_gpio_in(mpu->gpio, TOSA_GPIO_TC6393XB_INT));
+ /*
+ * FIXME: remove this fishy cast when the board gets some
+ * more QOMification
+ */
+ tmio = (TC6393xbState *)object_new("TC6393xb");
+ sysbus_mmio_map(SYS_BUS_DEVICE(tmio), 0, 0x10000000);
+ sysbus_mmio_map(SYS_BUS_DEVICE(tmio), 1, 0x10100000);
+ sysbus_connect_irq(SYS_BUS_DEVICE(tmio), 0,
+ qdev_get_gpio_in(mpu->gpio, TOSA_GPIO_TC6393XB_INT));
+ object_property_set_bool(OBJECT(tmio), true, "realized", NULL);
scp0 = sysbus_create_simple("scoop", 0x08800000, NULL);
scp1 = sysbus_create_simple("scoop", 0x14800040, NULL);
diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c
index 3dd9b98..f78a9d0 100644
--- a/hw/display/tc6393xb.c
+++ b/hw/display/tc6393xb.c
@@ -12,6 +12,7 @@
*/
#include "hw/hw.h"
#include "hw/devices.h"
+#include "hw/sysbus.h"
#include "hw/block/flash.h"
#include "ui/console.h"
#include "ui/pixel_ops.h"
@@ -82,6 +83,10 @@
#define NAND_MODE_ECC_RST 0x60
struct TC6393xbState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
MemoryRegion iomem;
qemu_irq irq;
qemu_irq *sub_irqs;
@@ -134,6 +139,11 @@ struct TC6393xbState {
blanked : 1;
};
+#define TYPE_TC6393XB "TC6393xb"
+
+#define TC6393XB(obj) \
+ OBJECT_CHECK(TC6393xbState, (obj), TYPE_TC6393XB)
+
qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s)
{
return s->gpio_in;
@@ -552,9 +562,9 @@ static const GraphicHwOps tc6393xb_gfx_ops = {
.gfx_update = tc6393xb_update_display,
};
-TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
+static void tc6393xb_init(Object *obj)
{
- TC6393xbState *s;
+ TC6393xbState *s = TC6393XB(obj);
DriveInfo *nand;
static const MemoryRegionOps tc6393xb_ops = {
.read = tc6393xb_readb,
@@ -566,8 +576,7 @@ TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
},
};
- s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState));
- s->irq = irq;
+ sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1);
@@ -579,15 +588,28 @@ TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq)
s->flash = nand_init(nand ? nand->bdrv : NULL, NAND_MFR_TOSHIBA, 0x76);
memory_region_init_io(&s->iomem, NULL, &tc6393xb_ops, s, "tc6393xb", 0x10000);
- memory_region_add_subregion(sysmem, base, &s->iomem);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000);
vmstate_register_ram_global(&s->vram);
s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
- memory_region_add_subregion(sysmem, base + 0x100000, &s->vram);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->vram);
+
s->scr_width = 480;
s->scr_height = 640;
s->con = graphic_console_init(NULL, &tc6393xb_gfx_ops, s);
+}
- return s;
+static const TypeInfo tc6393xb_info = {
+ .name = TYPE_TC6393XB,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(TC6393xbState),
+ .instance_init = tc6393xb_init,
+};
+
+static void tc6393xb_register(void)
+{
+ type_register_static(&tc6393xb_info);
}
+
+type_init(tc6393xb_register)
diff --git a/include/hw/devices.h b/include/hw/devices.h
index c60bcab..d3c1108 100644
--- a/include/hw/devices.h
+++ b/include/hw/devices.h
@@ -55,8 +55,6 @@ void retu_key_event(void *retu, int state);
/* tc6393xb.c */
typedef struct TC6393xbState TC6393xbState;
#define TC6393XB_RAM 0x110000 /* amount of ram for Video and USB */
-TC6393xbState *tc6393xb_init(struct MemoryRegion *sysmem,
- uint32_t base, qemu_irq irq);
void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
qemu_irq handler);
qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s);
--
1.8.5.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* [Qemu-devel] [RFC/RFT v1 2/2] cris: axis_dev88: QOMify NAND controller
2014-02-12 1:12 [Qemu-devel] [RFC/RFT v1 0/2] NAND QOMification - Round 1 Peter Crosthwaite
2014-02-12 1:13 ` [Qemu-devel] [RFC/RFT v1 1/2] arm: tosa: QOMify NAND/display/irq controller Peter Crosthwaite
@ 2014-02-12 1:13 ` Peter Crosthwaite
1 sibling, 0 replies; 3+ messages in thread
From: Peter Crosthwaite @ 2014-02-12 1:13 UTC (permalink / raw)
To: afaerber, qemu-devel; +Cc: peter.maydell, edgari
First step QOMficiation of the Axis NAND controller. Setup the memory
regions properly as per sysbus.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
hw/cris/axis_dev88.c | 38 ++++++++++++++++++++++++++++++++++----
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c
index 645e45c..46d7c2a 100644
--- a/hw/cris/axis_dev88.c
+++ b/hw/cris/axis_dev88.c
@@ -39,6 +39,10 @@
struct nand_state_t
{
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public > */
+
DeviceState *nand;
MemoryRegion iomem;
unsigned int rdy:1;
@@ -47,6 +51,11 @@ struct nand_state_t
unsigned int ce:1;
};
+#define TYPE_AXIS_DEV88_NAND "axis-dev88-nand"
+
+#define AXIS_DEV88_NAND(obj) \
+ OBJECT_CHECK(struct nand_state_t, (obj), TYPE_AXIS_DEV88_NAND)
+
static struct nand_state_t nand_state;
static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
{
@@ -82,6 +91,21 @@ static const MemoryRegionOps nand_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static void axis_dev88_nand_init(Object *obj)
+{
+ struct nand_state_t *ns = AXIS_DEV88_NAND(obj);
+
+ memory_region_init_io(&ns->iomem, NULL, &nand_ops, ns, "nand", 0x05000000);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &ns->iomem);
+}
+
+static const TypeInfo axis_dev88_nand_info = {
+ .name = TYPE_AXIS_DEV88_NAND,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(struct nand_state_t),
+ .instance_init = axis_dev88_nand_init,
+};
+
struct tempsensor_t
{
unsigned int shiftreg;
@@ -238,6 +262,13 @@ static const MemoryRegionOps gpio_ops = {
},
};
+static void axis_dev88_register(void)
+{
+ type_register_static(&axis_dev88_nand_info);
+}
+
+type_init(axis_dev88_register)
+
#define INTMEM_SIZE (128 * 1024)
static struct cris_load_info li;
@@ -281,13 +312,12 @@ void axisdev88_init(QEMUMachineInitArgs *args)
memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
/* Attach a NAND flash to CS1. */
+ object_initialize(&nand_state, sizeof(nand_state), TYPE_AXIS_DEV88_NAND);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&nand_state), 0, 0x10000000);
nand = drive_get(IF_MTD, 0, 0);
nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
NAND_MFR_STMICRO, 0x39);
- memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
- "nand", 0x05000000);
- memory_region_add_subregion(address_space_mem, 0x10000000,
- &nand_state.iomem);
+ object_property_set_bool(OBJECT(&nand_state), true, "realized", NULL);
gpio_state.nand = &nand_state;
memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
--
1.8.5.4
^ permalink raw reply related [flat|nested] 3+ messages in thread