From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43826) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzFH7-00063e-QL for qemu-devel@nongnu.org; Mon, 23 Jun 2014 21:12:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WzFGy-0004iy-Ow for qemu-devel@nongnu.org; Mon, 23 Jun 2014 21:11:53 -0400 Received: from mail-yh0-x232.google.com ([2607:f8b0:4002:c01::232]:62454) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzFGy-0004io-Kl for qemu-devel@nongnu.org; Mon, 23 Jun 2014 21:11:44 -0400 Received: by mail-yh0-f50.google.com with SMTP id t59so5634817yho.23 for ; Mon, 23 Jun 2014 18:11:44 -0700 (PDT) Sender: Alistair Francis From: Alistair Francis Date: Tue, 24 Jun 2014 11:11:37 +1000 Message-Id: Subject: [Qemu-devel] [PATCH v1 0/7] target-arm: Extend PMCCNTR for ARMv8 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, alistair.francis@xilinx.com This patch series continues on from my original PMCCNTR patch work to extend the counter to be 64-bit and support for the PMCCFILTR_EL0 register which allows the counter to be disabled based on the current EL Alistair Francis (7): target-arm: Make the ARM PMCCNTR register 64-bit target-arm: Implement PMCCNTR_EL0 and related registers target-arm: Add helper macros and defines for CCNT register target-arm: Implement pmccntr_sync function target-arm: Remove old code and replace with new functions target-arm: Implement pmccfiltr_write function target-arm: Call the pmccntr_sync function when swapping ELs target-arm/cpu.h | 33 +++++++++++++- target-arm/helper-a64.c | 5 ++ target-arm/helper.c | 114 ++++++++++++++++++++++++++++++++++------------ target-arm/op_helper.c | 6 +++ 4 files changed, 127 insertions(+), 31 deletions(-)