From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49110) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X01oz-00089t-Ui for qemu-devel@nongnu.org; Thu, 26 Jun 2014 01:02:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X01oq-0006YO-VB for qemu-devel@nongnu.org; Thu, 26 Jun 2014 01:02:05 -0400 Received: from mail-ig0-x22f.google.com ([2607:f8b0:4001:c05::22f]:64240) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X01oq-0006YI-Qg for qemu-devel@nongnu.org; Thu, 26 Jun 2014 01:01:56 -0400 Received: by mail-ig0-f175.google.com with SMTP id h3so292390igd.8 for ; Wed, 25 Jun 2014 22:01:56 -0700 (PDT) Sender: Alistair Francis From: Alistair Francis Date: Thu, 26 Jun 2014 15:01:48 +1000 Message-Id: Subject: [Qemu-devel] [PATCH v2 0/7] target-arm: Extend PMCCNTR for ARMv8 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, cov@codeaurora.org, alistair.francis@xilinx.com This patch series continues on from my original PMCCNTR patch work to extend the counter to be 64-bit and support for the PMCCFILTR_EL0 register which allows the counter to be disabled based on the current EL V2: -Fix some typos identified by Christopher Covington -Convert the CCNT_ENABLED macro to the arm_ccnt_enabled function Alistair Francis (7): target-arm: Make the ARM PMCCNTR register 64-bit target-arm: Implement PMCCNTR_EL0 and related registers target-arm: Add arm_ccnt_enabled function target-arm: Implement pmccntr_sync function target-arm: Remove old code and replace with new functions target-arm: Implement pmccfiltr_write function target-arm: Call the pmccntr_sync function when swapping ELs target-arm/cpu.h | 14 ++++- target-arm/helper-a64.c | 5 ++ target-arm/helper.c | 150 ++++++++++++++++++++++++++++++++++++++--------- target-arm/op_helper.c | 6 ++ 4 files changed, 146 insertions(+), 29 deletions(-)