From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
To: qemu-devel@nongnu.org
Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org,
zach.pfeffer@xilinx.com, ozaki.ryota@gmail.com,
alistair.francis@xilinx.com, michals@xilinx.com
Subject: [Qemu-devel] [PATCH target-arm v1 00/15] Next Generation Xilinx Zynq SoC
Date: Mon, 23 Feb 2015 15:04:37 -0800 [thread overview]
Message-ID: <cover.1424731203.git.peter.crosthwaite@xilinx.com> (raw)
Hi Peter and all,
Xilinx's next gen SoC has been announced. This series adds a SoC and
machine model.
Series start with addition of ARM cortex A53 support (P1 and P2). The
Soc skeleton is then added with GIC, EMACs and UARTs are added. The
pre-existing models for GEM and UART are not SoC friendly (no visible
state struct), so those are refactored for SoC.
Create a generic machine model that exposes just the RAW SoC itself. The
only external device modelled is DDR RAM, as driven by the -m option.
The standard bootloader and PSCI support is used.
Regards,
Peter
Peter Crosthwaite (15):
target-arm: cpu64: Factor out ARM cortex init
target-arm: cpu64: Add support for cortex-a53
arm: Introduce Xilinx Zynq MPSoC
arm: xlnx-zynq-mp: Add GIC
arm: xlnx-zynq-mp: Connect CPU Timers to GIC
net: cadence_gem: Clean up variable names
net: cadence_gem: Split state struct and type into header
arm: xilinx-zynq-mp: Add GEM support
char: cadence_uart: Clean up variable names
char: cadence_uart: Split state struct and type into header
arm: xilinx-zynq-mp: Add UART support
arm: Add xilinx-zynq-mp-generic machine
arm: xilinx-zynq-mp-generic: Add external RAM
arm: xilinx-zynq-mp-generic: Add bootloading
arm: xlnx-zynq-mp: Add PSCI setup
default-configs/aarch64-softmmu.mak | 2 +-
hw/arm/Makefile.objs | 1 +
hw/arm/xlnx-zynq-mp-generic.c | 67 +++++++++++++++
hw/arm/xlnx-zynq-mp.c | 167 ++++++++++++++++++++++++++++++++++++
hw/char/cadence_uart.c | 113 ++++++++++--------------
hw/net/cadence_gem.c | 95 ++++++--------------
include/hw/arm/xlnx-zynq-mp.h | 29 +++++++
include/hw/char/cadence_uart.h | 35 ++++++++
include/hw/net/cadence_gem.h | 49 +++++++++++
target-arm/cpu64.c | 47 +++++++---
10 files changed, 456 insertions(+), 149 deletions(-)
create mode 100644 hw/arm/xlnx-zynq-mp-generic.c
create mode 100644 hw/arm/xlnx-zynq-mp.c
create mode 100644 include/hw/arm/xlnx-zynq-mp.h
create mode 100644 include/hw/char/cadence_uart.h
create mode 100644 include/hw/net/cadence_gem.h
--
2.3.0.1.g27a12f1
next reply other threads:[~2015-02-23 23:04 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-23 23:04 Peter Crosthwaite [this message]
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 01/15] target-arm: cpu64: Factor out ARM cortex init Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 02/15] target-arm: cpu64: Add support for cortex-a53 Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 03/15] arm: Introduce Xilinx Zynq MPSoC Peter Crosthwaite
2015-02-24 20:06 ` Michal Simek
2015-03-02 22:32 ` Peter Crosthwaite
2015-02-27 1:50 ` Alistair Francis
2015-03-02 20:08 ` Peter Crosthwaite
2015-03-02 22:31 ` Alistair Francis
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 04/15] arm: xlnx-zynq-mp: Add GIC Peter Crosthwaite
2015-02-27 1:59 ` Alistair Francis
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 05/15] arm: xlnx-zynq-mp: Connect CPU Timers to GIC Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 06/15] net: cadence_gem: Clean up variable names Peter Crosthwaite
2015-02-26 7:15 ` Alistair Francis
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 07/15] net: cadence_gem: Split state struct and type into header Peter Crosthwaite
2015-02-27 3:12 ` Alistair Francis
2015-03-02 22:24 ` Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 08/15] arm: xilinx-zynq-mp: Add GEM support Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 09/15] char: cadence_uart: Clean up variable names Peter Crosthwaite
2015-02-27 3:22 ` Alistair Francis
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 10/15] char: cadence_uart: Split state struct and type into header Peter Crosthwaite
2015-02-27 3:26 ` Alistair Francis
2015-03-02 22:27 ` Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 11/15] arm: xilinx-zynq-mp: Add UART support Peter Crosthwaite
2015-02-27 3:43 ` Alistair Francis
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 12/15] arm: Add xilinx-zynq-mp-generic machine Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 13/15] arm: xilinx-zynq-mp-generic: Add external RAM Peter Crosthwaite
2015-02-24 2:24 ` Alistair Francis
2015-03-02 19:40 ` Peter Crosthwaite
2015-03-02 22:38 ` Alistair Francis
2015-03-02 22:59 ` Peter Crosthwaite
2015-03-02 23:20 ` Alistair Francis
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 14/15] arm: xilinx-zynq-mp-generic: Add bootloading Peter Crosthwaite
2015-02-23 23:04 ` [Qemu-devel] [PATCH target-arm v1 15/15] arm: xlnx-zynq-mp: Add PSCI setup Peter Crosthwaite
2015-02-26 7:04 ` Alistair Francis
2015-03-02 19:56 ` Peter Crosthwaite
2015-02-27 3:38 ` [Qemu-devel] [PATCH target-arm v1 00/15] Next Generation Xilinx Zynq SoC Alistair Francis
2015-03-02 20:06 ` Peter Crosthwaite
2015-03-02 22:53 ` Alistair Francis
2015-03-02 23:05 ` Peter Crosthwaite
2015-03-02 23:22 ` Alistair Francis
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