From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33003) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YSbEv-0000BP-82 for qemu-devel@nongnu.org; Mon, 02 Mar 2015 20:03:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YSbEp-0005bT-9h for qemu-devel@nongnu.org; Mon, 02 Mar 2015 20:03:13 -0500 Received: from mail-by2on0088.outbound.protection.outlook.com ([207.46.100.88]:14528 helo=na01-by2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YSbEp-0005b8-06 for qemu-devel@nongnu.org; Mon, 02 Mar 2015 20:03:07 -0500 From: Peter Crosthwaite Date: Mon, 2 Mar 2015 16:28:49 -0800 Message-ID: MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH target-arm v2 00/15] Next Generation Xilinx Zynq SoC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, zach.pfeffer@xilinx.com, ozaki.ryota@gmail.com, alistair.francis@xilinx.com, michals@xilinx.com Hi Peter and all, Xilinx's next gen SoC has been announced. This series adds a SoC and board. Series start with addition of ARM cortex A53 support (P1 and P2). The Soc skeleton is then added with GIC, EMACs and UARTs are added. The pre-existing models for GEM and UART are not SoC friendly (no visible state struct), so those are refactored for SoC. Create a model of the EP108 board. Currently this doesn't have any EP108 specific features but is a usable board exposing the user visible features of the raw SoC. changed since v1: Addressed Alistair review (individual changes on resp. patches) Changed board name to EP108 Changed naming scheme to "zynqmp" / "ZYNQMP" (Michal review) Regards, Peter Peter Crosthwaite (15): target-arm: cpu64: Factor out ARM cortex init target-arm: cpu64: Add support for cortex-a53 arm: Introduce Xilinx ZynqMP SoC arm: xlnx-zynqmp: Add GIC arm: xlnx-zynqmp: Connect CPU Timers to GIC net: cadence_gem: Clean up variable names net: cadence_gem: Split state struct and type into header arm: xilinx-zynqmp: Add GEM support char: cadence_uart: Clean up variable names char: cadence_uart: Split state struct and type into header arm: xilinx-zynqmp: Add UART support arm: Add xlnx-ep108 machine arm: xilinx-ep108: Add external RAM arm: xilinx-ep108: Add bootloading arm: xlnx-zynqmp: Add PSCI setup default-configs/aarch64-softmmu.mak | 2 +- hw/arm/Makefile.objs | 1 + hw/arm/xlnx-ep108.c | 81 +++++++++++++++++ hw/arm/xlnx-zynqmp.c | 167 ++++++++++++++++++++++++++++++++++++ hw/char/cadence_uart.c | 113 ++++++++++-------------- hw/net/cadence_gem.c | 95 ++++++-------------- include/hw/arm/xlnx-zynqmp.h | 29 +++++++ include/hw/char/cadence_uart.h | 35 ++++++++ include/hw/net/cadence_gem.h | 49 +++++++++++ target-arm/cpu64.c | 47 +++++++--- 10 files changed, 470 insertions(+), 149 deletions(-) create mode 100644 hw/arm/xlnx-ep108.c create mode 100644 hw/arm/xlnx-zynqmp.c create mode 100644 include/hw/arm/xlnx-zynqmp.h create mode 100644 include/hw/char/cadence_uart.h create mode 100644 include/hw/net/cadence_gem.h -- 2.3.0.1.g27a12f1