From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39964) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yt5H5-000249-KR for qemu-devel@nongnu.org; Thu, 14 May 2015 22:22:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yt5H1-000669-Jc for qemu-devel@nongnu.org; Thu, 14 May 2015 22:22:55 -0400 Received: from mail-ob0-f171.google.com ([209.85.214.171]:36003) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yt5H1-000665-EY for qemu-devel@nongnu.org; Thu, 14 May 2015 22:22:51 -0400 Received: by obbkp3 with SMTP id kp3so67846217obb.3 for ; Thu, 14 May 2015 19:22:50 -0700 (PDT) Sender: Peter Crosthwaite From: Peter Crosthwaite Date: Thu, 14 May 2015 19:22:47 -0700 Message-Id: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH target-arm v9 00/14] Next Generation Xilinx Zynq SoC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, zach.pfeffer@xilinx.com, jues@xilinx.com, ozaki.ryota@gmail.com, alistair.francis@xilinx.com, michals@xilinx.com Hi Peter and all, Xilinx's next gen SoC has been announced. This series adds a SoC and board. Series start with addition of ARM cortex A53 support (P1 and P2). The Soc skeleton is then added with GIC, EMACs and UARTs added. The pre-existing models for GEM and UART are not SoC friendly (no visible state struct), so those are refactored for SoC. Create a model of the EP108 board. Currently this doesn't have any EP108 specific features but is a usable board exposing the user visible features of the raw SoC. See individual patches for detailed change logs. changed since v8 (Edgar review): Correct GIC nr of SPIs (=160) changed since v7 (PMM review): made GIC region sz defs board specific. changed since v6 (Edgar review): Added GIC region size macro Added GIC alises changed since v4: Addressed PMM and Alistair Reviews changed since v3: Included CPU thread kick fix Addressed Alistair review changed since v2: Fix CPU child prop adder Add DTS compat string changed since v1: Addressed Alistair review (individual changes on resp. patches) Changed board name to EP108 Changed naming scheme to "zynqmp" / "ZYNQMP" (Michal review) Regards, Peter Peter Crosthwaite (14): target-arm: cpu64: generalise name of A57 regs target-arm: cpu64: Add support for Cortex-A53 arm: Introduce Xilinx ZynqMP SoC arm: xlnx-zynqmp: Add GIC arm: xlnx-zynqmp: Connect CPU Timers to GIC net: cadence_gem: Clean up variable names net: cadence_gem: Split state struct and type into header arm: xlnx-zynqmp: Add GEM support char: cadence_uart: Clean up variable names char: cadence_uart: Split state struct and type into header arm: xlnx-zynqmp: Add UART support arm: Add xlnx-ep108 machine arm: xlnx-ep108: Add external RAM arm: xlnx-ep108: Add bootloading default-configs/aarch64-softmmu.mak | 2 +- hw/arm/Makefile.objs | 1 + hw/arm/xlnx-ep108.c | 82 ++++++++++++++ hw/arm/xlnx-zynqmp.c | 211 ++++++++++++++++++++++++++++++++++++ hw/char/cadence_uart.c | 115 ++++++++------------ hw/net/cadence_gem.c | 95 +++++----------- include/hw/arm/xlnx-zynqmp.h | 58 ++++++++++ include/hw/char/cadence_uart.h | 53 +++++++++ include/hw/net/cadence_gem.h | 73 +++++++++++++ target-arm/cpu64.c | 61 ++++++++++- 10 files changed, 609 insertions(+), 142 deletions(-) create mode 100644 hw/arm/xlnx-ep108.c create mode 100644 hw/arm/xlnx-zynqmp.c create mode 100644 include/hw/arm/xlnx-zynqmp.h create mode 100644 include/hw/char/cadence_uart.h create mode 100644 include/hw/net/cadence_gem.h -- 2.4.0.3.ge0ccc3b.dirty