From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37685) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU4Q-0002hB-AJ for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YzU4M-0008BC-8O for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:18 -0400 Received: from mail-ob0-f172.google.com ([209.85.214.172]:36147) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YzU4M-0008B2-3c for qemu-devel@nongnu.org; Mon, 01 Jun 2015 14:04:14 -0400 Received: by obbea2 with SMTP id ea2so109622361obb.3 for ; Mon, 01 Jun 2015 11:04:13 -0700 (PDT) Sender: Peter Crosthwaite From: Peter Crosthwaite Date: Mon, 1 Jun 2015 11:04:11 -0700 Message-Id: Subject: [Qemu-devel] [PATCH target-arm v1 0/9] ARM Cortex R5 Support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com, zach.pfeffer@xilinx.com, jues@xilinx.com Hi Peter and all, This patch series adds ARM Cortex R5 processor support. The PMSAv7 MPU is implemented. Two R5s are added to the Xilinx ZynqMP SoC. Regards, Peter Peter Crosthwaite (9): target-arm: Prepare support for Cortex-R5 arm: helper: Factor out CP regs common to [pv]msa target-arm/helper.c: define MPUIR register target-arm: Add registers for PMSAv7 arm: helper: rename get_phys_addr_mpu target-arm: Implement PMSAv7 MPU arm: r5: Implement dummy ATCM, BTCM and D-cache invalidate arm: xlnx-zynqmp: Preface CPU variables with "A" arm: xlnx-zynqmp: Add 2xCortexR5 CPUs hw/arm/xlnx-ep108.c | 2 +- hw/arm/xlnx-zynqmp.c | 50 +++++++--- include/hw/arm/xlnx-zynqmp.h | 6 +- target-arm/cpu.c | 39 ++++++++ target-arm/cpu.h | 9 ++ target-arm/helper.c | 226 +++++++++++++++++++++++++++++++++++++++---- 6 files changed, 299 insertions(+), 33 deletions(-) -- 2.4.2.3.g2ffcb72