From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48074) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3ULT-000775-MP for qemu-devel@nongnu.org; Fri, 12 Jun 2015 15:10:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z3ULO-0003A2-Mg for qemu-devel@nongnu.org; Fri, 12 Jun 2015 15:10:27 -0400 Received: from mail-qc0-f178.google.com ([209.85.216.178]:36359) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3ULO-00039w-Il for qemu-devel@nongnu.org; Fri, 12 Jun 2015 15:10:22 -0400 Received: by qcjl8 with SMTP id l8so13311581qcj.3 for ; Fri, 12 Jun 2015 12:10:22 -0700 (PDT) Sender: Peter Crosthwaite From: Peter Crosthwaite Date: Fri, 12 Jun 2015 12:10:20 -0700 Message-Id: Subject: [Qemu-devel] [PATCH target-arm v2 00/13] ARM Cortex R5 Support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com, zach.pfeffer@xilinx.com, jues@xilinx.com Hi Peter and all, This patch series adds ARM Cortex R5 processor support. The PMSAv7 MPU is implemented. Two R5s are added to the Xilinx ZynqMP SoC. Changed since v1: Addressed PMM and Alistair reviews (see indiv. patches) Adding prepatory refactorings to target-arm (new patches) - TLBTR VMSA conditional (1) - V7MP CP regs VMSA conditional (2) - Refactor get_phys_addr FSR return path (4) - Add MPUIR.U config (5) - Improved cpu configurability around MPUs (6-7) Regards, Peter Peter Crosthwaite (13): arm: Do not define TLBTR in PMSA systems arm: Don't add v7mp registers in MPU systems arm: helper: Factor out CP regs common to [pv]msa arm: Refactor get_phys_addr FSR return mechanism arm: Implement uniprocessor with MP config arm: Add has-mpu property target-arm/helper.c: define MPUIR register arm: helper: rename get_phys_addr_mpu target-arm: Add registers for PMSAv7 target-arm: Implement PMSAv7 MPU target-arm: Add support for Cortex-R5 arm: xlnx-zynqmp: Preface CPU variables with "apu" arm: xlnx-zynqmp: Add 2xCortexR5 CPUs hw/arm/xlnx-ep108.c | 2 +- hw/arm/xlnx-zynqmp.c | 53 ++++-- include/hw/arm/xlnx-zynqmp.h | 6 +- target-arm/cpu-qom.h | 8 + target-arm/cpu.c | 69 +++++++ target-arm/cpu.h | 11 ++ target-arm/helper.c | 439 +++++++++++++++++++++++++++++++++++-------- target-arm/internals.h | 3 +- target-arm/machine.c | 35 ++++ target-arm/op_helper.c | 11 +- 10 files changed, 533 insertions(+), 104 deletions(-) -- 2.4.3.3.g905f831