[Qemu-devel] [RFC PATCH v1 0/8] QOM prop overloading + ARM MPCore CPUs

[Qemu-devel] [RFC PATCH v1 0/8] QOM prop overloading + ARM MPCore CPUs

[Peter Crosthwaite]

Hi All,

This series introduced support for multi QOM properties with the same
name and then moves the ARM CPUs to the MPCore container objects (yes!
they are related!)

The application of the QOM change is container objects passing through
a single property on multiple same-type children as a single alias. The
immediate use case, is the ARM MPCore where we want to add N cpus but pass
through the CPU properties for all of them as an alias on the container
itself. The container property setter should fan out to all the CPUs in the
container.

Patches 1-5 implement overloaded properties as part of QOM. QOM
properties do not allow overloading by default, the creator of the
property has to switch it on.

Patch 6 switches this feature on for alias properties which handles the
container use case.

Patch 8 is the feature presentation, pulling the CPUs into the ARM
MPCore container. This is based on a series of Alistair's to do the same.
This version does the extra refactoring to handle the case of multiple CPUs
and the problems created around aliases.

Extra discussion points:

The QOM work will probably conflict with Pavel Fedin' work of arrayified
properties. So I'll resolve that conflict in a future spin.

Liviu recently brought up a desire for arguments to QOM constructors. P8
would probably be cleaner if this feature existed, as the number of CPUs
could be set as a constructor argument. There is no flexibility on when
this has to be set, it must be done immediately after construction so it
ideally should be part of construction.

My biggest fear is testing of the changes for the affected boards.
Peter, do you much coverage of these boards in your regressions? Do you
have automated tests in a git repo somewhere?

Regards,
Peter



Peter Crosthwaite (8):
  qom: Refactor array property code path
  qom: Add property overloading
  qom: Implement overloaded property setters
  qom: Delete all instances of an overloaded property
  qom: Disallow getting/resolving an overloaded property
  qom: Enable overloading of Alias properties
  arm: realview: Factor out CPU property setters
  arm: axxmpcore: Add CPUs to MPCore

 hw/arm/exynos4210.c         |  72 +++++++-----------------------
 hw/arm/highbank.c           |  65 +++++----------------------
 hw/arm/realview.c           | 100 +++++++++++++++++++++++------------------
 hw/arm/vexpress.c           |  71 +++++++-----------------------
 hw/arm/xilinx_zynq.c        |  65 ++++++++++-----------------
 hw/cpu/a15mpcore.c          |  66 ++++++++++++++++++++++++----
 hw/cpu/a9mpcore.c           |  97 +++++++++++++++++++++++++++++++++++++---
 hw/intc/exynos4210_gic.c    | 105 --------------------------------------------
 include/hw/arm/exynos4210.h |   2 -
 include/hw/cpu/a15mpcore.h  |   2 +
 include/hw/cpu/a9mpcore.h   |   6 +++
 include/qom/object.h        |   2 +
 qom/object.c                |  96 ++++++++++++++++++++++++----------------
 13 files changed, 341 insertions(+), 408 deletions(-)

-- 
2.4.3.3.g905f831

[Qemu-devel] [RFC PATCH v1 1/8] qom: Refactor array property code path

[Peter Crosthwaite]

To not be a trial and error based approach. Rather, explicitly scan the
existing property lists for the array format strings using a nested
strcmp loop.

This prepares support for multiple properties with the same name.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
 qom/object.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/qom/object.c b/qom/object.c
index 96abd34..2a65ab5 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -735,19 +735,22 @@ object_property_add(Object *obj, const char *name, const char *type,
         int i;
         ObjectProperty *ret;
         char *name_no_array = g_strdup(name);
+        char *full_name;
 
         name_no_array[name_len - 3] = '\0';
-        for (i = 0; ; ++i) {
-            char *full_name = g_strdup_printf("%s[%d]", name_no_array, i);
+        for (i = 0;; ++i) {
+            full_name = g_strdup_printf("%s[%d]", name_no_array, i);
 
-            ret = object_property_add(obj, full_name, type, get, set,
-                                      release, opaque, NULL);
-            g_free(full_name);
-            if (ret) {
+            if (!object_property_find(obj, full_name, NULL)) {
                 break;
             }
+            g_free(full_name);
         }
         g_free(name_no_array);
+
+        ret = object_property_add(obj, full_name, type, get, set,
+                                  release, opaque, &error_abort);
+        g_free(full_name);
         return ret;
     }
 
-- 
2.4.3.3.g905f831

[Qemu-devel] [RFC PATCH v1 2/8] qom: Add property overloading

[Peter Crosthwaite]

Add a mechanism to allow property name overloading. The property being
overloaded must explicitly allow it and the property types must match,
otherwise an error is returned as normal.

Once the property has been overloaded, set a flag indicating as such,
so operations that don't make sense for overloaded properties can raise
an error at their time of invocation.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
 include/qom/object.h |  2 ++
 qom/object.c         | 20 ++++++++++++--------
 2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/include/qom/object.h b/include/qom/object.h
index 0505f20..9fae8a4 100644
--- a/include/qom/object.h
+++ b/include/qom/object.h
@@ -343,6 +343,8 @@ typedef struct ObjectProperty
     ObjectPropertyAccessor *set;
     ObjectPropertyResolve *resolve;
     ObjectPropertyRelease *release;
+    bool allows_overloading;
+    bool overloaded;
     void *opaque;
 
     QTAILQ_ENTRY(ObjectProperty) node;
diff --git a/qom/object.c b/qom/object.c
index 2a65ab5..79172f7 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -728,7 +728,7 @@ object_property_add(Object *obj, const char *name, const char *type,
                     ObjectPropertyRelease *release,
                     void *opaque, Error **errp)
 {
-    ObjectProperty *prop;
+    ObjectProperty *first, *prop;
     size_t name_len = strlen(name);
 
     if (name_len >= 3 && !memcmp(name + name_len - 3, "[*]", 4)) {
@@ -754,13 +754,12 @@ object_property_add(Object *obj, const char *name, const char *type,
         return ret;
     }
 
-    QTAILQ_FOREACH(prop, &obj->properties, node) {
-        if (strcmp(prop->name, name) == 0) {
-            error_setg(errp, "attempt to add duplicate property '%s'"
-                       " to object (type '%s')", name,
-                       object_get_typename(obj));
-            return NULL;
-        }
+    first = object_property_find(obj, name, NULL);
+
+    if (first && (!first->allows_overloading || strcmp(type, first->type))) {
+        error_setg(errp, "attempt to add duplicate property '%s'"
+                   " to object (type '%s')", name, object_get_typename(obj));
+        return NULL;
     }
 
     prop = g_malloc0(sizeof(*prop));
@@ -773,6 +772,11 @@ object_property_add(Object *obj, const char *name, const char *type,
     prop->release = release;
     prop->opaque = opaque;
 
+    if (first) {
+        first->overloaded = true;
+        prop->overloaded = true;
+    }
+
     QTAILQ_INSERT_TAIL(&obj->properties, prop, node);
     return prop;
 }
-- 
2.4.3.3.g905f831

[Qemu-devel] [RFC PATCH v1 3/8] qom: Implement overloaded property setters

[Peter Crosthwaite]

Set the description/value of all matching properties for a given
name.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
 qom/object.c | 29 +++++++++++++++++++----------
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/qom/object.c b/qom/object.c
index 79172f7..46abf41 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -834,14 +834,24 @@ void object_property_set(Object *obj, Visitor *v, const char *name,
                          Error **errp)
 {
     ObjectProperty *prop = object_property_find(obj, name, errp);
+    Error *local_err = NULL;
+
     if (prop == NULL) {
         return;
     }
 
-    if (!prop->set) {
-        error_set(errp, QERR_PERMISSION_DENIED);
-    } else {
-        prop->set(obj, v, prop->opaque, name, errp);
+    QTAILQ_FOREACH(prop, &obj->properties, node) {
+        if (strcmp(prop->name, name) == 0) {
+            if (!prop->set) {
+                error_set(&local_err, QERR_PERMISSION_DENIED);
+            } else {
+                prop->set(obj, v, prop->opaque, name, &local_err);
+            }
+        }
+        if (local_err) {
+            error_propagate(errp, local_err);
+            return;
+        }
     }
 }
 
@@ -1797,13 +1807,12 @@ void object_property_set_description(Object *obj, const char *name,
 {
     ObjectProperty *op;
 
-    op = object_property_find(obj, name, errp);
-    if (!op) {
-        return;
+    QTAILQ_FOREACH(op, &obj->properties, node) {
+        if (strcmp(op->name, name) == 0) {
+            g_free(op->description);
+            op->description = g_strdup(description);
+        }
     }
-
-    g_free(op->description);
-    op->description = g_strdup(description);
 }
 
 static void object_instance_init(Object *obj)
-- 
2.4.3.3.g905f831

[Qemu-devel] [RFC PATCH v1 4/8] qom: Delete all instances of an overloaded property

[Peter Crosthwaite]

If a property name is overloaded all instances should be deleted by the
deleter.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
 qom/object.c | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/qom/object.c b/qom/object.c
index 46abf41..967ed0d 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -798,21 +798,23 @@ ObjectProperty *object_property_find(Object *obj, const char *name,
 
 void object_property_del(Object *obj, const char *name, Error **errp)
 {
-    ObjectProperty *prop = object_property_find(obj, name, errp);
-    if (prop == NULL) {
-        return;
-    }
+    for (;;) {
+        ObjectProperty *prop = object_property_find(obj, name, errp);
+        if (prop == NULL) {
+            return;
+        }
 
-    if (prop->release) {
-        prop->release(obj, name, prop->opaque);
-    }
+        if (prop->release) {
+            prop->release(obj, name, prop->opaque);
+        }
 
-    QTAILQ_REMOVE(&obj->properties, prop, node);
+        QTAILQ_REMOVE(&obj->properties, prop, node);
 
-    g_free(prop->name);
-    g_free(prop->type);
-    g_free(prop->description);
-    g_free(prop);
+        g_free(prop->name);
+        g_free(prop->type);
+        g_free(prop->description);
+        g_free(prop);
+    }
 }
 
 void object_property_get(Object *obj, Visitor *v, const char *name,
-- 
2.4.3.3.g905f831

[Qemu-devel] [RFC PATCH v1 5/8] qom: Disallow getting/resolving an overloaded property

[Peter Crosthwaite]

Using a getter or trying to resolve an overloaded property is
ambiguous. Disallow it.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
 qom/object.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/qom/object.c b/qom/object.c
index 967ed0d..1590df7 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -827,6 +827,9 @@ void object_property_get(Object *obj, Visitor *v, const char *name,
 
     if (!prop->get) {
         error_set(errp, QERR_PERMISSION_DENIED);
+    } else if (prop->overloaded) {
+        error_setg(errp, "Overloaded property '.%s' getter not supported\n",
+                   name);
     } else {
         prop->get(obj, v, prop->opaque, name, errp);
     }
@@ -1352,7 +1355,7 @@ gchar *object_get_canonical_path(Object *obj)
 Object *object_resolve_path_component(Object *parent, const gchar *part)
 {
     ObjectProperty *prop = object_property_find(parent, part, NULL);
-    if (prop == NULL) {
+    if (prop == NULL || prop->overloaded) {
         return NULL;
     }
 
-- 
2.4.3.3.g905f831

[Qemu-devel] [RFC PATCH v1 6/8] qom: Enable overloading of Alias properties

[Peter Crosthwaite]

So that container objects can implement multi-way setting aliases of
their contained objects.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
 qom/object.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/qom/object.c b/qom/object.c
index 1590df7..496bed8 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -1798,6 +1798,7 @@ void object_property_add_alias(Object *obj, const char *name,
         goto out;
     }
     op->resolve = property_resolve_alias;
+    op->allows_overloading = true;
 
     object_property_set_description(obj, op->name,
                                     target_prop->description,
-- 
2.4.3.3.g905f831

[Qemu-devel] [RFC PATCH v1 7/8] arm: realview: Factor out CPU property setters

[Peter Crosthwaite]

Into its own function. This prepares support for cpu-inclusive MPCores
which may need to have these props set for them as well.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
 hw/arm/realview.c | 46 +++++++++++++++++++++++++++-------------------
 1 file changed, 27 insertions(+), 19 deletions(-)

diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index ef2788d..251b328 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -45,6 +45,32 @@ static const int realview_board_id[] = {
     0x76d
 };
 
+static inline void realview_init_cpu_props(Object *obj, hwaddr reset_cbar,
+                                           bool do_reset_cbar)
+{
+        Error *err = NULL;
+
+        /* By default A9,A15 and ARM1176 CPUs have EL3 enabled.  This board
+         * does not currently support EL3 so the CPU EL3 property is disabled
+         * before realization.
+         */
+        if (object_property_find(obj, "has_el3", NULL)) {
+            object_property_set_bool(obj, false, "has_el3", &err);
+            if (err) {
+                error_report_err(err);
+                exit(1);
+            }
+        }
+
+        if (do_reset_cbar) {
+            object_property_set_int(obj, reset_cbar, "reset-cbar", &err);
+            if (err) {
+                error_report_err(err);
+                exit(1);
+            }
+        }
+}
+
 static void realview_init(MachineState *machine,
                           enum realview_board_type board_type)
 {
@@ -101,25 +127,7 @@ static void realview_init(MachineState *machine,
         Object *cpuobj = object_new(object_class_get_name(cpu_oc));
         Error *err = NULL;
 
-        /* By default A9,A15 and ARM1176 CPUs have EL3 enabled.  This board
-         * does not currently support EL3 so the CPU EL3 property is disabled
-         * before realization.
-         */
-        if (object_property_find(cpuobj, "has_el3", NULL)) {
-            object_property_set_bool(cpuobj, false, "has_el3", &err);
-            if (err) {
-                error_report_err(err);
-                exit(1);
-            }
-        }
-
-        if (is_pb && is_mpcore) {
-            object_property_set_int(cpuobj, periphbase, "reset-cbar", &err);
-            if (err) {
-                error_report_err(err);
-                exit(1);
-            }
-        }
+        realview_init_cpu_props(cpuobj, periphbase, is_pb && is_mpcore);
 
         object_property_set_bool(cpuobj, true, "realized", &err);
         if (err) {
-- 
2.4.3.3.g905f831

[Qemu-devel] [RFC PATCH v1 8/8] arm: axxmpcore: Add CPUs to MPCore

[Peter Crosthwaite]

Add the ARM a9/a15 Cortex CPUs to their respective MPCore containers.
Update all users or MPCore to not instantiate CPUs on the machine
level.

A9 MPCore needs to be extended with the external interrupt controller
capability (which ors a set of pins with the GIC CPU IRQs). This is
needed by Exynos, which uses the current MPCore/CPU split to manually
implement an extra interrupt controller.

Change both a15 and a9 at once to the interface consistent for the
Vexpress and Highbank boards.

This defeatures cpu_model override of some of the existing ARM boards.
This is ok, as this is invalid for all of these platforms. A board
including an A9 or A15 MPCore cannot validly have its CPU type
overridden.

Promote property setters of some of the CPU properties to &error abort.
With no CPU model flexibility, these shouldn't fail anymore for the way
they are used by the fixed machine models.

As part of the change, A9MPCore now supports the oring in of external
interrupt controller natively. This obsoletes the Exynos specific IRQ
gate logic.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
Sorry about the big patch. I can't see a way to split this without
having to rewrite/delete added code.

 hw/arm/exynos4210.c         |  72 +++++++-----------------------
 hw/arm/highbank.c           |  65 +++++----------------------
 hw/arm/realview.c           |  54 +++++++++++++----------
 hw/arm/vexpress.c           |  71 +++++++-----------------------
 hw/arm/xilinx_zynq.c        |  65 ++++++++++-----------------
 hw/cpu/a15mpcore.c          |  66 ++++++++++++++++++++++++----
 hw/cpu/a9mpcore.c           |  97 +++++++++++++++++++++++++++++++++++++---
 hw/intc/exynos4210_gic.c    | 105 --------------------------------------------
 include/hw/arm/exynos4210.h |   2 -
 include/hw/cpu/a15mpcore.h  |   2 +
 include/hw/cpu/a9mpcore.h   |   6 +++
 11 files changed, 253 insertions(+), 352 deletions(-)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index c55fab8..1c6e061 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -137,73 +137,34 @@ void exynos4210_write_secondary(ARMCPU *cpu,
 Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
         unsigned long ram_size)
 {
-    int i, n;
+    int n;
     Exynos4210State *s = g_new(Exynos4210State, 1);
-    qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
     unsigned long mem_size;
-    DeviceState *dev;
+    DeviceState *dev, *mpcore;
     SysBusDevice *busdev;
     ObjectClass *cpu_oc;
 
     cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
     assert(cpu_oc);
 
-    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
-        Object *cpuobj = object_new(object_class_get_name(cpu_oc));
-        Error *err = NULL;
-
-        /* By default A9 CPUs have EL3 enabled.  This board does not currently
-         * support EL3 so the CPU EL3 property is disabled before realization.
-         */
-        if (object_property_find(cpuobj, "has_el3", NULL)) {
-            object_property_set_bool(cpuobj, false, "has_el3", &err);
-            if (err) {
-                error_report_err(err);
-                exit(1);
-            }
-        }
-
-        s->cpu[n] = ARM_CPU(cpuobj);
-        object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
-                                "reset-cbar", &error_abort);
-        object_property_set_bool(cpuobj, true, "realized", &err);
-        if (err) {
-            error_report_err(err);
-            exit(1);
-        }
-    }
-
     /*** IRQs ***/
 
     s->irq_table = exynos4210_init_irq(&s->irqs);
 
-    /* IRQ Gate */
-    for (i = 0; i < EXYNOS4210_NCPUS; i++) {
-        dev = qdev_create(NULL, "exynos4210.irq_gate");
-        qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
-        qdev_init_nofail(dev);
-        /* Get IRQ Gate input in gate_irq */
-        for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
-            gate_irq[i][n] = qdev_get_gpio_in(dev, n);
-        }
-        busdev = SYS_BUS_DEVICE(dev);
-
-        /* Connect IRQ Gate output to CPU's IRQ line */
-        sysbus_connect_irq(busdev, 0,
-                           qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
-    }
-
-    /* Private memory region and Internal GIC */
-    dev = qdev_create(NULL, "a9mpcore_priv");
-    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
-    qdev_init_nofail(dev);
-    busdev = SYS_BUS_DEVICE(dev);
+    /* MPCore (Contains internal GIC) */
+    mpcore = qdev_create(NULL, "a9mpcore_priv");
+    qdev_prop_set_uint32(mpcore, "num-cpu", EXYNOS4210_NCPUS);
+    /* By default A9 CPUs have EL3 enabled.  This board does not currently
+     * support EL3 so the CPU EL3 property is disabled before realization.
+     */
+    object_property_set_bool(OBJECT(mpcore), false, "has_el3", &error_abort);
+    object_property_set_int(OBJECT(mpcore), EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
+                            "reset-cbar", &error_abort);
+    qdev_init_nofail(mpcore);
+    busdev = SYS_BUS_DEVICE(mpcore);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
-    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
-        sysbus_connect_irq(busdev, n, gate_irq[n][0]);
-    }
     for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
-        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
+        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(mpcore, n);
     }
 
     /* Cache controller */
@@ -216,10 +177,11 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
     busdev = SYS_BUS_DEVICE(dev);
     /* Map CPU interface */
     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
-    /* Map Distributer interface */
+    /* Map Distributor interface */
     sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
-        sysbus_connect_irq(busdev, n, gate_irq[n][1]);
+        sysbus_connect_irq(busdev, n,
+                           qdev_get_gpio_in_named(mpcore, "ext-interrupt", n));
     }
     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
         s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index f8353a7..32deadb 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -208,7 +208,6 @@ enum cxmachines {
 static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
 {
     ram_addr_t ram_size = machine->ram_size;
-    const char *cpu_model = machine->cpu_model;
     const char *kernel_filename = machine->kernel_filename;
     const char *kernel_cmdline = machine->kernel_cmdline;
     const char *initrd_filename = machine->initrd_filename;
@@ -216,61 +215,14 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
     SysBusDevice *busdev;
     qemu_irq pic[128];
     int n;
-    qemu_irq cpu_irq[4];
-    qemu_irq cpu_fiq[4];
     MemoryRegion *sysram;
     MemoryRegion *dram;
     MemoryRegion *sysmem;
     char *sysboot_filename;
 
-    if (!cpu_model) {
-        switch (machine_id) {
-        case CALXEDA_HIGHBANK:
-            cpu_model = "cortex-a9";
-            break;
-        case CALXEDA_MIDWAY:
-            cpu_model = "cortex-a15";
-            break;
-        }
-    }
-
-    for (n = 0; n < smp_cpus; n++) {
-        ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
-        Object *cpuobj;
-        ARMCPU *cpu;
-        Error *err = NULL;
-
-        if (!oc) {
-            error_report("Unable to find CPU definition");
-            exit(1);
-        }
-
-        cpuobj = object_new(object_class_get_name(oc));
-        cpu = ARM_CPU(cpuobj);
-
-        /* By default A9 and A15 CPUs have EL3 enabled.  This board does not
-         * currently support EL3 so the CPU EL3 property is disabled before
-         * realization.
-         */
-        if (object_property_find(cpuobj, "has_el3", NULL)) {
-            object_property_set_bool(cpuobj, false, "has_el3", &err);
-            if (err) {
-                error_report_err(err);
-                exit(1);
-            }
-        }
-
-        if (object_property_find(cpuobj, "reset-cbar", NULL)) {
-            object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
-                                    "reset-cbar", &error_abort);
-        }
-        object_property_set_bool(cpuobj, true, "realized", &err);
-        if (err) {
-            error_report_err(err);
-            exit(1);
-        }
-        cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
-        cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
+    if (machine->cpu_model) {
+        error_report("Highbank/Midway does not support CPU model override!\n");
+        exit(1);
     }
 
     sysmem = get_system_memory();
@@ -310,13 +262,16 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
     }
     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
+     /* By default A9 and A15 CPUs have EL3 enabled.  This board does not
+     * currently support EL3 so the CPU EL3 property is disabled before
+     * realization.
+     */
+    object_property_set_bool(OBJECT(dev), false, "has_el3", &error_abort);
+    object_property_set_int(OBJECT(dev), MPCORE_PERIPHBASE, "reset-cbar",
+                            &error_abort);
     qdev_init_nofail(dev);
     busdev = SYS_BUS_DEVICE(dev);
     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
-    for (n = 0; n < smp_cpus; n++) {
-        sysbus_connect_irq(busdev, n, cpu_irq[n]);
-        sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
-    }
 
     for (n = 0; n < 128; n++) {
         pic[n] = qdev_get_gpio_in(dev, n);
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 251b328..9684b58 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -93,6 +93,7 @@ static void realview_init(MachineState *machine,
     int done_nic = 0;
     qemu_irq cpu_irq[4];
     int is_mpcore = 0;
+    bool mpcore_cpus = false;
     int is_pb = 0;
     uint32_t proc_id = 0;
     uint32_t sys_id;
@@ -112,6 +113,7 @@ static void realview_init(MachineState *machine,
         break;
     case BOARD_PBX_A9:
         is_mpcore = 1;
+        mpcore_cpus = true;
         is_pb = 1;
         periphbase = 0x1f000000;
         break;
@@ -123,7 +125,7 @@ static void realview_init(MachineState *machine,
         exit(1);
     }
 
-    for (n = 0; n < smp_cpus; n++) {
+    for (n = 0; !mpcore_cpus && n < smp_cpus; n++) {
         Object *cpuobj = object_new(object_class_get_name(cpu_oc));
         Error *err = NULL;
 
@@ -137,21 +139,6 @@ static void realview_init(MachineState *machine,
 
         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
     }
-    cpu = ARM_CPU(first_cpu);
-    env = &cpu->env;
-    if (arm_feature(env, ARM_FEATURE_V7)) {
-        if (is_mpcore) {
-            proc_id = 0x0c000000;
-        } else {
-            proc_id = 0x0e000000;
-        }
-    } else if (arm_feature(env, ARM_FEATURE_V6K)) {
-        proc_id = 0x06000000;
-    } else if (arm_feature(env, ARM_FEATURE_V6)) {
-        proc_id = 0x04000000;
-    } else {
-        proc_id = 0x02000000;
-    }
 
     if (is_pb && ram_size > 0x20000000) {
         /* Core tile RAM.  */
@@ -181,20 +168,16 @@ static void realview_init(MachineState *machine,
         ram_size = low_ram_size;
     }
 
-    sys_id = is_pb ? 0x01780500 : 0xc1400400;
-    sysctl = qdev_create(NULL, "realview_sysctl");
-    qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
-    qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
-    qdev_init_nofail(sysctl);
-    sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
-
     if (is_mpcore) {
         dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
         qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
+        if (mpcore_cpus) {
+            realview_init_cpu_props(OBJECT(dev), periphbase, is_pb);
+        }
         qdev_init_nofail(dev);
         busdev = SYS_BUS_DEVICE(dev);
         sysbus_mmio_map(busdev, 0, periphbase);
-        for (n = 0; n < smp_cpus; n++) {
+        for (n = 0; !mpcore_cpus && n < smp_cpus; n++) {
             sysbus_connect_irq(busdev, n, cpu_irq[n]);
         }
         sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL);
@@ -209,6 +192,29 @@ static void realview_init(MachineState *machine,
         pic[n] = qdev_get_gpio_in(dev, n);
     }
 
+    cpu = ARM_CPU(first_cpu);
+    env = &cpu->env;
+    if (arm_feature(env, ARM_FEATURE_V7)) {
+        if (is_mpcore) {
+            proc_id = 0x0c000000;
+        } else {
+            proc_id = 0x0e000000;
+        }
+    } else if (arm_feature(env, ARM_FEATURE_V6K)) {
+        proc_id = 0x06000000;
+    } else if (arm_feature(env, ARM_FEATURE_V6)) {
+        proc_id = 0x04000000;
+    } else {
+        proc_id = 0x02000000;
+    }
+
+    sys_id = is_pb ? 0x01780500 : 0xc1400400;
+    sysctl = qdev_create(NULL, "realview_sysctl");
+    qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
+    qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
+    qdev_init_nofail(sysctl);
+    sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
+
     pl041 = qdev_create(NULL, "pl041");
     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
     qdev_init_nofail(pl041);
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index da21788..784203f 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -179,7 +179,6 @@ typedef struct {
 
 typedef void DBoardInitFn(const VexpressMachineState *machine,
                           ram_addr_t ram_size,
-                          const char *cpu_model,
                           qemu_irq *pic);
 
 struct VEDBoardInfo {
@@ -195,45 +194,23 @@ struct VEDBoardInfo {
     DBoardInitFn *init;
 };
 
-static void init_cpus(const char *cpu_model, const char *privdev,
+static void init_cpus(const char *privdev,
                       hwaddr periphbase, qemu_irq *pic, bool secure)
 {
-    ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
     DeviceState *dev;
     SysBusDevice *busdev;
     int n;
 
-    if (!cpu_oc) {
-        fprintf(stderr, "Unable to find CPU definition\n");
-        exit(1);
-    }
-
-    /* Create the actual CPUs */
-    for (n = 0; n < smp_cpus; n++) {
-        Object *cpuobj = object_new(object_class_get_name(cpu_oc));
-        Error *err = NULL;
-
-        if (!secure) {
-            object_property_set_bool(cpuobj, false, "has_el3", NULL);
-        }
-
-        if (object_property_find(cpuobj, "reset-cbar", NULL)) {
-            object_property_set_int(cpuobj, periphbase,
-                                    "reset-cbar", &error_abort);
-        }
-        object_property_set_bool(cpuobj, true, "realized", &err);
-        if (err) {
-            error_report_err(err);
-            exit(1);
-        }
-    }
-
-    /* Create the private peripheral devices (including the GIC);
-     * this must happen after the CPUs are created because a15mpcore_priv
-     * wires itself up to the CPU's generic_timer gpio out lines.
-     */
+    /* Create the relevant CPU MPCore */
     dev = qdev_create(NULL, privdev);
     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
+    if (!secure) {
+        object_property_set_bool(OBJECT(dev), false, "has_el3", NULL);
+    }
+    if (object_property_find(OBJECT(dev), "reset-cbar", NULL)) {
+        object_property_set_int(OBJECT(dev), periphbase, "reset-cbar",
+                                &error_abort);
+    }
     qdev_init_nofail(dev);
     busdev = SYS_BUS_DEVICE(dev);
     sysbus_mmio_map(busdev, 0, periphbase);
@@ -247,20 +224,10 @@ static void init_cpus(const char *cpu_model, const char *privdev,
     for (n = 0; n < 64; n++) {
         pic[n] = qdev_get_gpio_in(dev, n);
     }
-
-    /* Connect the CPUs to the GIC */
-    for (n = 0; n < smp_cpus; n++) {
-        DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
-
-        sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
-        sysbus_connect_irq(busdev, n + smp_cpus,
-                           qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
-    }
 }
 
 static void a9_daughterboard_init(const VexpressMachineState *vms,
                                   ram_addr_t ram_size,
-                                  const char *cpu_model,
                                   qemu_irq *pic)
 {
     MemoryRegion *sysmem = get_system_memory();
@@ -268,10 +235,6 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
     MemoryRegion *lowram = g_new(MemoryRegion, 1);
     ram_addr_t low_ram_size;
 
-    if (!cpu_model) {
-        cpu_model = "cortex-a9";
-    }
-
     if (ram_size > 0x40000000) {
         /* 1GB is the maximum the address space permits */
         fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
@@ -293,7 +256,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,
     memory_region_add_subregion(sysmem, 0x60000000, ram);
 
     /* 0x1e000000 A9MPCore (SCU) private memory region */
-    init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic, vms->secure);
+    init_cpus("a9mpcore_priv", 0x1e000000, pic, vms->secure);
 
     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 
@@ -349,17 +312,12 @@ static VEDBoardInfo a9_daughterboard = {
 
 static void a15_daughterboard_init(const VexpressMachineState *vms,
                                    ram_addr_t ram_size,
-                                   const char *cpu_model,
                                    qemu_irq *pic)
 {
     MemoryRegion *sysmem = get_system_memory();
     MemoryRegion *ram = g_new(MemoryRegion, 1);
     MemoryRegion *sram = g_new(MemoryRegion, 1);
 
-    if (!cpu_model) {
-        cpu_model = "cortex-a15";
-    }
-
     {
         /* We have to use a separate 64 bit variable here to avoid the gcc
          * "comparison is always false due to limited range of data type"
@@ -378,7 +336,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,
     memory_region_add_subregion(sysmem, 0x80000000, ram);
 
     /* 0x2c000000 A15MPCore private memory region (GIC) */
-    init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic, vms->secure);
+    init_cpus("a15mpcore_priv", 0x2c000000, pic, vms->secure);
 
     /* A15 daughterboard peripherals: */
 
@@ -556,7 +514,12 @@ static void vexpress_common_init(MachineState *machine)
     const hwaddr *map = daughterboard->motherboard_map;
     int i;
 
-    daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic);
+    if (machine->cpu_model) {
+        error_report("Vexpress does not support CPU model override!\n");
+        exit(1);
+    }
+
+    daughterboard->init(vms, machine->ram_size, pic);
 
     /*
      * If a bios file was provided, attempt to map it into memory
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index a4e7b5c..037cd21 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -26,6 +26,7 @@
 #include "hw/loader.h"
 #include "hw/ssi.h"
 #include "qemu/error-report.h"
+#include "hw/cpu/a9mpcore.h"
 
 #define NUM_SPI_FLASHES 4
 #define NUM_QSPI_FLASHES 2
@@ -104,12 +105,10 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
 static void zynq_init(MachineState *machine)
 {
     ram_addr_t ram_size = machine->ram_size;
-    const char *cpu_model = machine->cpu_model;
     const char *kernel_filename = machine->kernel_filename;
     const char *kernel_cmdline = machine->kernel_cmdline;
     const char *initrd_filename = machine->initrd_filename;
-    ObjectClass *cpu_oc;
-    ARMCPU *cpu;
+    A9MPPrivState *mpcore;
     MemoryRegion *address_space_mem = get_system_memory();
     MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
     MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
@@ -119,39 +118,8 @@ static void zynq_init(MachineState *machine)
     Error *err = NULL;
     int n;
 
-    if (!cpu_model) {
-        cpu_model = "cortex-a9";
-    }
-    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
-
-    cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
-
-    /* By default A9 CPUs have EL3 enabled.  This board does not
-     * currently support EL3 so the CPU EL3 property is disabled before
-     * realization.
-     */
-    if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
-        object_property_set_bool(OBJECT(cpu), false, "has_el3", &err);
-        if (err) {
-            error_report_err(err);
-            exit(1);
-        }
-    }
-
-    object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", &err);
-    if (err) {
-        error_report_err(err);
-        exit(1);
-    }
-
-    object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", &err);
-    if (err) {
-        error_report_err(err);
-        exit(1);
-    }
-    object_property_set_bool(OBJECT(cpu), true, "realized", &err);
-    if (err) {
-        error_report_err(err);
+    if (machine->cpu_model) {
+        error_report("Zynq does not support CPU model override!\n");
         exit(1);
     }
 
@@ -185,16 +153,27 @@ static void zynq_init(MachineState *machine)
     qdev_init_nofail(dev);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
 
-    dev = qdev_create(NULL, "a9mpcore_priv");
-    qdev_prop_set_uint32(dev, "num-cpu", 1);
-    qdev_init_nofail(dev);
-    busdev = SYS_BUS_DEVICE(dev);
+    mpcore = A9MPCORE_PRIV(object_new("a9mpcore_priv"));
+    qdev_prop_set_uint32(DEVICE(mpcore), "num-cpu", 1);
+    qdev_prop_set_uint32(DEVICE(mpcore), "midr", ZYNQ_BOARD_MIDR);
+    qdev_prop_set_uint64(DEVICE(mpcore), "reset-cbar", MPCORE_PERIPHBASE);
+
+    /* By default A9 CPUs have EL3 enabled.  This board does not
+     * currently support EL3 so the CPU EL3 property is disabled before
+     * realization.
+     */
+    object_property_set_bool(OBJECT(mpcore), false, "has_el3", &error_abort);
+    object_property_set_bool(OBJECT(mpcore), true, "realized", &err);
+    if (err != NULL) {
+        error_report("Couldn't realize the Zynq A9MPCore: %s",
+                     error_get_pretty(err));
+        exit(1);
+    }
+    busdev = SYS_BUS_DEVICE(DEVICE(mpcore));
     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
-    sysbus_connect_irq(busdev, 0,
-                       qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
 
     for (n = 0; n < 64; n++) {
-        pic[n] = qdev_get_gpio_in(dev, n);
+        pic[n] = qdev_get_gpio_in(DEVICE(mpcore), n);
     }
 
     zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index acc419e..c5c8869 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -20,6 +20,7 @@
 
 #include "hw/cpu/a15mpcore.h"
 #include "sysemu/kvm.h"
+#include "qapi/visitor.h"
 
 static void a15mp_priv_set_irq(void *opaque, int irq, int level)
 {
@@ -28,6 +29,39 @@ static void a15mp_priv_set_irq(void *opaque, int irq, int level)
     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
 }
 
+static void a15mpcore_set_num_cpus(Object *obj, Visitor *v,
+                                   void *opaque, const char *name,
+                                   Error **errp)
+{
+    A15MPPrivState *s = A15MPCORE_PRIV(obj);
+    ObjectClass *cpu_oc;
+    Error *err = NULL;
+    int i;
+    int64_t value;
+
+    visit_type_int(v, &value, name, &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    s->num_cpu = value;
+
+    s->cpu = g_new0(ARMCPU, s->num_cpu);
+    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a15");
+
+    for (i = 0; i < s->num_cpu; i++) {
+        object_initialize(&s->cpu[i], sizeof(*s->cpu),
+                          object_class_get_name(cpu_oc));
+
+        object_property_add_alias(obj, "midr", OBJECT(&s->cpu[i]),
+                                  "midr", &error_abort);
+        object_property_add_alias(obj, "reset-cbar", OBJECT(&s->cpu[i]),
+                                  "reset-cbar", &error_abort);
+        object_property_add_alias(obj, "has_el3", OBJECT(&s->cpu[i]),
+                                  "has_el3", &error_abort);
+    }
+}
+
 static void a15mp_priv_initfn(Object *obj)
 {
     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
@@ -39,6 +73,10 @@ static void a15mp_priv_initfn(Object *obj)
         gictype = "kvm-arm-gic";
     }
 
+    object_property_add(obj, "num-cpu", "int",
+                        NULL, a15mpcore_set_num_cpus,
+                        NULL, NULL, NULL);
+
     memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
     sysbus_init_mmio(sbd, &s->container);
 
@@ -50,13 +88,16 @@ static void a15mp_priv_initfn(Object *obj)
 
 static void a15mp_priv_realize(DeviceState *dev, Error **errp)
 {
-    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
     A15MPPrivState *s = A15MPCORE_PRIV(dev);
     DeviceState *gicdev;
     SysBusDevice *busdev;
     int i;
     Error *err = NULL;
 
+    if (!s->cpu) {
+        qdev_prop_set_uint32(dev, "num-cpu", 1);
+    }
+
     gicdev = DEVICE(&s->gic);
     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
     qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
@@ -67,18 +108,26 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
     }
     busdev = SYS_BUS_DEVICE(&s->gic);
 
-    /* Pass through outbound IRQ lines from the GIC */
-    sysbus_pass_irq(sbd, busdev);
-
     /* Pass through inbound GPIO lines to the GIC */
     qdev_init_gpio_in(dev, a15mp_priv_set_irq, s->num_irq - 32);
 
-    /* Wire the outputs from each CPU's generic timer to the
-     * appropriate GIC PPI inputs
-     */
     for (i = 0; i < s->num_cpu; i++) {
-        DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
+        DeviceState *cpudev = DEVICE(&s->cpu[i]);
         int ppibase = s->num_irq - 32 + i * 32;
+
+        object_property_set_bool(OBJECT(&s->cpu[i]), true,
+                                 "realized", &err);
+        if (err) {
+            error_propagate(errp, err);
+            return;
+        }
+        sysbus_connect_irq(busdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
+        sysbus_connect_irq(busdev, i + s->num_cpu,
+                           qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
+        /* Wire the outputs from each CPU's generic timer to the
+         * appropriate GIC PPI inputs
+         */
+
         /* physical timer; we wire it up to the non-secure timer's ID,
          * since a real A15 always has TrustZone but QEMU doesn't.
          */
@@ -104,7 +153,6 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
 }
 
 static Property a15mp_priv_properties[] = {
-    DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
     /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
      * IRQ lines (with another 32 internal). We default to 128+32, which
      * is the number provided by the Cortex-A15MP test chip in the
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index c09358c..4a7c561 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -9,6 +9,7 @@
  */
 
 #include "hw/cpu/a9mpcore.h"
+#include "qapi/visitor.h"
 
 static void a9mp_priv_set_irq(void *opaque, int irq, int level)
 {
@@ -17,10 +18,77 @@ static void a9mp_priv_set_irq(void *opaque, int irq, int level)
     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
 }
 
+static inline void a9mp_priv_set_cpu_irq(A9MPPrivState *s, int irq,
+                                         bool old_pin_state)
+{
+    bool pin_state = s->gic_pin_states[irq] || s->ext_intc_states[irq];
+
+    if (pin_state != old_pin_state) {
+        qemu_set_irq(s->cpu_irq[irq], pin_state);
+    }
+}
+
+static void a9mp_priv_set_ext_irq(void *opaque, int irq, int level)
+{
+    A9MPPrivState *s = (A9MPPrivState *)opaque;
+    bool old_pin_state = s->gic_pin_states[irq] || s->ext_intc_states[irq];
+
+    assert(irq < s->num_cpu);
+    s->ext_intc_states[irq] = level;
+    a9mp_priv_set_cpu_irq(s, irq, old_pin_state);
+}
+
+static void a9mp_priv_set_gic_irq(void *opaque, int irq, int level)
+{
+    A9MPPrivState *s = (A9MPPrivState *)opaque;
+    bool old_pin_state = s->gic_pin_states[irq] || s->ext_intc_states[irq];
+
+    assert(irq < s->num_cpu);
+    s->gic_pin_states[irq] = level;
+    a9mp_priv_set_cpu_irq(s, irq, old_pin_state);
+}
+
+static void a9mpcore_set_num_cpus(Object *obj, Visitor *v,
+                                  void *opaque, const char *name,
+                                  Error **errp)
+{
+    A9MPPrivState *s = A9MPCORE_PRIV(obj);
+    ObjectClass *cpu_oc;
+    Error *err = NULL;
+    int i;
+    int64_t value;
+
+    visit_type_int(v, &value, name, &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    s->num_cpu = value;
+
+    s->cpu = g_new0(ARMCPU, s->num_cpu);
+    cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
+
+    for (i = 0; i < s->num_cpu; i++) {
+        object_initialize(&s->cpu[i], sizeof(*s->cpu),
+                          object_class_get_name(cpu_oc));
+
+        object_property_add_alias(obj, "midr", OBJECT(&s->cpu[i]),
+                                  "midr", &error_abort);
+        object_property_add_alias(obj, "reset-cbar", OBJECT(&s->cpu[i]),
+                                  "reset-cbar", &error_abort);
+        object_property_add_alias(obj, "has_el3", OBJECT(&s->cpu[i]),
+                                  "has_el3", &error_abort);
+    }
+}
+
 static void a9mp_priv_initfn(Object *obj)
 {
     A9MPPrivState *s = A9MPCORE_PRIV(obj);
 
+    object_property_add(obj, "num-cpu", "int",
+                        NULL, a9mpcore_set_num_cpus,
+                        NULL, NULL, NULL);
+
     memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
 
@@ -42,14 +110,18 @@ static void a9mp_priv_initfn(Object *obj)
 
 static void a9mp_priv_realize(DeviceState *dev, Error **errp)
 {
-    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
     A9MPPrivState *s = A9MPCORE_PRIV(dev);
     DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev;
     SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev,
                  *wdtbusdev;
+    qemu_irq *gic_local_cpu_irqs;
     Error *err = NULL;
     int i;
 
+    if (!s->cpu) {
+        qdev_prop_set_uint32(dev, "num-cpu", 1);
+    }
+
     scudev = DEVICE(&s->scu);
     qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
     object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
@@ -69,12 +141,28 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
     }
     gicbusdev = SYS_BUS_DEVICE(&s->gic);
 
-    /* Pass through outbound IRQ lines from the GIC */
-    sysbus_pass_irq(sbd, gicbusdev);
-
     /* Pass through inbound GPIO lines to the GIC */
     qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32);
 
+    gic_local_cpu_irqs = qemu_allocate_irqs(a9mp_priv_set_gic_irq, OBJECT(dev),
+                                            s->num_cpu);
+    s->cpu_irq = g_new0(qemu_irq, s->num_cpu);
+    s->gic_pin_states = g_new0(bool, s->num_cpu);
+    s->ext_intc_states = g_new0(bool, s->num_cpu);
+    for (i = 0; i < s->num_cpu; i++) {
+        object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
+        if (err) {
+            error_propagate(errp, err);
+            return;
+        }
+        s->cpu_irq[i] = qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ);
+        sysbus_connect_irq(gicbusdev, i + s->num_cpu,
+                           qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
+        sysbus_connect_irq(gicbusdev, i, gic_local_cpu_irqs[i]);
+    }
+    qdev_init_gpio_in_named(dev, a9mp_priv_set_ext_irq, "ext-interrupt",
+                            s->num_cpu);
+
     gtimerdev = DEVICE(&s->gtimer);
     qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu);
     object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err);
@@ -144,7 +232,6 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
 }
 
 static Property a9mp_priv_properties[] = {
-    DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
     /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
      * IRQ lines (with another 32 internal). We default to 64+32, which
      * is the number provided by the Cortex-A9MP test chip in the
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index b2a4950..75dd944 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -364,108 +364,3 @@ static void exynos4210_gic_register_types(void)
 }
 
 type_init(exynos4210_gic_register_types)
-
-/* IRQ OR Gate struct.
- *
- * This device models an OR gate. There are n_in input qdev gpio lines and one
- * output sysbus IRQ line. The output IRQ level is formed as OR between all
- * gpio inputs.
- */
-
-#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate"
-#define EXYNOS4210_IRQ_GATE(obj) \
-    OBJECT_CHECK(Exynos4210IRQGateState, (obj), TYPE_EXYNOS4210_IRQ_GATE)
-
-typedef struct Exynos4210IRQGateState {
-    SysBusDevice parent_obj;
-
-    uint32_t n_in;      /* inputs amount */
-    uint32_t *level;    /* input levels */
-    qemu_irq out;       /* output IRQ */
-} Exynos4210IRQGateState;
-
-static Property exynos4210_irq_gate_properties[] = {
-    DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1),
-    DEFINE_PROP_END_OF_LIST(),
-};
-
-static const VMStateDescription vmstate_exynos4210_irq_gate = {
-    .name = "exynos4210.irq_gate",
-    .version_id = 2,
-    .minimum_version_id = 2,
-    .fields = (VMStateField[]) {
-        VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, 0, n_in),
-        VMSTATE_END_OF_LIST()
-    }
-};
-
-/* Process a change in IRQ input. */
-static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
-{
-    Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque;
-    uint32_t i;
-
-    assert(irq < s->n_in);
-
-    s->level[irq] = level;
-
-    for (i = 0; i < s->n_in; i++) {
-        if (s->level[i] >= 1) {
-            qemu_irq_raise(s->out);
-            return;
-        }
-    }
-
-    qemu_irq_lower(s->out);
-}
-
-static void exynos4210_irq_gate_reset(DeviceState *d)
-{
-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d);
-
-    memset(s->level, 0, s->n_in * sizeof(*s->level));
-}
-
-/*
- * IRQ Gate initialization.
- */
-static int exynos4210_irq_gate_init(SysBusDevice *sbd)
-{
-    DeviceState *dev = DEVICE(sbd);
-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev);
-
-    /* Allocate general purpose input signals and connect a handler to each of
-     * them */
-    qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in);
-
-    s->level = g_malloc0(s->n_in * sizeof(*s->level));
-
-    sysbus_init_irq(sbd, &s->out);
-
-    return 0;
-}
-
-static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(klass);
-    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
-
-    k->init = exynos4210_irq_gate_init;
-    dc->reset = exynos4210_irq_gate_reset;
-    dc->vmsd = &vmstate_exynos4210_irq_gate;
-    dc->props = exynos4210_irq_gate_properties;
-}
-
-static const TypeInfo exynos4210_irq_gate_info = {
-    .name          = TYPE_EXYNOS4210_IRQ_GATE,
-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(Exynos4210IRQGateState),
-    .class_init    = exynos4210_irq_gate_class_init,
-};
-
-static void exynos4210_irq_gate_register_types(void)
-{
-    type_register_static(&exynos4210_irq_gate_info);
-}
-
-type_init(exynos4210_irq_gate_register_types)
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index 5c1820f..404ae65 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -56,7 +56,6 @@
 /*
  * exynos4210 IRQ subsystem stub definitions.
  */
-#define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */
 
 #define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ  64
 #define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ  16
@@ -85,7 +84,6 @@ typedef struct Exynos4210Irq {
 } Exynos4210Irq;
 
 typedef struct Exynos4210State {
-    ARMCPU *cpu[EXYNOS4210_NCPUS];
     Exynos4210Irq irqs;
     qemu_irq *irq_table;
 
diff --git a/include/hw/cpu/a15mpcore.h b/include/hw/cpu/a15mpcore.h
index b423533..9613690 100644
--- a/include/hw/cpu/a15mpcore.h
+++ b/include/hw/cpu/a15mpcore.h
@@ -34,6 +34,8 @@ typedef struct A15MPPrivState {
     SysBusDevice parent_obj;
     /*< public >*/
 
+    ARMCPU *cpu;
+
     uint32_t num_cpu;
     uint32_t num_irq;
     MemoryRegion container;
diff --git a/include/hw/cpu/a9mpcore.h b/include/hw/cpu/a9mpcore.h
index 5d67ca2..97b3ea1 100644
--- a/include/hw/cpu/a9mpcore.h
+++ b/include/hw/cpu/a9mpcore.h
@@ -29,11 +29,17 @@ typedef struct A9MPPrivState {
     MemoryRegion container;
     uint32_t num_irq;
 
+    ARMCPU *cpu;
+
     A9SCUState scu;
     GICState gic;
     A9GTimerState gtimer;
     ARMMPTimerState mptimer;
     ARMMPTimerState wdt;
+
+    qemu_irq *cpu_irq;
+    bool *gic_pin_states;
+    bool *ext_intc_states;
 } A9MPPrivState;
 
 #endif
-- 
2.4.3.3.g905f831

Re: [Qemu-devel] [RFC PATCH v1 0/8] QOM prop overloading + ARM MPCore CPUs

[Liviu Ionescu]

> On 15 Jun 2015, at 01:36, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote:
> 
> Liviu recently brought up a desire for arguments to QOM constructors. P8
> would probably be cleaner if this feature existed, as the number of CPUs
> could be set as a constructor argument. There is no flexibility on when
> this has to be set, it must be done immediately after construction so it
> ideally should be part of construction.

as Peter mentioned in another thread, for some situations instance_init() is too early, realize() is to late.

here is another one, from the implementation of my Cortex-M framework:

    DeviceState *mcu = qdev_alloc(NULL, TYPE_STM32F103RB);
    {
        STM32F103RB_GET_CLASS(mcu)->construct(OBJECT(mcu), machine);

        /* Set the board specific oscillator frequencies. */
        qdev_prop_set_uint32(mcu, "hse-freq-hz", 8000000); /* 8.0 MHz */
        qdev_prop_set_uint32(mcu, "lse-freq-hz", 32768); /* 32 KHz */
    }
    qdev_realize(mcu);


the two properties are in fact aliases to an internal object that handles clocks. doing the MCU construction in .instance_init() is not possible, because it depends on some data not available at that moment, and doing the construction at realize() is too late, because setting properties will no longer be possible after this point.

my solution was to add a custom constructor to each class, and manually chain them up to the parent, as in any OO implementation.


regards,

Liviu

Re: [Qemu-devel] [RFC PATCH v1 0/8] QOM prop overloading + ARM MPCore CPUs

[Alistair Francis]

On Mon, Jun 15, 2015 at 8:36 AM, Peter Crosthwaite
<peter.crosthwaite@xilinx.com> wrote:
>
> Hi All,
>
> This series introduced support for multi QOM properties with the same
> name and then moves the ARM CPUs to the MPCore container objects (yes!
> they are related!)
>
> The application of the QOM change is container objects passing through
> a single property on multiple same-type children as a single alias. The
> immediate use case, is the ARM MPCore where we want to add N cpus but pass
> through the CPU properties for all of them as an alias on the container
> itself. The container property setter should fan out to all the CPUs in the
> container.
>
> Patches 1-5 implement overloaded properties as part of QOM. QOM
> properties do not allow overloading by default, the creator of the
> property has to switch it on.

Looks pretty good. I'm just wondering what the logic is for making it off
by default. Why not make everything overloadable?

Thanks,

Alistair

>
> Patch 6 switches this feature on for alias properties which handles the
> container use case.
>
> Patch 8 is the feature presentation, pulling the CPUs into the ARM
> MPCore container. This is based on a series of Alistair's to do the same.
> This version does the extra refactoring to handle the case of multiple CPUs
> and the problems created around aliases.
>
> Extra discussion points:
>
> The QOM work will probably conflict with Pavel Fedin' work of arrayified
> properties. So I'll resolve that conflict in a future spin.
>
> Liviu recently brought up a desire for arguments to QOM constructors. P8
> would probably be cleaner if this feature existed, as the number of CPUs
> could be set as a constructor argument. There is no flexibility on when
> this has to be set, it must be done immediately after construction so it
> ideally should be part of construction.
>
> My biggest fear is testing of the changes for the affected boards.
> Peter, do you much coverage of these boards in your regressions? Do you
> have automated tests in a git repo somewhere?
>
> Regards,
> Peter
>
>
>
> Peter Crosthwaite (8):
>   qom: Refactor array property code path
>   qom: Add property overloading
>   qom: Implement overloaded property setters
>   qom: Delete all instances of an overloaded property
>   qom: Disallow getting/resolving an overloaded property
>   qom: Enable overloading of Alias properties
>   arm: realview: Factor out CPU property setters
>   arm: axxmpcore: Add CPUs to MPCore
>
>  hw/arm/exynos4210.c         |  72 +++++++-----------------------
>  hw/arm/highbank.c           |  65 +++++----------------------
>  hw/arm/realview.c           | 100 +++++++++++++++++++++++------------------
>  hw/arm/vexpress.c           |  71 +++++++-----------------------
>  hw/arm/xilinx_zynq.c        |  65 ++++++++++-----------------
>  hw/cpu/a15mpcore.c          |  66 ++++++++++++++++++++++++----
>  hw/cpu/a9mpcore.c           |  97 +++++++++++++++++++++++++++++++++++++---
>  hw/intc/exynos4210_gic.c    | 105 --------------------------------------------
>  include/hw/arm/exynos4210.h |   2 -
>  include/hw/cpu/a15mpcore.h  |   2 +
>  include/hw/cpu/a9mpcore.h   |   6 +++
>  include/qom/object.h        |   2 +
>  qom/object.c                |  96 ++++++++++++++++++++++++----------------
>  13 files changed, 341 insertions(+), 408 deletions(-)
>
> --
> 2.4.3.3.g905f831
>
>

Re: [Qemu-devel] [RFC PATCH v1 0/8] QOM prop overloading + ARM MPCore CPUs

[Peter Maydell]

On 14 June 2015 at 23:36, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote
> This series introduced support for multi QOM properties with the same
> name and then moves the ARM CPUs to the MPCore container objects (yes!
> they are related!)
>
> The application of the QOM change is container objects passing through
> a single property on multiple same-type children as a single alias. The
> immediate use case, is the ARM MPCore where we want to add N cpus but pass
> through the CPU properties for all of them as an alias on the container
> itself. The container property setter should fan out to all the CPUs in the
> container.
>
> Patches 1-5 implement overloaded properties as part of QOM. QOM
> properties do not allow overloading by default, the creator of the
> property has to switch it on.
>
> Patch 6 switches this feature on for alias properties which handles the
> container use case.
>
> Patch 8 is the feature presentation, pulling the CPUs into the ARM
> MPCore container. This is based on a series of Alistair's to do the same.
> This version does the extra refactoring to handle the case of multiple CPUs
> and the problems created around aliases.

Hi. I've been going through my to-review folder cleaning it out, and
I found this patchset from back in June in it. Sorry I never got round
to reviewing it back then. This is just a note to say that if you
care about this series you should rebase it and resend it and I'll
have a look at it then.

> My biggest fear is testing of the changes for the affected boards.
> Peter, do you much coverage of these boards in your regressions? Do you
> have automated tests in a git repo somewhere?

The answers to these questions are "nowhere near enough" and
"unfortunately not"...

thanks
-- PMM

Re: [Qemu-devel] [RFC PATCH v1 0/8] QOM prop overloading + ARM MPCore CPUs

[Peter Crosthwaite]

On Fri, Sep 18, 2015 at 9:28 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 14 June 2015 at 23:36, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote
>> This series introduced support for multi QOM properties with the same
>> name and then moves the ARM CPUs to the MPCore container objects (yes!
>> they are related!)
>>
>> The application of the QOM change is container objects passing through
>> a single property on multiple same-type children as a single alias. The
>> immediate use case, is the ARM MPCore where we want to add N cpus but pass
>> through the CPU properties for all of them as an alias on the container
>> itself. The container property setter should fan out to all the CPUs in the
>> container.
>>
>> Patches 1-5 implement overloaded properties as part of QOM. QOM
>> properties do not allow overloading by default, the creator of the
>> property has to switch it on.
>>
>> Patch 6 switches this feature on for alias properties which handles the
>> container use case.
>>
>> Patch 8 is the feature presentation, pulling the CPUs into the ARM
>> MPCore container. This is based on a series of Alistair's to do the same.
>> This version does the extra refactoring to handle the case of multiple CPUs
>> and the problems created around aliases.
>
> Hi. I've been going through my to-review folder cleaning it out, and
> I found this patchset from back in June in it. Sorry I never got round
> to reviewing it back then. This is just a note to say that if you
> care about this series you should rebase it and resend it and I'll
> have a look at it then.
>

Nice catch, A ping of this was on my todo. Ill add it to the queue of
stuff. The other one I have in need of a review is:

http://lists.nongnu.org/archive/html/qemu-devel/2015-07/msg05891.html

>> My biggest fear is testing of the changes for the affected boards.
>> Peter, do you much coverage of these boards in your regressions? Do you
>> have automated tests in a git repo somewhere?
>
> The answers to these questions are "nowhere near enough" and
> "unfortunately not"...
>

How hard would it be to do something Yocto powered? AFAIK Yocto only
supports the one ARM board (Vexpress), three (+ZynqMP, +Zynq) with the
Meta-Xilinx layer and there may be more with other layers (anything in
meta-linaro?). Can we bitbake something that builds out a large number
of ARM machines and tests them all on QEMU?

Regards,
Peter

> thanks
> -- PMM

Re: [Qemu-devel] [RFC PATCH v1 0/8] QOM prop overloading + ARM MPCore CPUs

[Peter Maydell]

On 18 September 2015 at 17:46, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> The other one I have in need of a review is:
>
> http://lists.nongnu.org/archive/html/qemu-devel/2015-07/msg05891.html

Ah, data-driven device registers. I think I decided I didn't
personally care enough about that to put it into my to-review
queue in the first place; I was hoping maybe somebody else
would tackle it instead...

-- PMM

Re: [Qemu-devel] [RFC PATCH v1 0/8] QOM prop overloading + ARM MPCore CPUs

[Richard Purdie]

On Fri, 2015-09-18 at 09:46 -0700, Peter Crosthwaite wrote:
> >> My biggest fear is testing of the changes for the affected boards.
> >> Peter, do you much coverage of these boards in your regressions? Do you
> >> have automated tests in a git repo somewhere?
> >
> > The answers to these questions are "nowhere near enough" and
> > "unfortunately not"...
> >
> 
> How hard would it be to do something Yocto powered? AFAIK Yocto only
> supports the one ARM board (Vexpress), three (+ZynqMP, +Zynq) with the
> Meta-Xilinx layer and there may be more with other layers (anything in
> meta-linaro?). Can we bitbake something that builds out a large number
> of ARM machines and tests them all on QEMU?

Running our standard ARM board tests is a case of:

git clone http://git.yoctoproject.org/git/poky
cd poky
source oe-init-build-env
echo 'INHERIT += "testimage"' >> ./conf/local.conf
MACHINE=qemuarm bitbake core-image-sato
MACHINE=qemuarm bitbake core-image-sato -c testimage

You could replace core-image-sato -> core-image-minimal for a smaller
image and fewer tests or try core-image-sato-sdk or core-image-lsb-sdk
for more.

The Quick Start guide is at
http://www.yoctoproject.org/docs/1.8/yocto-project-qs/yocto-project-qs.html and has various things like precanned lists of prerequisites for the package manager.

Not sure which other boards you could try booting but I know the Zaurus
machines did work a long time ago as we submitted the qemu code. They
are now in their own layer and I've not tried them in a long time.

The above will build its own qemu-native as there are some patches we
rely on (like the network fixes). You can point the qemu recipe at
different source easily enough.

Cheers,

Richard

Re: [Qemu-devel] [RFC PATCH v1 0/8] QOM prop overloading + ARM MPCore CPUs

[Peter Crosthwaite]

On Fri, Sep 18, 2015 at 10:23 AM, Richard Purdie
<richard.purdie@linuxfoundation.org> wrote:
> On Fri, 2015-09-18 at 09:46 -0700, Peter Crosthwaite wrote:
>> >> My biggest fear is testing of the changes for the affected boards.
>> >> Peter, do you much coverage of these boards in your regressions? Do you
>> >> have automated tests in a git repo somewhere?
>> >
>> > The answers to these questions are "nowhere near enough" and
>> > "unfortunately not"...
>> >
>>
>> How hard would it be to do something Yocto powered? AFAIK Yocto only
>> supports the one ARM board (Vexpress), three (+ZynqMP, +Zynq) with the
>> Meta-Xilinx layer and there may be more with other layers (anything in
>> meta-linaro?). Can we bitbake something that builds out a large number
>> of ARM machines and tests them all on QEMU?
>
> Running our standard ARM board tests is a case of:
>
> git clone http://git.yoctoproject.org/git/poky
> cd poky
> source oe-init-build-env
> echo 'INHERIT += "testimage"' >> ./conf/local.conf
> MACHINE=qemuarm bitbake core-image-sato
> MACHINE=qemuarm bitbake core-image-sato -c testimage
>

So qemuarm is implicitly vexpress, I guess we would want to add more,
such as qemuarm-zynq, qemuarm-zaurus, qemuarm-virt etc. Can a single
bitbake core-image-foo build out multiple MACHINEs or does it not work
like that?

> You could replace core-image-sato -> core-image-minimal for a smaller
> image and fewer tests or try core-image-sato-sdk or core-image-lsb-sdk
> for more.
>
> The Quick Start guide is at
> http://www.yoctoproject.org/docs/1.8/yocto-project-qs/yocto-project-qs.html and has various things like precanned lists of prerequisites for the package manager.
>
> Not sure which other boards you could try booting but I know the Zaurus
> machines did work a long time ago as we submitted the qemu code. They
> are now in their own layer and I've not tried them in a long time.
>

Do these multiple vendor layers conflict with each other and is
merging all the different ARM machines to poky mainline feasible?

Something else that is on topic, is we should consider changing
(subject to backwards compat) the default qemuarm machine to virt, as
this machine is well maintained and intended for use as a pure virtual
machine (which is intent of Yocto qemu specific target IIUC).

Regards,
Peter

> The above will build its own qemu-native as there are some patches we
> rely on (like the network fixes). You can point the qemu recipe at
> different source easily enough.
>
> Cheers,
>
> Richard
>

Re: [Qemu-devel] [RFC PATCH v1 0/8] QOM prop overloading + ARM MPCore CPUs

[Richard Purdie]

On Fri, 2015-09-18 at 11:14 -0700, Peter Crosthwaite wrote:
> On Fri, Sep 18, 2015 at 10:23 AM, Richard Purdie
> <richard.purdie@linuxfoundation.org> wrote:
> > On Fri, 2015-09-18 at 09:46 -0700, Peter Crosthwaite wrote:
> >> >> My biggest fear is testing of the changes for the affected boards.
> >> >> Peter, do you much coverage of these boards in your regressions? Do you
> >> >> have automated tests in a git repo somewhere?
> >> >
> >> > The answers to these questions are "nowhere near enough" and
> >> > "unfortunately not"...
> >> >
> >>
> >> How hard would it be to do something Yocto powered? AFAIK Yocto only
> >> supports the one ARM board (Vexpress), three (+ZynqMP, +Zynq) with the
> >> Meta-Xilinx layer and there may be more with other layers (anything in
> >> meta-linaro?). Can we bitbake something that builds out a large number
> >> of ARM machines and tests them all on QEMU?
> >
> > Running our standard ARM board tests is a case of:
> >
> > git clone http://git.yoctoproject.org/git/poky
> > cd poky
> > source oe-init-build-env
> > echo 'INHERIT += "testimage"' >> ./conf/local.conf
> > MACHINE=qemuarm bitbake core-image-sato
> > MACHINE=qemuarm bitbake core-image-sato -c testimage
> >
> 
> So qemuarm is implicitly vexpress, I guess we would want to add more,
> such as qemuarm-zynq, qemuarm-zaurus, qemuarm-virt etc. Can a single
> bitbake core-image-foo build out multiple MACHINEs or does it not work
> like that?

You'd usually just MACHINE=X bitbake <image>; MACHINE=Y bitbake <image>.
If the configuration shares a common set of compiler optimisation flags,
it will reuse the image binaries.

> > You could replace core-image-sato -> core-image-minimal for a smaller
> > image and fewer tests or try core-image-sato-sdk or core-image-lsb-sdk
> > for more.
> >
> > The Quick Start guide is at
> > http://www.yoctoproject.org/docs/1.8/yocto-project-qs/yocto-project-qs.html and has various things like precanned lists of prerequisites for the package manager.
> >
> > Not sure which other boards you could try booting but I know the Zaurus
> > machines did work a long time ago as we submitted the qemu code. They
> > are now in their own layer and I've not tried them in a long time.
> 
> Do these multiple vendor layers conflict with each other and is
> merging all the different ARM machines to poky mainline feasible?

The layer model is intentional like a plugin architecture. OE was once a
monolithic repository, it grew too large and painful to work. We
therefore now have layers which have separate maintainership. The
quality does vary a bit but it did with the monolithic repo too.

In theory you can just plug the layers you want into the core and use
them, they shouldn't conflict.

> Something else that is on topic, is we should consider changing
> (subject to backwards compat) the default qemuarm machine to virt, as
> this machine is well maintained and intended for use as a pure virtual
> machine (which is intent of Yocto qemu specific target IIUC).

That would need some wider discussion with the OE community and our
kernel maintainers since I know we build a specific qemuarm kernel but
in principle it could be done.

There are also qemux86, qemux86-64, qemuppc, qemumips, qemuarm64 and
qemumips64 fwiw. I'm not sure we make the best use of qemu in these so
I'd be interested in any opinions on what we're doing there... :)

FWIW we did leave qemuarm as an armv5 cpu since we tend to test a lot of
of armv7 on real hardware.

Cheers,

Richard