From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36518) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZS2Sx-00053O-0I for qemu-devel@nongnu.org; Wed, 19 Aug 2015 08:27:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZS2St-0008Am-R7 for qemu-devel@nongnu.org; Wed, 19 Aug 2015 08:27:38 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:36172) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZS2St-0008AY-KD for qemu-devel@nongnu.org; Wed, 19 Aug 2015 08:27:35 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NTB000KIX9VIU80@mailout1.w1.samsung.com> for qemu-devel@nongnu.org; Wed, 19 Aug 2015 13:27:31 +0100 (BST) From: Pavel Fedin Date: Wed, 19 Aug 2015 15:27:28 +0300 Message-id: Subject: [Qemu-devel] [PATCH 0/2] cpu_arm: Implement irqchip property for ARM CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Shlomo Pongratz , Shlomo Pongratz ARMv7m CPU needs a link to NVIC instance for processing interrupts. Similarly ARMv8 needs a link to GICv3 for its CPU interface. This series builds upon existing mechanism for linking irqchip and CPU, bringing the code up to date and making it reusable. Pavel Fedin (2): cpu_arm: Rename 'nvic' to 'irqchip' cpu_arm: Use irqchip property instead of direct assignment hw/arm/armv7m.c | 5 ++--- target-arm/cpu.c | 6 ++++++ target-arm/cpu.h | 5 ++++- target-arm/helper.c | 12 ++++++------ 4 files changed, 18 insertions(+), 10 deletions(-) -- 1.9.5.msysgit.0