From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33233) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUDBS-0006D9-9X for qemu-devel@nongnu.org; Tue, 25 Aug 2015 08:18:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZUDBN-00085j-6e for qemu-devel@nongnu.org; Tue, 25 Aug 2015 08:18:34 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:35485) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZUDBN-00082b-1O for qemu-devel@nongnu.org; Tue, 25 Aug 2015 08:18:29 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NTN00EXM0UM5BA0@mailout4.w1.samsung.com> for qemu-devel@nongnu.org; Tue, 25 Aug 2015 13:18:22 +0100 (BST) From: Pavel Fedin Date: Tue, 25 Aug 2015 15:18:18 +0300 Message-id: Subject: [Qemu-devel] [PATCH v2 0/2] cpu_arm: Implement irqchip property for ARM CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Shlomo Pongratz , Shlomo Pongratz ARMv7m CPU needs a link to NVIC instance for processing interrupts. Similarly ARMv8 needs a link to GICv3 for its CPU interface. This series builds upon existing mechanism for linking irqchip and CPU, bringing the code up to date and making it reusable. Another small step towards complete GICv3 implementation. v1 => v2: - Set link to nvic after it has been initialized - Changed object type to "sys-bus-device" because GICv2 and GICv3 do not share common ancestors above that. Pavel Fedin (2): cpu_arm: Rename 'nvic' to 'irqchip' armv7m: Use irqchip property instead of direct assignment hw/arm/armv7m.c | 5 ++--- target-arm/cpu.c | 6 ++++++ target-arm/cpu.h | 5 ++++- target-arm/helper.c | 12 ++++++------ 4 files changed, 18 insertions(+), 10 deletions(-) -- 1.9.5.msysgit.0