* [Qemu-devel] [PATCH v1 0/3] Connect the SPI devices to ZynqMP
@ 2015-09-29 23:03 Alistair Francis
2015-09-29 23:03 ` [Qemu-devel] [PATCH v1 1/3] ssi: Move ssi.h into a seperate directory Alistair Francis
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Alistair Francis @ 2015-09-29 23:03 UTC (permalink / raw)
To: qemu-devel
Cc: edgar.iglesias, peter.maydell, crosthwaitepeter, edgar.iglesias,
alistair.francis
Connect the SPI devices to Xilinx's ZynqMP.
I also need to make some changes to the actual SPI device to
imporove the fuctionality, but for the time being this works.
Alistair Francis (3):
ssi: Move ssi.h into a seperate directory
xilinx_spips: Seperate the state struct into a header
xlnx-zynqmp: Connect the SPI devices
hw/arm/pxa2xx.c | 2 +-
hw/arm/spitz.c | 2 +-
hw/arm/stellaris.c | 2 +-
hw/arm/strongarm.c | 2 +-
hw/arm/tosa.c | 2 +-
hw/arm/xilinx_zynq.c | 2 +-
hw/arm/xlnx-zynqmp.c | 46 ++++++++++++-
hw/arm/z2.c | 2 +-
hw/block/m25p80.c | 2 +-
hw/display/ads7846.c | 2 +-
hw/display/ssd0323.c | 2 +-
hw/microblaze/petalogix_ml605_mmu.c | 2 +-
hw/misc/max111x.c | 2 +-
hw/sd/ssi-sd.c | 2 +-
hw/ssi/pl022.c | 2 +-
hw/ssi/ssi.c | 2 +-
hw/ssi/xilinx_spi.c | 2 +-
hw/ssi/xilinx_spips.c | 104 +---------------------------
include/hw/arm/xlnx-zynqmp.h | 4 ++
include/hw/ssi.h | 94 -------------------------
include/hw/ssi/ssi.h | 96 ++++++++++++++++++++++++++
include/hw/ssi/xilinx_spips.h | 134 ++++++++++++++++++++++++++++++++++++
22 files changed, 296 insertions(+), 214 deletions(-)
delete mode 100644 include/hw/ssi.h
create mode 100644 include/hw/ssi/ssi.h
create mode 100644 include/hw/ssi/xilinx_spips.h
--
1.9.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v1 1/3] ssi: Move ssi.h into a seperate directory 2015-09-29 23:03 [Qemu-devel] [PATCH v1 0/3] Connect the SPI devices to ZynqMP Alistair Francis @ 2015-09-29 23:03 ` Alistair Francis 2015-09-30 21:06 ` Peter Crosthwaite 2015-09-29 23:03 ` [Qemu-devel] [PATCH v1 2/3] xilinx_spips: Seperate the state struct into a header Alistair Francis ` (2 subsequent siblings) 3 siblings, 1 reply; 13+ messages in thread From: Alistair Francis @ 2015-09-29 23:03 UTC (permalink / raw) To: qemu-devel Cc: edgar.iglesias, peter.maydell, crosthwaitepeter, edgar.iglesias, alistair.francis Move the ssi.h include file into the ssi directory. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> --- hw/arm/pxa2xx.c | 2 +- hw/arm/spitz.c | 2 +- hw/arm/stellaris.c | 2 +- hw/arm/strongarm.c | 2 +- hw/arm/tosa.c | 2 +- hw/arm/xilinx_zynq.c | 2 +- hw/arm/z2.c | 2 +- hw/block/m25p80.c | 2 +- hw/display/ads7846.c | 2 +- hw/display/ssd0323.c | 2 +- hw/microblaze/petalogix_ml605_mmu.c | 2 +- hw/misc/max111x.c | 2 +- hw/sd/ssi-sd.c | 2 +- hw/ssi/pl022.c | 2 +- hw/ssi/ssi.c | 2 +- hw/ssi/xilinx_spi.c | 2 +- hw/ssi/xilinx_spips.c | 2 +- include/hw/ssi.h | 94 ------------------------------------ include/hw/ssi/ssi.h | 96 +++++++++++++++++++++++++++++++++++++ 19 files changed, 113 insertions(+), 111 deletions(-) delete mode 100644 include/hw/ssi.h create mode 100644 include/hw/ssi/ssi.h diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 164260a..534c06f 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -12,7 +12,7 @@ #include "sysemu/sysemu.h" #include "hw/char/serial.h" #include "hw/i2c/i2c.h" -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" #include "sysemu/char.h" #include "sysemu/block-backend.h" #include "sysemu/blockdev.h" diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 2af03be..c9405af 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -16,7 +16,7 @@ #include "sysemu/sysemu.h" #include "hw/pcmcia.h" #include "hw/i2c/i2c.h" -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" #include "hw/block/flash.h" #include "qemu/timer.h" #include "hw/devices.h" diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 3d6486f..c785e90 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -8,7 +8,7 @@ */ #include "hw/sysbus.h" -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" #include "hw/arm/arm.h" #include "hw/devices.h" #include "qemu/timer.h" diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 9624ecb..4d2ba02 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -34,7 +34,7 @@ #include "hw/arm/arm.h" #include "sysemu/char.h" #include "sysemu/sysemu.h" -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" //#define DEBUG diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c index 51d0b89..6b210a6 100644 --- a/hw/arm/tosa.c +++ b/hw/arm/tosa.c @@ -19,7 +19,7 @@ #include "hw/pcmcia.h" #include "hw/boards.h" #include "hw/i2c/i2c.h" -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" #include "sysemu/block-backend.h" #include "hw/sysbus.h" #include "exec/address-spaces.h" diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 9f89483..9db9602 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -24,7 +24,7 @@ #include "hw/block/flash.h" #include "sysemu/block-backend.h" #include "hw/loader.h" -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" #include "qemu/error-report.h" #define NUM_SPI_FLASHES 4 diff --git a/hw/arm/z2.c b/hw/arm/z2.c index b44eb76..c82fe2c 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -16,7 +16,7 @@ #include "hw/arm/arm.h" #include "hw/devices.h" #include "hw/i2c/i2c.h" -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" #include "hw/boards.h" #include "sysemu/sysemu.h" #include "hw/block/flash.h" diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index efc43dd..44830c7 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -24,7 +24,7 @@ #include "hw/hw.h" #include "sysemu/block-backend.h" #include "sysemu/blockdev.h" -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" #ifndef M25P80_ERR_DEBUG #define M25P80_ERR_DEBUG 0 diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c index 3f35369..cb82317 100644 --- a/hw/display/ads7846.c +++ b/hw/display/ads7846.c @@ -10,7 +10,7 @@ * GNU GPL, version 2 or (at your option) any later version. */ -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" #include "ui/console.h" typedef struct { diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c index 9727007..7545da8 100644 --- a/hw/display/ssd0323.c +++ b/hw/display/ssd0323.c @@ -10,7 +10,7 @@ /* The controller can support a variety of different displays, but we only implement one. Most of the commends relating to brightness and geometry setup are ignored. */ -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" #include "ui/console.h" //#define DEBUG_SSD0323 1 diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index 462060f..5366cec 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -35,7 +35,7 @@ #include "sysemu/block-backend.h" #include "hw/char/serial.h" #include "exec/address-spaces.h" -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" #include "boot.h" diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c index bef3651..d619d61 100644 --- a/hw/misc/max111x.c +++ b/hw/misc/max111x.c @@ -10,7 +10,7 @@ * GNU GPL, version 2 or (at your option) any later version. */ -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" typedef struct { SSISlave parent_obj; diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index e4b2d4f..4fe00fd 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -12,7 +12,7 @@ #include "sysemu/block-backend.h" #include "sysemu/blockdev.h" -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" #include "hw/sd.h" //#define DEBUG_SSI_SD 1 diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c index 61d568f..0bbf633 100644 --- a/hw/ssi/pl022.c +++ b/hw/ssi/pl022.c @@ -8,7 +8,7 @@ */ #include "hw/sysbus.h" -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" //#define DEBUG_PL022 1 diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c index 2aab79b..a0f57c0 100644 --- a/hw/ssi/ssi.c +++ b/hw/ssi/ssi.c @@ -12,7 +12,7 @@ * GNU GPL, version 2 or (at your option) any later version. */ -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" struct SSIBus { BusState parent_obj; diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index 620573c..94bb2a7 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -29,7 +29,7 @@ #include "qemu/log.h" #include "qemu/fifo8.h" -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" #ifdef XILINX_SPI_ERR_DEBUG #define DB_PRINT(...) do { \ diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 0910f54..e9471ff 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -27,7 +27,7 @@ #include "hw/ptimer.h" #include "qemu/log.h" #include "qemu/fifo8.h" -#include "hw/ssi.h" +#include "hw/ssi/ssi.h" #include "qemu/bitops.h" #ifndef XILINX_SPIPS_ERR_DEBUG diff --git a/include/hw/ssi.h b/include/hw/ssi.h deleted file mode 100644 index df0f838..0000000 --- a/include/hw/ssi.h +++ /dev/null @@ -1,94 +0,0 @@ -/* QEMU Synchronous Serial Interface support. */ - -/* In principle SSI is a point-point interface. As such the qemu - implementation has a single slave device on a "bus". - However it is fairly common for boards to have multiple slaves - connected to a single master, and select devices with an external - chip select. This is implemented in qemu by having an explicit mux device. - It is assumed that master and slave are both using the same transfer width. - */ - -#ifndef QEMU_SSI_H -#define QEMU_SSI_H - -#include "hw/qdev.h" - -typedef struct SSISlave SSISlave; - -#define TYPE_SSI_SLAVE "ssi-slave" -#define SSI_SLAVE(obj) \ - OBJECT_CHECK(SSISlave, (obj), TYPE_SSI_SLAVE) -#define SSI_SLAVE_CLASS(klass) \ - OBJECT_CLASS_CHECK(SSISlaveClass, (klass), TYPE_SSI_SLAVE) -#define SSI_SLAVE_GET_CLASS(obj) \ - OBJECT_GET_CLASS(SSISlaveClass, (obj), TYPE_SSI_SLAVE) - -#define SSI_GPIO_CS "ssi-gpio-cs" - -typedef enum { - SSI_CS_NONE = 0, - SSI_CS_LOW, - SSI_CS_HIGH, -} SSICSMode; - -/* Slave devices. */ -typedef struct SSISlaveClass { - DeviceClass parent_class; - - int (*init)(SSISlave *dev); - - /* if you have standard or no CS behaviour, just override transfer. - * This is called when the device cs is active (true by default). - */ - uint32_t (*transfer)(SSISlave *dev, uint32_t val); - /* called when the CS line changes. Optional, devices only need to implement - * this if they have side effects associated with the cs line (beyond - * tristating the txrx lines). - */ - int (*set_cs)(SSISlave *dev, bool select); - /* define whether or not CS exists and is active low/high */ - SSICSMode cs_polarity; - - /* if you have non-standard CS behaviour override this to take control - * of the CS behaviour at the device level. transfer, set_cs, and - * cs_polarity are unused if this is overwritten. Transfer_raw will - * always be called for the device for every txrx access to the parent bus - */ - uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val); -} SSISlaveClass; - -struct SSISlave { - DeviceState parent_obj; - - /* Chip select state */ - bool cs; -}; - -#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) - -extern const VMStateDescription vmstate_ssi_slave; - -#define VMSTATE_SSI_SLAVE(_field, _state) { \ - .name = (stringify(_field)), \ - .size = sizeof(SSISlave), \ - .vmsd = &vmstate_ssi_slave, \ - .flags = VMS_STRUCT, \ - .offset = vmstate_offset_value(_state, _field, SSISlave), \ -} - -DeviceState *ssi_create_slave(SSIBus *bus, const char *name); -DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name); - -/* Master interface. */ -SSIBus *ssi_create_bus(DeviceState *parent, const char *name); - -uint32_t ssi_transfer(SSIBus *bus, uint32_t val); - -/* Automatically connect all children nodes a spi controller as slaves */ -void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_lines, - SSIBus *bus); - -/* max111x.c */ -void max111x_set_input(DeviceState *dev, int line, uint8_t value); - -#endif diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h new file mode 100644 index 0000000..4a0a539 --- /dev/null +++ b/include/hw/ssi/ssi.h @@ -0,0 +1,96 @@ +/* QEMU Synchronous Serial Interface support. */ + +/* In principle SSI is a point-point interface. As such the qemu + implementation has a single slave device on a "bus". + However it is fairly common for boards to have multiple slaves + connected to a single master, and select devices with an external + chip select. This is implemented in qemu by having an explicit mux device. + It is assumed that master and slave are both using the same transfer width. + */ + +#ifndef QEMU_SSI_H +#define QEMU_SSI_H + +#include "hw/qdev.h" + +typedef struct SSISlave SSISlave; +typedef struct SSISlaveClass SSISlaveClass; +typedef enum SSICSMode SSICSMode; + +#define TYPE_SSI_SLAVE "ssi-slave" +#define SSI_SLAVE(obj) \ + OBJECT_CHECK(SSISlave, (obj), TYPE_SSI_SLAVE) +#define SSI_SLAVE_CLASS(klass) \ + OBJECT_CLASS_CHECK(SSISlaveClass, (klass), TYPE_SSI_SLAVE) +#define SSI_SLAVE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(SSISlaveClass, (obj), TYPE_SSI_SLAVE) + +#define SSI_GPIO_CS "ssi-gpio-cs" + +enum SSICSMode { + SSI_CS_NONE = 0, + SSI_CS_LOW, + SSI_CS_HIGH, +}; + +/* Slave devices. */ +struct SSISlaveClass { + DeviceClass parent_class; + + int (*init)(SSISlave *dev); + + /* if you have standard or no CS behaviour, just override transfer. + * This is called when the device cs is active (true by default). + */ + uint32_t (*transfer)(SSISlave *dev, uint32_t val); + /* called when the CS line changes. Optional, devices only need to implement + * this if they have side effects associated with the cs line (beyond + * tristating the txrx lines). + */ + int (*set_cs)(SSISlave *dev, bool select); + /* define whether or not CS exists and is active low/high */ + SSICSMode cs_polarity; + + /* if you have non-standard CS behaviour override this to take control + * of the CS behaviour at the device level. transfer, set_cs, and + * cs_polarity are unused if this is overwritten. Transfer_raw will + * always be called for the device for every txrx access to the parent bus + */ + uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val); +}; + +struct SSISlave { + DeviceState parent_obj; + + /* Chip select state */ + bool cs; +}; + +#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) + +extern const VMStateDescription vmstate_ssi_slave; + +#define VMSTATE_SSI_SLAVE(_field, _state) { \ + .name = (stringify(_field)), \ + .size = sizeof(SSISlave), \ + .vmsd = &vmstate_ssi_slave, \ + .flags = VMS_STRUCT, \ + .offset = vmstate_offset_value(_state, _field, SSISlave), \ +} + +DeviceState *ssi_create_slave(SSIBus *bus, const char *name); +DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name); + +/* Master interface. */ +SSIBus *ssi_create_bus(DeviceState *parent, const char *name); + +uint32_t ssi_transfer(SSIBus *bus, uint32_t val); + +/* Automatically connect all children nodes a spi controller as slaves */ +void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_lines, + SSIBus *bus); + +/* max111x.c */ +void max111x_set_input(DeviceState *dev, int line, uint8_t value); + +#endif -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/3] ssi: Move ssi.h into a seperate directory 2015-09-29 23:03 ` [Qemu-devel] [PATCH v1 1/3] ssi: Move ssi.h into a seperate directory Alistair Francis @ 2015-09-30 21:06 ` Peter Crosthwaite 2015-10-01 17:19 ` Alistair Francis 0 siblings, 1 reply; 13+ messages in thread From: Peter Crosthwaite @ 2015-09-30 21:06 UTC (permalink / raw) To: Alistair Francis Cc: Edgar Iglesias, Peter Maydell, qemu-devel@nongnu.org Developers, Edgar E. Iglesias On Tue, Sep 29, 2015 at 4:03 PM, Alistair Francis <alistair.francis@xilinx.com> wrote: > Move the ssi.h include file into the ssi directory. > > Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> > --- > > hw/arm/pxa2xx.c | 2 +- > hw/arm/spitz.c | 2 +- > hw/arm/stellaris.c | 2 +- > hw/arm/strongarm.c | 2 +- > hw/arm/tosa.c | 2 +- > hw/arm/xilinx_zynq.c | 2 +- > hw/arm/z2.c | 2 +- > hw/block/m25p80.c | 2 +- > hw/display/ads7846.c | 2 +- > hw/display/ssd0323.c | 2 +- > hw/microblaze/petalogix_ml605_mmu.c | 2 +- > hw/misc/max111x.c | 2 +- > hw/sd/ssi-sd.c | 2 +- > hw/ssi/pl022.c | 2 +- > hw/ssi/ssi.c | 2 +- > hw/ssi/xilinx_spi.c | 2 +- > hw/ssi/xilinx_spips.c | 2 +- > include/hw/ssi.h | 94 ------------------------------------ > include/hw/ssi/ssi.h | 96 +++++++++++++++++++++++++++++++++++++ Curious as to why git didn't pick this up as a rename (I think it should handle small diffs in the renaming). Do you have rename detection turned on? Regards, Peter > 19 files changed, 113 insertions(+), 111 deletions(-) > delete mode 100644 include/hw/ssi.h > create mode 100644 include/hw/ssi/ssi.h > > diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c > index 164260a..534c06f 100644 > --- a/hw/arm/pxa2xx.c > +++ b/hw/arm/pxa2xx.c > @@ -12,7 +12,7 @@ > #include "sysemu/sysemu.h" > #include "hw/char/serial.h" > #include "hw/i2c/i2c.h" > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > #include "sysemu/char.h" > #include "sysemu/block-backend.h" > #include "sysemu/blockdev.h" > diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c > index 2af03be..c9405af 100644 > --- a/hw/arm/spitz.c > +++ b/hw/arm/spitz.c > @@ -16,7 +16,7 @@ > #include "sysemu/sysemu.h" > #include "hw/pcmcia.h" > #include "hw/i2c/i2c.h" > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > #include "hw/block/flash.h" > #include "qemu/timer.h" > #include "hw/devices.h" > diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c > index 3d6486f..c785e90 100644 > --- a/hw/arm/stellaris.c > +++ b/hw/arm/stellaris.c > @@ -8,7 +8,7 @@ > */ > > #include "hw/sysbus.h" > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > #include "hw/arm/arm.h" > #include "hw/devices.h" > #include "qemu/timer.h" > diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c > index 9624ecb..4d2ba02 100644 > --- a/hw/arm/strongarm.c > +++ b/hw/arm/strongarm.c > @@ -34,7 +34,7 @@ > #include "hw/arm/arm.h" > #include "sysemu/char.h" > #include "sysemu/sysemu.h" > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > > //#define DEBUG > > diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c > index 51d0b89..6b210a6 100644 > --- a/hw/arm/tosa.c > +++ b/hw/arm/tosa.c > @@ -19,7 +19,7 @@ > #include "hw/pcmcia.h" > #include "hw/boards.h" > #include "hw/i2c/i2c.h" > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > #include "sysemu/block-backend.h" > #include "hw/sysbus.h" > #include "exec/address-spaces.h" > diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c > index 9f89483..9db9602 100644 > --- a/hw/arm/xilinx_zynq.c > +++ b/hw/arm/xilinx_zynq.c > @@ -24,7 +24,7 @@ > #include "hw/block/flash.h" > #include "sysemu/block-backend.h" > #include "hw/loader.h" > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > #include "qemu/error-report.h" > > #define NUM_SPI_FLASHES 4 > diff --git a/hw/arm/z2.c b/hw/arm/z2.c > index b44eb76..c82fe2c 100644 > --- a/hw/arm/z2.c > +++ b/hw/arm/z2.c > @@ -16,7 +16,7 @@ > #include "hw/arm/arm.h" > #include "hw/devices.h" > #include "hw/i2c/i2c.h" > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > #include "hw/boards.h" > #include "sysemu/sysemu.h" > #include "hw/block/flash.h" > diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c > index efc43dd..44830c7 100644 > --- a/hw/block/m25p80.c > +++ b/hw/block/m25p80.c > @@ -24,7 +24,7 @@ > #include "hw/hw.h" > #include "sysemu/block-backend.h" > #include "sysemu/blockdev.h" > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > > #ifndef M25P80_ERR_DEBUG > #define M25P80_ERR_DEBUG 0 > diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c > index 3f35369..cb82317 100644 > --- a/hw/display/ads7846.c > +++ b/hw/display/ads7846.c > @@ -10,7 +10,7 @@ > * GNU GPL, version 2 or (at your option) any later version. > */ > > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > #include "ui/console.h" > > typedef struct { > diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c > index 9727007..7545da8 100644 > --- a/hw/display/ssd0323.c > +++ b/hw/display/ssd0323.c > @@ -10,7 +10,7 @@ > /* The controller can support a variety of different displays, but we only > implement one. Most of the commends relating to brightness and geometry > setup are ignored. */ > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > #include "ui/console.h" > > //#define DEBUG_SSD0323 1 > diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c > index 462060f..5366cec 100644 > --- a/hw/microblaze/petalogix_ml605_mmu.c > +++ b/hw/microblaze/petalogix_ml605_mmu.c > @@ -35,7 +35,7 @@ > #include "sysemu/block-backend.h" > #include "hw/char/serial.h" > #include "exec/address-spaces.h" > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > > #include "boot.h" > > diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c > index bef3651..d619d61 100644 > --- a/hw/misc/max111x.c > +++ b/hw/misc/max111x.c > @@ -10,7 +10,7 @@ > * GNU GPL, version 2 or (at your option) any later version. > */ > > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > > typedef struct { > SSISlave parent_obj; > diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c > index e4b2d4f..4fe00fd 100644 > --- a/hw/sd/ssi-sd.c > +++ b/hw/sd/ssi-sd.c > @@ -12,7 +12,7 @@ > > #include "sysemu/block-backend.h" > #include "sysemu/blockdev.h" > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > #include "hw/sd.h" > > //#define DEBUG_SSI_SD 1 > diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c > index 61d568f..0bbf633 100644 > --- a/hw/ssi/pl022.c > +++ b/hw/ssi/pl022.c > @@ -8,7 +8,7 @@ > */ > > #include "hw/sysbus.h" > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > > //#define DEBUG_PL022 1 > > diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c > index 2aab79b..a0f57c0 100644 > --- a/hw/ssi/ssi.c > +++ b/hw/ssi/ssi.c > @@ -12,7 +12,7 @@ > * GNU GPL, version 2 or (at your option) any later version. > */ > > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > > struct SSIBus { > BusState parent_obj; > diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c > index 620573c..94bb2a7 100644 > --- a/hw/ssi/xilinx_spi.c > +++ b/hw/ssi/xilinx_spi.c > @@ -29,7 +29,7 @@ > #include "qemu/log.h" > #include "qemu/fifo8.h" > > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > > #ifdef XILINX_SPI_ERR_DEBUG > #define DB_PRINT(...) do { \ > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c > index 0910f54..e9471ff 100644 > --- a/hw/ssi/xilinx_spips.c > +++ b/hw/ssi/xilinx_spips.c > @@ -27,7 +27,7 @@ > #include "hw/ptimer.h" > #include "qemu/log.h" > #include "qemu/fifo8.h" > -#include "hw/ssi.h" > +#include "hw/ssi/ssi.h" > #include "qemu/bitops.h" > > #ifndef XILINX_SPIPS_ERR_DEBUG > diff --git a/include/hw/ssi.h b/include/hw/ssi.h > deleted file mode 100644 > index df0f838..0000000 > --- a/include/hw/ssi.h > +++ /dev/null > @@ -1,94 +0,0 @@ > -/* QEMU Synchronous Serial Interface support. */ > - > -/* In principle SSI is a point-point interface. As such the qemu > - implementation has a single slave device on a "bus". > - However it is fairly common for boards to have multiple slaves > - connected to a single master, and select devices with an external > - chip select. This is implemented in qemu by having an explicit mux device. > - It is assumed that master and slave are both using the same transfer width. > - */ > - > -#ifndef QEMU_SSI_H > -#define QEMU_SSI_H > - > -#include "hw/qdev.h" > - > -typedef struct SSISlave SSISlave; > - > -#define TYPE_SSI_SLAVE "ssi-slave" > -#define SSI_SLAVE(obj) \ > - OBJECT_CHECK(SSISlave, (obj), TYPE_SSI_SLAVE) > -#define SSI_SLAVE_CLASS(klass) \ > - OBJECT_CLASS_CHECK(SSISlaveClass, (klass), TYPE_SSI_SLAVE) > -#define SSI_SLAVE_GET_CLASS(obj) \ > - OBJECT_GET_CLASS(SSISlaveClass, (obj), TYPE_SSI_SLAVE) > - > -#define SSI_GPIO_CS "ssi-gpio-cs" > - > -typedef enum { > - SSI_CS_NONE = 0, > - SSI_CS_LOW, > - SSI_CS_HIGH, > -} SSICSMode; > - > -/* Slave devices. */ > -typedef struct SSISlaveClass { > - DeviceClass parent_class; > - > - int (*init)(SSISlave *dev); > - > - /* if you have standard or no CS behaviour, just override transfer. > - * This is called when the device cs is active (true by default). > - */ > - uint32_t (*transfer)(SSISlave *dev, uint32_t val); > - /* called when the CS line changes. Optional, devices only need to implement > - * this if they have side effects associated with the cs line (beyond > - * tristating the txrx lines). > - */ > - int (*set_cs)(SSISlave *dev, bool select); > - /* define whether or not CS exists and is active low/high */ > - SSICSMode cs_polarity; > - > - /* if you have non-standard CS behaviour override this to take control > - * of the CS behaviour at the device level. transfer, set_cs, and > - * cs_polarity are unused if this is overwritten. Transfer_raw will > - * always be called for the device for every txrx access to the parent bus > - */ > - uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val); > -} SSISlaveClass; > - > -struct SSISlave { > - DeviceState parent_obj; > - > - /* Chip select state */ > - bool cs; > -}; > - > -#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) > - > -extern const VMStateDescription vmstate_ssi_slave; > - > -#define VMSTATE_SSI_SLAVE(_field, _state) { \ > - .name = (stringify(_field)), \ > - .size = sizeof(SSISlave), \ > - .vmsd = &vmstate_ssi_slave, \ > - .flags = VMS_STRUCT, \ > - .offset = vmstate_offset_value(_state, _field, SSISlave), \ > -} > - > -DeviceState *ssi_create_slave(SSIBus *bus, const char *name); > -DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name); > - > -/* Master interface. */ > -SSIBus *ssi_create_bus(DeviceState *parent, const char *name); > - > -uint32_t ssi_transfer(SSIBus *bus, uint32_t val); > - > -/* Automatically connect all children nodes a spi controller as slaves */ > -void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_lines, > - SSIBus *bus); > - > -/* max111x.c */ > -void max111x_set_input(DeviceState *dev, int line, uint8_t value); > - > -#endif > diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h > new file mode 100644 > index 0000000..4a0a539 > --- /dev/null > +++ b/include/hw/ssi/ssi.h > @@ -0,0 +1,96 @@ > +/* QEMU Synchronous Serial Interface support. */ > + > +/* In principle SSI is a point-point interface. As such the qemu > + implementation has a single slave device on a "bus". > + However it is fairly common for boards to have multiple slaves > + connected to a single master, and select devices with an external > + chip select. This is implemented in qemu by having an explicit mux device. > + It is assumed that master and slave are both using the same transfer width. > + */ > + > +#ifndef QEMU_SSI_H > +#define QEMU_SSI_H > + > +#include "hw/qdev.h" > + > +typedef struct SSISlave SSISlave; > +typedef struct SSISlaveClass SSISlaveClass; > +typedef enum SSICSMode SSICSMode; > + > +#define TYPE_SSI_SLAVE "ssi-slave" > +#define SSI_SLAVE(obj) \ > + OBJECT_CHECK(SSISlave, (obj), TYPE_SSI_SLAVE) > +#define SSI_SLAVE_CLASS(klass) \ > + OBJECT_CLASS_CHECK(SSISlaveClass, (klass), TYPE_SSI_SLAVE) > +#define SSI_SLAVE_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(SSISlaveClass, (obj), TYPE_SSI_SLAVE) > + > +#define SSI_GPIO_CS "ssi-gpio-cs" > + > +enum SSICSMode { > + SSI_CS_NONE = 0, > + SSI_CS_LOW, > + SSI_CS_HIGH, > +}; > + > +/* Slave devices. */ > +struct SSISlaveClass { > + DeviceClass parent_class; > + > + int (*init)(SSISlave *dev); > + > + /* if you have standard or no CS behaviour, just override transfer. > + * This is called when the device cs is active (true by default). > + */ > + uint32_t (*transfer)(SSISlave *dev, uint32_t val); > + /* called when the CS line changes. Optional, devices only need to implement > + * this if they have side effects associated with the cs line (beyond > + * tristating the txrx lines). > + */ > + int (*set_cs)(SSISlave *dev, bool select); > + /* define whether or not CS exists and is active low/high */ > + SSICSMode cs_polarity; > + > + /* if you have non-standard CS behaviour override this to take control > + * of the CS behaviour at the device level. transfer, set_cs, and > + * cs_polarity are unused if this is overwritten. Transfer_raw will > + * always be called for the device for every txrx access to the parent bus > + */ > + uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val); > +}; > + > +struct SSISlave { > + DeviceState parent_obj; > + > + /* Chip select state */ > + bool cs; > +}; > + > +#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) > + > +extern const VMStateDescription vmstate_ssi_slave; > + > +#define VMSTATE_SSI_SLAVE(_field, _state) { \ > + .name = (stringify(_field)), \ > + .size = sizeof(SSISlave), \ > + .vmsd = &vmstate_ssi_slave, \ > + .flags = VMS_STRUCT, \ > + .offset = vmstate_offset_value(_state, _field, SSISlave), \ > +} > + > +DeviceState *ssi_create_slave(SSIBus *bus, const char *name); > +DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name); > + > +/* Master interface. */ > +SSIBus *ssi_create_bus(DeviceState *parent, const char *name); > + > +uint32_t ssi_transfer(SSIBus *bus, uint32_t val); > + > +/* Automatically connect all children nodes a spi controller as slaves */ > +void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_lines, > + SSIBus *bus); > + > +/* max111x.c */ > +void max111x_set_input(DeviceState *dev, int line, uint8_t value); > + > +#endif > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/3] ssi: Move ssi.h into a seperate directory 2015-09-30 21:06 ` Peter Crosthwaite @ 2015-10-01 17:19 ` Alistair Francis 2015-10-01 17:39 ` Peter Crosthwaite 0 siblings, 1 reply; 13+ messages in thread From: Alistair Francis @ 2015-10-01 17:19 UTC (permalink / raw) To: Peter Crosthwaite Cc: Edgar Iglesias, Peter Maydell, Edgar E. Iglesias, qemu-devel@nongnu.org Developers, Alistair Francis On Wed, Sep 30, 2015 at 2:06 PM, Peter Crosthwaite <crosthwaitepeter@gmail.com> wrote: > On Tue, Sep 29, 2015 at 4:03 PM, Alistair Francis > <alistair.francis@xilinx.com> wrote: >> Move the ssi.h include file into the ssi directory. >> >> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> >> --- >> >> hw/arm/pxa2xx.c | 2 +- >> hw/arm/spitz.c | 2 +- >> hw/arm/stellaris.c | 2 +- >> hw/arm/strongarm.c | 2 +- >> hw/arm/tosa.c | 2 +- >> hw/arm/xilinx_zynq.c | 2 +- >> hw/arm/z2.c | 2 +- >> hw/block/m25p80.c | 2 +- >> hw/display/ads7846.c | 2 +- >> hw/display/ssd0323.c | 2 +- >> hw/microblaze/petalogix_ml605_mmu.c | 2 +- >> hw/misc/max111x.c | 2 +- >> hw/sd/ssi-sd.c | 2 +- >> hw/ssi/pl022.c | 2 +- >> hw/ssi/ssi.c | 2 +- >> hw/ssi/xilinx_spi.c | 2 +- >> hw/ssi/xilinx_spips.c | 2 +- >> include/hw/ssi.h | 94 ------------------------------------ >> include/hw/ssi/ssi.h | 96 +++++++++++++++++++++++++++++++++++++ > > Curious as to why git didn't pick this up as a rename (I think it > should handle small diffs in the renaming). Do you have rename > detection turned on? I do have rename detection turned on. I think the reason it didn't is because I tiddied up the code a little bit when I moved it. Checkpatch was reproting errors on the struct typedeffs so I had to change that. Thanks, Alistair > > Regards, > Peter > >> 19 files changed, 113 insertions(+), 111 deletions(-) >> delete mode 100644 include/hw/ssi.h >> create mode 100644 include/hw/ssi/ssi.h >> >> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c >> index 164260a..534c06f 100644 >> --- a/hw/arm/pxa2xx.c >> +++ b/hw/arm/pxa2xx.c >> @@ -12,7 +12,7 @@ >> #include "sysemu/sysemu.h" >> #include "hw/char/serial.h" >> #include "hw/i2c/i2c.h" >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> #include "sysemu/char.h" >> #include "sysemu/block-backend.h" >> #include "sysemu/blockdev.h" >> diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c >> index 2af03be..c9405af 100644 >> --- a/hw/arm/spitz.c >> +++ b/hw/arm/spitz.c >> @@ -16,7 +16,7 @@ >> #include "sysemu/sysemu.h" >> #include "hw/pcmcia.h" >> #include "hw/i2c/i2c.h" >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> #include "hw/block/flash.h" >> #include "qemu/timer.h" >> #include "hw/devices.h" >> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c >> index 3d6486f..c785e90 100644 >> --- a/hw/arm/stellaris.c >> +++ b/hw/arm/stellaris.c >> @@ -8,7 +8,7 @@ >> */ >> >> #include "hw/sysbus.h" >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> #include "hw/arm/arm.h" >> #include "hw/devices.h" >> #include "qemu/timer.h" >> diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c >> index 9624ecb..4d2ba02 100644 >> --- a/hw/arm/strongarm.c >> +++ b/hw/arm/strongarm.c >> @@ -34,7 +34,7 @@ >> #include "hw/arm/arm.h" >> #include "sysemu/char.h" >> #include "sysemu/sysemu.h" >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> >> //#define DEBUG >> >> diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c >> index 51d0b89..6b210a6 100644 >> --- a/hw/arm/tosa.c >> +++ b/hw/arm/tosa.c >> @@ -19,7 +19,7 @@ >> #include "hw/pcmcia.h" >> #include "hw/boards.h" >> #include "hw/i2c/i2c.h" >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> #include "sysemu/block-backend.h" >> #include "hw/sysbus.h" >> #include "exec/address-spaces.h" >> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c >> index 9f89483..9db9602 100644 >> --- a/hw/arm/xilinx_zynq.c >> +++ b/hw/arm/xilinx_zynq.c >> @@ -24,7 +24,7 @@ >> #include "hw/block/flash.h" >> #include "sysemu/block-backend.h" >> #include "hw/loader.h" >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> #include "qemu/error-report.h" >> >> #define NUM_SPI_FLASHES 4 >> diff --git a/hw/arm/z2.c b/hw/arm/z2.c >> index b44eb76..c82fe2c 100644 >> --- a/hw/arm/z2.c >> +++ b/hw/arm/z2.c >> @@ -16,7 +16,7 @@ >> #include "hw/arm/arm.h" >> #include "hw/devices.h" >> #include "hw/i2c/i2c.h" >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> #include "hw/boards.h" >> #include "sysemu/sysemu.h" >> #include "hw/block/flash.h" >> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c >> index efc43dd..44830c7 100644 >> --- a/hw/block/m25p80.c >> +++ b/hw/block/m25p80.c >> @@ -24,7 +24,7 @@ >> #include "hw/hw.h" >> #include "sysemu/block-backend.h" >> #include "sysemu/blockdev.h" >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> >> #ifndef M25P80_ERR_DEBUG >> #define M25P80_ERR_DEBUG 0 >> diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c >> index 3f35369..cb82317 100644 >> --- a/hw/display/ads7846.c >> +++ b/hw/display/ads7846.c >> @@ -10,7 +10,7 @@ >> * GNU GPL, version 2 or (at your option) any later version. >> */ >> >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> #include "ui/console.h" >> >> typedef struct { >> diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c >> index 9727007..7545da8 100644 >> --- a/hw/display/ssd0323.c >> +++ b/hw/display/ssd0323.c >> @@ -10,7 +10,7 @@ >> /* The controller can support a variety of different displays, but we only >> implement one. Most of the commends relating to brightness and geometry >> setup are ignored. */ >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> #include "ui/console.h" >> >> //#define DEBUG_SSD0323 1 >> diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c >> index 462060f..5366cec 100644 >> --- a/hw/microblaze/petalogix_ml605_mmu.c >> +++ b/hw/microblaze/petalogix_ml605_mmu.c >> @@ -35,7 +35,7 @@ >> #include "sysemu/block-backend.h" >> #include "hw/char/serial.h" >> #include "exec/address-spaces.h" >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> >> #include "boot.h" >> >> diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c >> index bef3651..d619d61 100644 >> --- a/hw/misc/max111x.c >> +++ b/hw/misc/max111x.c >> @@ -10,7 +10,7 @@ >> * GNU GPL, version 2 or (at your option) any later version. >> */ >> >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> >> typedef struct { >> SSISlave parent_obj; >> diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c >> index e4b2d4f..4fe00fd 100644 >> --- a/hw/sd/ssi-sd.c >> +++ b/hw/sd/ssi-sd.c >> @@ -12,7 +12,7 @@ >> >> #include "sysemu/block-backend.h" >> #include "sysemu/blockdev.h" >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> #include "hw/sd.h" >> >> //#define DEBUG_SSI_SD 1 >> diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c >> index 61d568f..0bbf633 100644 >> --- a/hw/ssi/pl022.c >> +++ b/hw/ssi/pl022.c >> @@ -8,7 +8,7 @@ >> */ >> >> #include "hw/sysbus.h" >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> >> //#define DEBUG_PL022 1 >> >> diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c >> index 2aab79b..a0f57c0 100644 >> --- a/hw/ssi/ssi.c >> +++ b/hw/ssi/ssi.c >> @@ -12,7 +12,7 @@ >> * GNU GPL, version 2 or (at your option) any later version. >> */ >> >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> >> struct SSIBus { >> BusState parent_obj; >> diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c >> index 620573c..94bb2a7 100644 >> --- a/hw/ssi/xilinx_spi.c >> +++ b/hw/ssi/xilinx_spi.c >> @@ -29,7 +29,7 @@ >> #include "qemu/log.h" >> #include "qemu/fifo8.h" >> >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> >> #ifdef XILINX_SPI_ERR_DEBUG >> #define DB_PRINT(...) do { \ >> diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c >> index 0910f54..e9471ff 100644 >> --- a/hw/ssi/xilinx_spips.c >> +++ b/hw/ssi/xilinx_spips.c >> @@ -27,7 +27,7 @@ >> #include "hw/ptimer.h" >> #include "qemu/log.h" >> #include "qemu/fifo8.h" >> -#include "hw/ssi.h" >> +#include "hw/ssi/ssi.h" >> #include "qemu/bitops.h" >> >> #ifndef XILINX_SPIPS_ERR_DEBUG >> diff --git a/include/hw/ssi.h b/include/hw/ssi.h >> deleted file mode 100644 >> index df0f838..0000000 >> --- a/include/hw/ssi.h >> +++ /dev/null >> @@ -1,94 +0,0 @@ >> -/* QEMU Synchronous Serial Interface support. */ >> - >> -/* In principle SSI is a point-point interface. As such the qemu >> - implementation has a single slave device on a "bus". >> - However it is fairly common for boards to have multiple slaves >> - connected to a single master, and select devices with an external >> - chip select. This is implemented in qemu by having an explicit mux device. >> - It is assumed that master and slave are both using the same transfer width. >> - */ >> - >> -#ifndef QEMU_SSI_H >> -#define QEMU_SSI_H >> - >> -#include "hw/qdev.h" >> - >> -typedef struct SSISlave SSISlave; >> - >> -#define TYPE_SSI_SLAVE "ssi-slave" >> -#define SSI_SLAVE(obj) \ >> - OBJECT_CHECK(SSISlave, (obj), TYPE_SSI_SLAVE) >> -#define SSI_SLAVE_CLASS(klass) \ >> - OBJECT_CLASS_CHECK(SSISlaveClass, (klass), TYPE_SSI_SLAVE) >> -#define SSI_SLAVE_GET_CLASS(obj) \ >> - OBJECT_GET_CLASS(SSISlaveClass, (obj), TYPE_SSI_SLAVE) >> - >> -#define SSI_GPIO_CS "ssi-gpio-cs" >> - >> -typedef enum { >> - SSI_CS_NONE = 0, >> - SSI_CS_LOW, >> - SSI_CS_HIGH, >> -} SSICSMode; >> - >> -/* Slave devices. */ >> -typedef struct SSISlaveClass { >> - DeviceClass parent_class; >> - >> - int (*init)(SSISlave *dev); >> - >> - /* if you have standard or no CS behaviour, just override transfer. >> - * This is called when the device cs is active (true by default). >> - */ >> - uint32_t (*transfer)(SSISlave *dev, uint32_t val); >> - /* called when the CS line changes. Optional, devices only need to implement >> - * this if they have side effects associated with the cs line (beyond >> - * tristating the txrx lines). >> - */ >> - int (*set_cs)(SSISlave *dev, bool select); >> - /* define whether or not CS exists and is active low/high */ >> - SSICSMode cs_polarity; >> - >> - /* if you have non-standard CS behaviour override this to take control >> - * of the CS behaviour at the device level. transfer, set_cs, and >> - * cs_polarity are unused if this is overwritten. Transfer_raw will >> - * always be called for the device for every txrx access to the parent bus >> - */ >> - uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val); >> -} SSISlaveClass; >> - >> -struct SSISlave { >> - DeviceState parent_obj; >> - >> - /* Chip select state */ >> - bool cs; >> -}; >> - >> -#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) >> - >> -extern const VMStateDescription vmstate_ssi_slave; >> - >> -#define VMSTATE_SSI_SLAVE(_field, _state) { \ >> - .name = (stringify(_field)), \ >> - .size = sizeof(SSISlave), \ >> - .vmsd = &vmstate_ssi_slave, \ >> - .flags = VMS_STRUCT, \ >> - .offset = vmstate_offset_value(_state, _field, SSISlave), \ >> -} >> - >> -DeviceState *ssi_create_slave(SSIBus *bus, const char *name); >> -DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name); >> - >> -/* Master interface. */ >> -SSIBus *ssi_create_bus(DeviceState *parent, const char *name); >> - >> -uint32_t ssi_transfer(SSIBus *bus, uint32_t val); >> - >> -/* Automatically connect all children nodes a spi controller as slaves */ >> -void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_lines, >> - SSIBus *bus); >> - >> -/* max111x.c */ >> -void max111x_set_input(DeviceState *dev, int line, uint8_t value); >> - >> -#endif >> diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h >> new file mode 100644 >> index 0000000..4a0a539 >> --- /dev/null >> +++ b/include/hw/ssi/ssi.h >> @@ -0,0 +1,96 @@ >> +/* QEMU Synchronous Serial Interface support. */ >> + >> +/* In principle SSI is a point-point interface. As such the qemu >> + implementation has a single slave device on a "bus". >> + However it is fairly common for boards to have multiple slaves >> + connected to a single master, and select devices with an external >> + chip select. This is implemented in qemu by having an explicit mux device. >> + It is assumed that master and slave are both using the same transfer width. >> + */ >> + >> +#ifndef QEMU_SSI_H >> +#define QEMU_SSI_H >> + >> +#include "hw/qdev.h" >> + >> +typedef struct SSISlave SSISlave; >> +typedef struct SSISlaveClass SSISlaveClass; >> +typedef enum SSICSMode SSICSMode; >> + >> +#define TYPE_SSI_SLAVE "ssi-slave" >> +#define SSI_SLAVE(obj) \ >> + OBJECT_CHECK(SSISlave, (obj), TYPE_SSI_SLAVE) >> +#define SSI_SLAVE_CLASS(klass) \ >> + OBJECT_CLASS_CHECK(SSISlaveClass, (klass), TYPE_SSI_SLAVE) >> +#define SSI_SLAVE_GET_CLASS(obj) \ >> + OBJECT_GET_CLASS(SSISlaveClass, (obj), TYPE_SSI_SLAVE) >> + >> +#define SSI_GPIO_CS "ssi-gpio-cs" >> + >> +enum SSICSMode { >> + SSI_CS_NONE = 0, >> + SSI_CS_LOW, >> + SSI_CS_HIGH, >> +}; >> + >> +/* Slave devices. */ >> +struct SSISlaveClass { >> + DeviceClass parent_class; >> + >> + int (*init)(SSISlave *dev); >> + >> + /* if you have standard or no CS behaviour, just override transfer. >> + * This is called when the device cs is active (true by default). >> + */ >> + uint32_t (*transfer)(SSISlave *dev, uint32_t val); >> + /* called when the CS line changes. Optional, devices only need to implement >> + * this if they have side effects associated with the cs line (beyond >> + * tristating the txrx lines). >> + */ >> + int (*set_cs)(SSISlave *dev, bool select); >> + /* define whether or not CS exists and is active low/high */ >> + SSICSMode cs_polarity; >> + >> + /* if you have non-standard CS behaviour override this to take control >> + * of the CS behaviour at the device level. transfer, set_cs, and >> + * cs_polarity are unused if this is overwritten. Transfer_raw will >> + * always be called for the device for every txrx access to the parent bus >> + */ >> + uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val); >> +}; >> + >> +struct SSISlave { >> + DeviceState parent_obj; >> + >> + /* Chip select state */ >> + bool cs; >> +}; >> + >> +#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) >> + >> +extern const VMStateDescription vmstate_ssi_slave; >> + >> +#define VMSTATE_SSI_SLAVE(_field, _state) { \ >> + .name = (stringify(_field)), \ >> + .size = sizeof(SSISlave), \ >> + .vmsd = &vmstate_ssi_slave, \ >> + .flags = VMS_STRUCT, \ >> + .offset = vmstate_offset_value(_state, _field, SSISlave), \ >> +} >> + >> +DeviceState *ssi_create_slave(SSIBus *bus, const char *name); >> +DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name); >> + >> +/* Master interface. */ >> +SSIBus *ssi_create_bus(DeviceState *parent, const char *name); >> + >> +uint32_t ssi_transfer(SSIBus *bus, uint32_t val); >> + >> +/* Automatically connect all children nodes a spi controller as slaves */ >> +void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_lines, >> + SSIBus *bus); >> + >> +/* max111x.c */ >> +void max111x_set_input(DeviceState *dev, int line, uint8_t value); >> + >> +#endif >> -- >> 1.9.1 >> > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/3] ssi: Move ssi.h into a seperate directory 2015-10-01 17:19 ` Alistair Francis @ 2015-10-01 17:39 ` Peter Crosthwaite 2015-10-02 21:29 ` Alistair Francis 0 siblings, 1 reply; 13+ messages in thread From: Peter Crosthwaite @ 2015-10-01 17:39 UTC (permalink / raw) To: Alistair Francis Cc: Edgar Iglesias, Peter Maydell, qemu-devel@nongnu.org Developers, Edgar E. Iglesias On Thu, Oct 1, 2015 at 10:19 AM, Alistair Francis <alistair.francis@xilinx.com> wrote: > On Wed, Sep 30, 2015 at 2:06 PM, Peter Crosthwaite > <crosthwaitepeter@gmail.com> wrote: >> On Tue, Sep 29, 2015 at 4:03 PM, Alistair Francis >> <alistair.francis@xilinx.com> wrote: >>> Move the ssi.h include file into the ssi directory. >>> >>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> >>> --- >>> >>> hw/arm/pxa2xx.c | 2 +- >>> hw/arm/spitz.c | 2 +- >>> hw/arm/stellaris.c | 2 +- >>> hw/arm/strongarm.c | 2 +- >>> hw/arm/tosa.c | 2 +- >>> hw/arm/xilinx_zynq.c | 2 +- >>> hw/arm/z2.c | 2 +- >>> hw/block/m25p80.c | 2 +- >>> hw/display/ads7846.c | 2 +- >>> hw/display/ssd0323.c | 2 +- >>> hw/microblaze/petalogix_ml605_mmu.c | 2 +- >>> hw/misc/max111x.c | 2 +- >>> hw/sd/ssi-sd.c | 2 +- >>> hw/ssi/pl022.c | 2 +- >>> hw/ssi/ssi.c | 2 +- >>> hw/ssi/xilinx_spi.c | 2 +- >>> hw/ssi/xilinx_spips.c | 2 +- >>> include/hw/ssi.h | 94 ------------------------------------ >>> include/hw/ssi/ssi.h | 96 +++++++++++++++++++++++++++++++++++++ >> >> Curious as to why git didn't pick this up as a rename (I think it >> should handle small diffs in the renaming). Do you have rename >> detection turned on? > > I do have rename detection turned on. I think the reason it didn't is > because I tiddied up the code a little bit when I moved it. Checkpatch > was reproting errors on the struct typedeffs so I had to change that. > Can we do it in two steps and take the hit on the checkpatch fails on P1? Checkpatch fails are acceptable for pure mass-code movements. There is also probably some way to set your rename detction to higher level that should pick it up. Regards, Peter > Thanks, > > Alistair > >> >> Regards, >> Peter >> >>> 19 files changed, 113 insertions(+), 111 deletions(-) >>> delete mode 100644 include/hw/ssi.h >>> create mode 100644 include/hw/ssi/ssi.h >>> >>> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c >>> index 164260a..534c06f 100644 >>> --- a/hw/arm/pxa2xx.c >>> +++ b/hw/arm/pxa2xx.c >>> @@ -12,7 +12,7 @@ >>> #include "sysemu/sysemu.h" >>> #include "hw/char/serial.h" >>> #include "hw/i2c/i2c.h" >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> #include "sysemu/char.h" >>> #include "sysemu/block-backend.h" >>> #include "sysemu/blockdev.h" >>> diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c >>> index 2af03be..c9405af 100644 >>> --- a/hw/arm/spitz.c >>> +++ b/hw/arm/spitz.c >>> @@ -16,7 +16,7 @@ >>> #include "sysemu/sysemu.h" >>> #include "hw/pcmcia.h" >>> #include "hw/i2c/i2c.h" >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> #include "hw/block/flash.h" >>> #include "qemu/timer.h" >>> #include "hw/devices.h" >>> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c >>> index 3d6486f..c785e90 100644 >>> --- a/hw/arm/stellaris.c >>> +++ b/hw/arm/stellaris.c >>> @@ -8,7 +8,7 @@ >>> */ >>> >>> #include "hw/sysbus.h" >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> #include "hw/arm/arm.h" >>> #include "hw/devices.h" >>> #include "qemu/timer.h" >>> diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c >>> index 9624ecb..4d2ba02 100644 >>> --- a/hw/arm/strongarm.c >>> +++ b/hw/arm/strongarm.c >>> @@ -34,7 +34,7 @@ >>> #include "hw/arm/arm.h" >>> #include "sysemu/char.h" >>> #include "sysemu/sysemu.h" >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> >>> //#define DEBUG >>> >>> diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c >>> index 51d0b89..6b210a6 100644 >>> --- a/hw/arm/tosa.c >>> +++ b/hw/arm/tosa.c >>> @@ -19,7 +19,7 @@ >>> #include "hw/pcmcia.h" >>> #include "hw/boards.h" >>> #include "hw/i2c/i2c.h" >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> #include "sysemu/block-backend.h" >>> #include "hw/sysbus.h" >>> #include "exec/address-spaces.h" >>> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c >>> index 9f89483..9db9602 100644 >>> --- a/hw/arm/xilinx_zynq.c >>> +++ b/hw/arm/xilinx_zynq.c >>> @@ -24,7 +24,7 @@ >>> #include "hw/block/flash.h" >>> #include "sysemu/block-backend.h" >>> #include "hw/loader.h" >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> #include "qemu/error-report.h" >>> >>> #define NUM_SPI_FLASHES 4 >>> diff --git a/hw/arm/z2.c b/hw/arm/z2.c >>> index b44eb76..c82fe2c 100644 >>> --- a/hw/arm/z2.c >>> +++ b/hw/arm/z2.c >>> @@ -16,7 +16,7 @@ >>> #include "hw/arm/arm.h" >>> #include "hw/devices.h" >>> #include "hw/i2c/i2c.h" >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> #include "hw/boards.h" >>> #include "sysemu/sysemu.h" >>> #include "hw/block/flash.h" >>> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c >>> index efc43dd..44830c7 100644 >>> --- a/hw/block/m25p80.c >>> +++ b/hw/block/m25p80.c >>> @@ -24,7 +24,7 @@ >>> #include "hw/hw.h" >>> #include "sysemu/block-backend.h" >>> #include "sysemu/blockdev.h" >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> >>> #ifndef M25P80_ERR_DEBUG >>> #define M25P80_ERR_DEBUG 0 >>> diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c >>> index 3f35369..cb82317 100644 >>> --- a/hw/display/ads7846.c >>> +++ b/hw/display/ads7846.c >>> @@ -10,7 +10,7 @@ >>> * GNU GPL, version 2 or (at your option) any later version. >>> */ >>> >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> #include "ui/console.h" >>> >>> typedef struct { >>> diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c >>> index 9727007..7545da8 100644 >>> --- a/hw/display/ssd0323.c >>> +++ b/hw/display/ssd0323.c >>> @@ -10,7 +10,7 @@ >>> /* The controller can support a variety of different displays, but we only >>> implement one. Most of the commends relating to brightness and geometry >>> setup are ignored. */ >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> #include "ui/console.h" >>> >>> //#define DEBUG_SSD0323 1 >>> diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c >>> index 462060f..5366cec 100644 >>> --- a/hw/microblaze/petalogix_ml605_mmu.c >>> +++ b/hw/microblaze/petalogix_ml605_mmu.c >>> @@ -35,7 +35,7 @@ >>> #include "sysemu/block-backend.h" >>> #include "hw/char/serial.h" >>> #include "exec/address-spaces.h" >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> >>> #include "boot.h" >>> >>> diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c >>> index bef3651..d619d61 100644 >>> --- a/hw/misc/max111x.c >>> +++ b/hw/misc/max111x.c >>> @@ -10,7 +10,7 @@ >>> * GNU GPL, version 2 or (at your option) any later version. >>> */ >>> >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> >>> typedef struct { >>> SSISlave parent_obj; >>> diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c >>> index e4b2d4f..4fe00fd 100644 >>> --- a/hw/sd/ssi-sd.c >>> +++ b/hw/sd/ssi-sd.c >>> @@ -12,7 +12,7 @@ >>> >>> #include "sysemu/block-backend.h" >>> #include "sysemu/blockdev.h" >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> #include "hw/sd.h" >>> >>> //#define DEBUG_SSI_SD 1 >>> diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c >>> index 61d568f..0bbf633 100644 >>> --- a/hw/ssi/pl022.c >>> +++ b/hw/ssi/pl022.c >>> @@ -8,7 +8,7 @@ >>> */ >>> >>> #include "hw/sysbus.h" >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> >>> //#define DEBUG_PL022 1 >>> >>> diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c >>> index 2aab79b..a0f57c0 100644 >>> --- a/hw/ssi/ssi.c >>> +++ b/hw/ssi/ssi.c >>> @@ -12,7 +12,7 @@ >>> * GNU GPL, version 2 or (at your option) any later version. >>> */ >>> >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> >>> struct SSIBus { >>> BusState parent_obj; >>> diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c >>> index 620573c..94bb2a7 100644 >>> --- a/hw/ssi/xilinx_spi.c >>> +++ b/hw/ssi/xilinx_spi.c >>> @@ -29,7 +29,7 @@ >>> #include "qemu/log.h" >>> #include "qemu/fifo8.h" >>> >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> >>> #ifdef XILINX_SPI_ERR_DEBUG >>> #define DB_PRINT(...) do { \ >>> diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c >>> index 0910f54..e9471ff 100644 >>> --- a/hw/ssi/xilinx_spips.c >>> +++ b/hw/ssi/xilinx_spips.c >>> @@ -27,7 +27,7 @@ >>> #include "hw/ptimer.h" >>> #include "qemu/log.h" >>> #include "qemu/fifo8.h" >>> -#include "hw/ssi.h" >>> +#include "hw/ssi/ssi.h" >>> #include "qemu/bitops.h" >>> >>> #ifndef XILINX_SPIPS_ERR_DEBUG >>> diff --git a/include/hw/ssi.h b/include/hw/ssi.h >>> deleted file mode 100644 >>> index df0f838..0000000 >>> --- a/include/hw/ssi.h >>> +++ /dev/null >>> @@ -1,94 +0,0 @@ >>> -/* QEMU Synchronous Serial Interface support. */ >>> - >>> -/* In principle SSI is a point-point interface. As such the qemu >>> - implementation has a single slave device on a "bus". >>> - However it is fairly common for boards to have multiple slaves >>> - connected to a single master, and select devices with an external >>> - chip select. This is implemented in qemu by having an explicit mux device. >>> - It is assumed that master and slave are both using the same transfer width. >>> - */ >>> - >>> -#ifndef QEMU_SSI_H >>> -#define QEMU_SSI_H >>> - >>> -#include "hw/qdev.h" >>> - >>> -typedef struct SSISlave SSISlave; >>> - >>> -#define TYPE_SSI_SLAVE "ssi-slave" >>> -#define SSI_SLAVE(obj) \ >>> - OBJECT_CHECK(SSISlave, (obj), TYPE_SSI_SLAVE) >>> -#define SSI_SLAVE_CLASS(klass) \ >>> - OBJECT_CLASS_CHECK(SSISlaveClass, (klass), TYPE_SSI_SLAVE) >>> -#define SSI_SLAVE_GET_CLASS(obj) \ >>> - OBJECT_GET_CLASS(SSISlaveClass, (obj), TYPE_SSI_SLAVE) >>> - >>> -#define SSI_GPIO_CS "ssi-gpio-cs" >>> - >>> -typedef enum { >>> - SSI_CS_NONE = 0, >>> - SSI_CS_LOW, >>> - SSI_CS_HIGH, >>> -} SSICSMode; >>> - >>> -/* Slave devices. */ >>> -typedef struct SSISlaveClass { >>> - DeviceClass parent_class; >>> - >>> - int (*init)(SSISlave *dev); >>> - >>> - /* if you have standard or no CS behaviour, just override transfer. >>> - * This is called when the device cs is active (true by default). >>> - */ >>> - uint32_t (*transfer)(SSISlave *dev, uint32_t val); >>> - /* called when the CS line changes. Optional, devices only need to implement >>> - * this if they have side effects associated with the cs line (beyond >>> - * tristating the txrx lines). >>> - */ >>> - int (*set_cs)(SSISlave *dev, bool select); >>> - /* define whether or not CS exists and is active low/high */ >>> - SSICSMode cs_polarity; >>> - >>> - /* if you have non-standard CS behaviour override this to take control >>> - * of the CS behaviour at the device level. transfer, set_cs, and >>> - * cs_polarity are unused if this is overwritten. Transfer_raw will >>> - * always be called for the device for every txrx access to the parent bus >>> - */ >>> - uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val); >>> -} SSISlaveClass; >>> - >>> -struct SSISlave { >>> - DeviceState parent_obj; >>> - >>> - /* Chip select state */ >>> - bool cs; >>> -}; >>> - >>> -#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) >>> - >>> -extern const VMStateDescription vmstate_ssi_slave; >>> - >>> -#define VMSTATE_SSI_SLAVE(_field, _state) { \ >>> - .name = (stringify(_field)), \ >>> - .size = sizeof(SSISlave), \ >>> - .vmsd = &vmstate_ssi_slave, \ >>> - .flags = VMS_STRUCT, \ >>> - .offset = vmstate_offset_value(_state, _field, SSISlave), \ >>> -} >>> - >>> -DeviceState *ssi_create_slave(SSIBus *bus, const char *name); >>> -DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name); >>> - >>> -/* Master interface. */ >>> -SSIBus *ssi_create_bus(DeviceState *parent, const char *name); >>> - >>> -uint32_t ssi_transfer(SSIBus *bus, uint32_t val); >>> - >>> -/* Automatically connect all children nodes a spi controller as slaves */ >>> -void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_lines, >>> - SSIBus *bus); >>> - >>> -/* max111x.c */ >>> -void max111x_set_input(DeviceState *dev, int line, uint8_t value); >>> - >>> -#endif >>> diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h >>> new file mode 100644 >>> index 0000000..4a0a539 >>> --- /dev/null >>> +++ b/include/hw/ssi/ssi.h >>> @@ -0,0 +1,96 @@ >>> +/* QEMU Synchronous Serial Interface support. */ >>> + >>> +/* In principle SSI is a point-point interface. As such the qemu >>> + implementation has a single slave device on a "bus". >>> + However it is fairly common for boards to have multiple slaves >>> + connected to a single master, and select devices with an external >>> + chip select. This is implemented in qemu by having an explicit mux device. >>> + It is assumed that master and slave are both using the same transfer width. >>> + */ >>> + >>> +#ifndef QEMU_SSI_H >>> +#define QEMU_SSI_H >>> + >>> +#include "hw/qdev.h" >>> + >>> +typedef struct SSISlave SSISlave; >>> +typedef struct SSISlaveClass SSISlaveClass; >>> +typedef enum SSICSMode SSICSMode; >>> + >>> +#define TYPE_SSI_SLAVE "ssi-slave" >>> +#define SSI_SLAVE(obj) \ >>> + OBJECT_CHECK(SSISlave, (obj), TYPE_SSI_SLAVE) >>> +#define SSI_SLAVE_CLASS(klass) \ >>> + OBJECT_CLASS_CHECK(SSISlaveClass, (klass), TYPE_SSI_SLAVE) >>> +#define SSI_SLAVE_GET_CLASS(obj) \ >>> + OBJECT_GET_CLASS(SSISlaveClass, (obj), TYPE_SSI_SLAVE) >>> + >>> +#define SSI_GPIO_CS "ssi-gpio-cs" >>> + >>> +enum SSICSMode { >>> + SSI_CS_NONE = 0, >>> + SSI_CS_LOW, >>> + SSI_CS_HIGH, >>> +}; >>> + >>> +/* Slave devices. */ >>> +struct SSISlaveClass { >>> + DeviceClass parent_class; >>> + >>> + int (*init)(SSISlave *dev); >>> + >>> + /* if you have standard or no CS behaviour, just override transfer. >>> + * This is called when the device cs is active (true by default). >>> + */ >>> + uint32_t (*transfer)(SSISlave *dev, uint32_t val); >>> + /* called when the CS line changes. Optional, devices only need to implement >>> + * this if they have side effects associated with the cs line (beyond >>> + * tristating the txrx lines). >>> + */ >>> + int (*set_cs)(SSISlave *dev, bool select); >>> + /* define whether or not CS exists and is active low/high */ >>> + SSICSMode cs_polarity; >>> + >>> + /* if you have non-standard CS behaviour override this to take control >>> + * of the CS behaviour at the device level. transfer, set_cs, and >>> + * cs_polarity are unused if this is overwritten. Transfer_raw will >>> + * always be called for the device for every txrx access to the parent bus >>> + */ >>> + uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val); >>> +}; >>> + >>> +struct SSISlave { >>> + DeviceState parent_obj; >>> + >>> + /* Chip select state */ >>> + bool cs; >>> +}; >>> + >>> +#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) >>> + >>> +extern const VMStateDescription vmstate_ssi_slave; >>> + >>> +#define VMSTATE_SSI_SLAVE(_field, _state) { \ >>> + .name = (stringify(_field)), \ >>> + .size = sizeof(SSISlave), \ >>> + .vmsd = &vmstate_ssi_slave, \ >>> + .flags = VMS_STRUCT, \ >>> + .offset = vmstate_offset_value(_state, _field, SSISlave), \ >>> +} >>> + >>> +DeviceState *ssi_create_slave(SSIBus *bus, const char *name); >>> +DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name); >>> + >>> +/* Master interface. */ >>> +SSIBus *ssi_create_bus(DeviceState *parent, const char *name); >>> + >>> +uint32_t ssi_transfer(SSIBus *bus, uint32_t val); >>> + >>> +/* Automatically connect all children nodes a spi controller as slaves */ >>> +void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_lines, >>> + SSIBus *bus); >>> + >>> +/* max111x.c */ >>> +void max111x_set_input(DeviceState *dev, int line, uint8_t value); >>> + >>> +#endif >>> -- >>> 1.9.1 >>> >> ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/3] ssi: Move ssi.h into a seperate directory 2015-10-01 17:39 ` Peter Crosthwaite @ 2015-10-02 21:29 ` Alistair Francis 0 siblings, 0 replies; 13+ messages in thread From: Alistair Francis @ 2015-10-02 21:29 UTC (permalink / raw) To: Peter Crosthwaite Cc: Edgar Iglesias, Peter Maydell, Edgar E. Iglesias, qemu-devel@nongnu.org Developers, Alistair Francis On Thu, Oct 1, 2015 at 10:39 AM, Peter Crosthwaite <crosthwaitepeter@gmail.com> wrote: > On Thu, Oct 1, 2015 at 10:19 AM, Alistair Francis > <alistair.francis@xilinx.com> wrote: >> On Wed, Sep 30, 2015 at 2:06 PM, Peter Crosthwaite >> <crosthwaitepeter@gmail.com> wrote: >>> On Tue, Sep 29, 2015 at 4:03 PM, Alistair Francis >>> <alistair.francis@xilinx.com> wrote: >>>> Move the ssi.h include file into the ssi directory. >>>> >>>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> >>>> --- >>>> >>>> hw/arm/pxa2xx.c | 2 +- >>>> hw/arm/spitz.c | 2 +- >>>> hw/arm/stellaris.c | 2 +- >>>> hw/arm/strongarm.c | 2 +- >>>> hw/arm/tosa.c | 2 +- >>>> hw/arm/xilinx_zynq.c | 2 +- >>>> hw/arm/z2.c | 2 +- >>>> hw/block/m25p80.c | 2 +- >>>> hw/display/ads7846.c | 2 +- >>>> hw/display/ssd0323.c | 2 +- >>>> hw/microblaze/petalogix_ml605_mmu.c | 2 +- >>>> hw/misc/max111x.c | 2 +- >>>> hw/sd/ssi-sd.c | 2 +- >>>> hw/ssi/pl022.c | 2 +- >>>> hw/ssi/ssi.c | 2 +- >>>> hw/ssi/xilinx_spi.c | 2 +- >>>> hw/ssi/xilinx_spips.c | 2 +- >>>> include/hw/ssi.h | 94 ------------------------------------ >>>> include/hw/ssi/ssi.h | 96 +++++++++++++++++++++++++++++++++++++ >>> >>> Curious as to why git didn't pick this up as a rename (I think it >>> should handle small diffs in the renaming). Do you have rename >>> detection turned on? >> >> I do have rename detection turned on. I think the reason it didn't is >> because I tiddied up the code a little bit when I moved it. Checkpatch >> was reproting errors on the struct typedeffs so I had to change that. >> > > Can we do it in two steps and take the hit on the checkpatch fails on > P1? Checkpatch fails are acceptable for pure mass-code movements. > There is also probably some way to set your rename detction to higher > level that should pick it up. I managed to change the rename detection (-M for git format-patch) and now the diff passes checkpatch and indicates a rename. Thanks, Alistair > > Regards, > Peter > >> Thanks, >> >> Alistair >> >>> >>> Regards, >>> Peter >>> >>>> 19 files changed, 113 insertions(+), 111 deletions(-) >>>> delete mode 100644 include/hw/ssi.h >>>> create mode 100644 include/hw/ssi/ssi.h >>>> >>>> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c >>>> index 164260a..534c06f 100644 >>>> --- a/hw/arm/pxa2xx.c >>>> +++ b/hw/arm/pxa2xx.c >>>> @@ -12,7 +12,7 @@ >>>> #include "sysemu/sysemu.h" >>>> #include "hw/char/serial.h" >>>> #include "hw/i2c/i2c.h" >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> #include "sysemu/char.h" >>>> #include "sysemu/block-backend.h" >>>> #include "sysemu/blockdev.h" >>>> diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c >>>> index 2af03be..c9405af 100644 >>>> --- a/hw/arm/spitz.c >>>> +++ b/hw/arm/spitz.c >>>> @@ -16,7 +16,7 @@ >>>> #include "sysemu/sysemu.h" >>>> #include "hw/pcmcia.h" >>>> #include "hw/i2c/i2c.h" >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> #include "hw/block/flash.h" >>>> #include "qemu/timer.h" >>>> #include "hw/devices.h" >>>> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c >>>> index 3d6486f..c785e90 100644 >>>> --- a/hw/arm/stellaris.c >>>> +++ b/hw/arm/stellaris.c >>>> @@ -8,7 +8,7 @@ >>>> */ >>>> >>>> #include "hw/sysbus.h" >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> #include "hw/arm/arm.h" >>>> #include "hw/devices.h" >>>> #include "qemu/timer.h" >>>> diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c >>>> index 9624ecb..4d2ba02 100644 >>>> --- a/hw/arm/strongarm.c >>>> +++ b/hw/arm/strongarm.c >>>> @@ -34,7 +34,7 @@ >>>> #include "hw/arm/arm.h" >>>> #include "sysemu/char.h" >>>> #include "sysemu/sysemu.h" >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> >>>> //#define DEBUG >>>> >>>> diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c >>>> index 51d0b89..6b210a6 100644 >>>> --- a/hw/arm/tosa.c >>>> +++ b/hw/arm/tosa.c >>>> @@ -19,7 +19,7 @@ >>>> #include "hw/pcmcia.h" >>>> #include "hw/boards.h" >>>> #include "hw/i2c/i2c.h" >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> #include "sysemu/block-backend.h" >>>> #include "hw/sysbus.h" >>>> #include "exec/address-spaces.h" >>>> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c >>>> index 9f89483..9db9602 100644 >>>> --- a/hw/arm/xilinx_zynq.c >>>> +++ b/hw/arm/xilinx_zynq.c >>>> @@ -24,7 +24,7 @@ >>>> #include "hw/block/flash.h" >>>> #include "sysemu/block-backend.h" >>>> #include "hw/loader.h" >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> #include "qemu/error-report.h" >>>> >>>> #define NUM_SPI_FLASHES 4 >>>> diff --git a/hw/arm/z2.c b/hw/arm/z2.c >>>> index b44eb76..c82fe2c 100644 >>>> --- a/hw/arm/z2.c >>>> +++ b/hw/arm/z2.c >>>> @@ -16,7 +16,7 @@ >>>> #include "hw/arm/arm.h" >>>> #include "hw/devices.h" >>>> #include "hw/i2c/i2c.h" >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> #include "hw/boards.h" >>>> #include "sysemu/sysemu.h" >>>> #include "hw/block/flash.h" >>>> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c >>>> index efc43dd..44830c7 100644 >>>> --- a/hw/block/m25p80.c >>>> +++ b/hw/block/m25p80.c >>>> @@ -24,7 +24,7 @@ >>>> #include "hw/hw.h" >>>> #include "sysemu/block-backend.h" >>>> #include "sysemu/blockdev.h" >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> >>>> #ifndef M25P80_ERR_DEBUG >>>> #define M25P80_ERR_DEBUG 0 >>>> diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c >>>> index 3f35369..cb82317 100644 >>>> --- a/hw/display/ads7846.c >>>> +++ b/hw/display/ads7846.c >>>> @@ -10,7 +10,7 @@ >>>> * GNU GPL, version 2 or (at your option) any later version. >>>> */ >>>> >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> #include "ui/console.h" >>>> >>>> typedef struct { >>>> diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c >>>> index 9727007..7545da8 100644 >>>> --- a/hw/display/ssd0323.c >>>> +++ b/hw/display/ssd0323.c >>>> @@ -10,7 +10,7 @@ >>>> /* The controller can support a variety of different displays, but we only >>>> implement one. Most of the commends relating to brightness and geometry >>>> setup are ignored. */ >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> #include "ui/console.h" >>>> >>>> //#define DEBUG_SSD0323 1 >>>> diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c >>>> index 462060f..5366cec 100644 >>>> --- a/hw/microblaze/petalogix_ml605_mmu.c >>>> +++ b/hw/microblaze/petalogix_ml605_mmu.c >>>> @@ -35,7 +35,7 @@ >>>> #include "sysemu/block-backend.h" >>>> #include "hw/char/serial.h" >>>> #include "exec/address-spaces.h" >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> >>>> #include "boot.h" >>>> >>>> diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c >>>> index bef3651..d619d61 100644 >>>> --- a/hw/misc/max111x.c >>>> +++ b/hw/misc/max111x.c >>>> @@ -10,7 +10,7 @@ >>>> * GNU GPL, version 2 or (at your option) any later version. >>>> */ >>>> >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> >>>> typedef struct { >>>> SSISlave parent_obj; >>>> diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c >>>> index e4b2d4f..4fe00fd 100644 >>>> --- a/hw/sd/ssi-sd.c >>>> +++ b/hw/sd/ssi-sd.c >>>> @@ -12,7 +12,7 @@ >>>> >>>> #include "sysemu/block-backend.h" >>>> #include "sysemu/blockdev.h" >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> #include "hw/sd.h" >>>> >>>> //#define DEBUG_SSI_SD 1 >>>> diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c >>>> index 61d568f..0bbf633 100644 >>>> --- a/hw/ssi/pl022.c >>>> +++ b/hw/ssi/pl022.c >>>> @@ -8,7 +8,7 @@ >>>> */ >>>> >>>> #include "hw/sysbus.h" >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> >>>> //#define DEBUG_PL022 1 >>>> >>>> diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c >>>> index 2aab79b..a0f57c0 100644 >>>> --- a/hw/ssi/ssi.c >>>> +++ b/hw/ssi/ssi.c >>>> @@ -12,7 +12,7 @@ >>>> * GNU GPL, version 2 or (at your option) any later version. >>>> */ >>>> >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> >>>> struct SSIBus { >>>> BusState parent_obj; >>>> diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c >>>> index 620573c..94bb2a7 100644 >>>> --- a/hw/ssi/xilinx_spi.c >>>> +++ b/hw/ssi/xilinx_spi.c >>>> @@ -29,7 +29,7 @@ >>>> #include "qemu/log.h" >>>> #include "qemu/fifo8.h" >>>> >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> >>>> #ifdef XILINX_SPI_ERR_DEBUG >>>> #define DB_PRINT(...) do { \ >>>> diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c >>>> index 0910f54..e9471ff 100644 >>>> --- a/hw/ssi/xilinx_spips.c >>>> +++ b/hw/ssi/xilinx_spips.c >>>> @@ -27,7 +27,7 @@ >>>> #include "hw/ptimer.h" >>>> #include "qemu/log.h" >>>> #include "qemu/fifo8.h" >>>> -#include "hw/ssi.h" >>>> +#include "hw/ssi/ssi.h" >>>> #include "qemu/bitops.h" >>>> >>>> #ifndef XILINX_SPIPS_ERR_DEBUG >>>> diff --git a/include/hw/ssi.h b/include/hw/ssi.h >>>> deleted file mode 100644 >>>> index df0f838..0000000 >>>> --- a/include/hw/ssi.h >>>> +++ /dev/null >>>> @@ -1,94 +0,0 @@ >>>> -/* QEMU Synchronous Serial Interface support. */ >>>> - >>>> -/* In principle SSI is a point-point interface. As such the qemu >>>> - implementation has a single slave device on a "bus". >>>> - However it is fairly common for boards to have multiple slaves >>>> - connected to a single master, and select devices with an external >>>> - chip select. This is implemented in qemu by having an explicit mux device. >>>> - It is assumed that master and slave are both using the same transfer width. >>>> - */ >>>> - >>>> -#ifndef QEMU_SSI_H >>>> -#define QEMU_SSI_H >>>> - >>>> -#include "hw/qdev.h" >>>> - >>>> -typedef struct SSISlave SSISlave; >>>> - >>>> -#define TYPE_SSI_SLAVE "ssi-slave" >>>> -#define SSI_SLAVE(obj) \ >>>> - OBJECT_CHECK(SSISlave, (obj), TYPE_SSI_SLAVE) >>>> -#define SSI_SLAVE_CLASS(klass) \ >>>> - OBJECT_CLASS_CHECK(SSISlaveClass, (klass), TYPE_SSI_SLAVE) >>>> -#define SSI_SLAVE_GET_CLASS(obj) \ >>>> - OBJECT_GET_CLASS(SSISlaveClass, (obj), TYPE_SSI_SLAVE) >>>> - >>>> -#define SSI_GPIO_CS "ssi-gpio-cs" >>>> - >>>> -typedef enum { >>>> - SSI_CS_NONE = 0, >>>> - SSI_CS_LOW, >>>> - SSI_CS_HIGH, >>>> -} SSICSMode; >>>> - >>>> -/* Slave devices. */ >>>> -typedef struct SSISlaveClass { >>>> - DeviceClass parent_class; >>>> - >>>> - int (*init)(SSISlave *dev); >>>> - >>>> - /* if you have standard or no CS behaviour, just override transfer. >>>> - * This is called when the device cs is active (true by default). >>>> - */ >>>> - uint32_t (*transfer)(SSISlave *dev, uint32_t val); >>>> - /* called when the CS line changes. Optional, devices only need to implement >>>> - * this if they have side effects associated with the cs line (beyond >>>> - * tristating the txrx lines). >>>> - */ >>>> - int (*set_cs)(SSISlave *dev, bool select); >>>> - /* define whether or not CS exists and is active low/high */ >>>> - SSICSMode cs_polarity; >>>> - >>>> - /* if you have non-standard CS behaviour override this to take control >>>> - * of the CS behaviour at the device level. transfer, set_cs, and >>>> - * cs_polarity are unused if this is overwritten. Transfer_raw will >>>> - * always be called for the device for every txrx access to the parent bus >>>> - */ >>>> - uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val); >>>> -} SSISlaveClass; >>>> - >>>> -struct SSISlave { >>>> - DeviceState parent_obj; >>>> - >>>> - /* Chip select state */ >>>> - bool cs; >>>> -}; >>>> - >>>> -#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) >>>> - >>>> -extern const VMStateDescription vmstate_ssi_slave; >>>> - >>>> -#define VMSTATE_SSI_SLAVE(_field, _state) { \ >>>> - .name = (stringify(_field)), \ >>>> - .size = sizeof(SSISlave), \ >>>> - .vmsd = &vmstate_ssi_slave, \ >>>> - .flags = VMS_STRUCT, \ >>>> - .offset = vmstate_offset_value(_state, _field, SSISlave), \ >>>> -} >>>> - >>>> -DeviceState *ssi_create_slave(SSIBus *bus, const char *name); >>>> -DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name); >>>> - >>>> -/* Master interface. */ >>>> -SSIBus *ssi_create_bus(DeviceState *parent, const char *name); >>>> - >>>> -uint32_t ssi_transfer(SSIBus *bus, uint32_t val); >>>> - >>>> -/* Automatically connect all children nodes a spi controller as slaves */ >>>> -void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_lines, >>>> - SSIBus *bus); >>>> - >>>> -/* max111x.c */ >>>> -void max111x_set_input(DeviceState *dev, int line, uint8_t value); >>>> - >>>> -#endif >>>> diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h >>>> new file mode 100644 >>>> index 0000000..4a0a539 >>>> --- /dev/null >>>> +++ b/include/hw/ssi/ssi.h >>>> @@ -0,0 +1,96 @@ >>>> +/* QEMU Synchronous Serial Interface support. */ >>>> + >>>> +/* In principle SSI is a point-point interface. As such the qemu >>>> + implementation has a single slave device on a "bus". >>>> + However it is fairly common for boards to have multiple slaves >>>> + connected to a single master, and select devices with an external >>>> + chip select. This is implemented in qemu by having an explicit mux device. >>>> + It is assumed that master and slave are both using the same transfer width. >>>> + */ >>>> + >>>> +#ifndef QEMU_SSI_H >>>> +#define QEMU_SSI_H >>>> + >>>> +#include "hw/qdev.h" >>>> + >>>> +typedef struct SSISlave SSISlave; >>>> +typedef struct SSISlaveClass SSISlaveClass; >>>> +typedef enum SSICSMode SSICSMode; >>>> + >>>> +#define TYPE_SSI_SLAVE "ssi-slave" >>>> +#define SSI_SLAVE(obj) \ >>>> + OBJECT_CHECK(SSISlave, (obj), TYPE_SSI_SLAVE) >>>> +#define SSI_SLAVE_CLASS(klass) \ >>>> + OBJECT_CLASS_CHECK(SSISlaveClass, (klass), TYPE_SSI_SLAVE) >>>> +#define SSI_SLAVE_GET_CLASS(obj) \ >>>> + OBJECT_GET_CLASS(SSISlaveClass, (obj), TYPE_SSI_SLAVE) >>>> + >>>> +#define SSI_GPIO_CS "ssi-gpio-cs" >>>> + >>>> +enum SSICSMode { >>>> + SSI_CS_NONE = 0, >>>> + SSI_CS_LOW, >>>> + SSI_CS_HIGH, >>>> +}; >>>> + >>>> +/* Slave devices. */ >>>> +struct SSISlaveClass { >>>> + DeviceClass parent_class; >>>> + >>>> + int (*init)(SSISlave *dev); >>>> + >>>> + /* if you have standard or no CS behaviour, just override transfer. >>>> + * This is called when the device cs is active (true by default). >>>> + */ >>>> + uint32_t (*transfer)(SSISlave *dev, uint32_t val); >>>> + /* called when the CS line changes. Optional, devices only need to implement >>>> + * this if they have side effects associated with the cs line (beyond >>>> + * tristating the txrx lines). >>>> + */ >>>> + int (*set_cs)(SSISlave *dev, bool select); >>>> + /* define whether or not CS exists and is active low/high */ >>>> + SSICSMode cs_polarity; >>>> + >>>> + /* if you have non-standard CS behaviour override this to take control >>>> + * of the CS behaviour at the device level. transfer, set_cs, and >>>> + * cs_polarity are unused if this is overwritten. Transfer_raw will >>>> + * always be called for the device for every txrx access to the parent bus >>>> + */ >>>> + uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val); >>>> +}; >>>> + >>>> +struct SSISlave { >>>> + DeviceState parent_obj; >>>> + >>>> + /* Chip select state */ >>>> + bool cs; >>>> +}; >>>> + >>>> +#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) >>>> + >>>> +extern const VMStateDescription vmstate_ssi_slave; >>>> + >>>> +#define VMSTATE_SSI_SLAVE(_field, _state) { \ >>>> + .name = (stringify(_field)), \ >>>> + .size = sizeof(SSISlave), \ >>>> + .vmsd = &vmstate_ssi_slave, \ >>>> + .flags = VMS_STRUCT, \ >>>> + .offset = vmstate_offset_value(_state, _field, SSISlave), \ >>>> +} >>>> + >>>> +DeviceState *ssi_create_slave(SSIBus *bus, const char *name); >>>> +DeviceState *ssi_create_slave_no_init(SSIBus *bus, const char *name); >>>> + >>>> +/* Master interface. */ >>>> +SSIBus *ssi_create_bus(DeviceState *parent, const char *name); >>>> + >>>> +uint32_t ssi_transfer(SSIBus *bus, uint32_t val); >>>> + >>>> +/* Automatically connect all children nodes a spi controller as slaves */ >>>> +void ssi_auto_connect_slaves(DeviceState *parent, qemu_irq *cs_lines, >>>> + SSIBus *bus); >>>> + >>>> +/* max111x.c */ >>>> +void max111x_set_input(DeviceState *dev, int line, uint8_t value); >>>> + >>>> +#endif >>>> -- >>>> 1.9.1 >>>> >>> > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH v1 2/3] xilinx_spips: Seperate the state struct into a header 2015-09-29 23:03 [Qemu-devel] [PATCH v1 0/3] Connect the SPI devices to ZynqMP Alistair Francis 2015-09-29 23:03 ` [Qemu-devel] [PATCH v1 1/3] ssi: Move ssi.h into a seperate directory Alistair Francis @ 2015-09-29 23:03 ` Alistair Francis 2015-09-30 21:10 ` Peter Crosthwaite [not found] ` <8bb979aa8ed92d7ee31f2625fa161699d4424268.1443567485.git.alistair.francis@xilinx.com> 2015-10-01 11:31 ` [Qemu-devel] [PATCH v1 0/3] Connect the SPI devices to ZynqMP Andrea Bolognani 3 siblings, 1 reply; 13+ messages in thread From: Alistair Francis @ 2015-09-29 23:03 UTC (permalink / raw) To: qemu-devel Cc: edgar.iglesias, peter.maydell, crosthwaitepeter, edgar.iglesias, alistair.francis Seperate out the XilinxSPIPS struct into a seperate header file. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> --- hw/ssi/xilinx_spips.c | 104 +------------------------------- include/hw/ssi/xilinx_spips.h | 134 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 135 insertions(+), 103 deletions(-) create mode 100644 include/hw/ssi/xilinx_spips.h diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index e9471ff..417c581 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -26,9 +26,8 @@ #include "sysemu/sysemu.h" #include "hw/ptimer.h" #include "qemu/log.h" -#include "qemu/fifo8.h" -#include "hw/ssi/ssi.h" #include "qemu/bitops.h" +#include "hw/ssi/xilinx_spips.h" #ifndef XILINX_SPIPS_ERR_DEBUG #define XILINX_SPIPS_ERR_DEBUG 0 @@ -41,70 +40,6 @@ } \ } while (0); -/* config register */ -#define R_CONFIG (0x00 / 4) -#define IFMODE (1U << 31) -#define ENDIAN (1 << 26) -#define MODEFAIL_GEN_EN (1 << 17) -#define MAN_START_COM (1 << 16) -#define MAN_START_EN (1 << 15) -#define MANUAL_CS (1 << 14) -#define CS (0xF << 10) -#define CS_SHIFT (10) -#define PERI_SEL (1 << 9) -#define REF_CLK (1 << 8) -#define FIFO_WIDTH (3 << 6) -#define BAUD_RATE_DIV (7 << 3) -#define CLK_PH (1 << 2) -#define CLK_POL (1 << 1) -#define MODE_SEL (1 << 0) -#define R_CONFIG_RSVD (0x7bf40000) - -/* interrupt mechanism */ -#define R_INTR_STATUS (0x04 / 4) -#define R_INTR_EN (0x08 / 4) -#define R_INTR_DIS (0x0C / 4) -#define R_INTR_MASK (0x10 / 4) -#define IXR_TX_FIFO_UNDERFLOW (1 << 6) -#define IXR_RX_FIFO_FULL (1 << 5) -#define IXR_RX_FIFO_NOT_EMPTY (1 << 4) -#define IXR_TX_FIFO_FULL (1 << 3) -#define IXR_TX_FIFO_NOT_FULL (1 << 2) -#define IXR_TX_FIFO_MODE_FAIL (1 << 1) -#define IXR_RX_FIFO_OVERFLOW (1 << 0) -#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) - -#define R_EN (0x14 / 4) -#define R_DELAY (0x18 / 4) -#define R_TX_DATA (0x1C / 4) -#define R_RX_DATA (0x20 / 4) -#define R_SLAVE_IDLE_COUNT (0x24 / 4) -#define R_TX_THRES (0x28 / 4) -#define R_RX_THRES (0x2C / 4) -#define R_TXD1 (0x80 / 4) -#define R_TXD2 (0x84 / 4) -#define R_TXD3 (0x88 / 4) - -#define R_LQSPI_CFG (0xa0 / 4) -#define R_LQSPI_CFG_RESET 0x03A002EB -#define LQSPI_CFG_LQ_MODE (1U << 31) -#define LQSPI_CFG_TWO_MEM (1 << 30) -#define LQSPI_CFG_SEP_BUS (1 << 30) -#define LQSPI_CFG_U_PAGE (1 << 28) -#define LQSPI_CFG_MODE_EN (1 << 25) -#define LQSPI_CFG_MODE_WIDTH 8 -#define LQSPI_CFG_MODE_SHIFT 16 -#define LQSPI_CFG_DUMMY_WIDTH 3 -#define LQSPI_CFG_DUMMY_SHIFT 8 -#define LQSPI_CFG_INST_CODE 0xFF - -#define R_LQSPI_STS (0xA4 / 4) -#define LQSPI_STS_WR_RECVD (1 << 1) - -#define R_MOD_ID (0xFC / 4) - -#define R_MAX (R_MOD_ID+1) - /* size of TXRX FIFOs */ #define RXFF_A 32 #define TXFF_A 32 @@ -135,30 +70,6 @@ typedef enum { } FlashCMD; typedef struct { - SysBusDevice parent_obj; - - MemoryRegion iomem; - MemoryRegion mmlqspi; - - qemu_irq irq; - int irqline; - - uint8_t num_cs; - uint8_t num_busses; - - uint8_t snoop_state; - qemu_irq *cs_lines; - SSIBus **spi; - - Fifo8 rx_fifo; - Fifo8 tx_fifo; - - uint8_t num_txrx_bytes; - - uint32_t regs[R_MAX]; -} XilinxSPIPS; - -typedef struct { XilinxSPIPS parent_obj; uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; @@ -174,19 +85,6 @@ typedef struct XilinxSPIPSClass { uint32_t tx_fifo_size; } XilinxSPIPSClass; -#define TYPE_XILINX_SPIPS "xlnx.ps7-spi" -#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" - -#define XILINX_SPIPS(obj) \ - OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) -#define XILINX_SPIPS_CLASS(klass) \ - OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS) -#define XILINX_SPIPS_GET_CLASS(obj) \ - OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS) - -#define XILINX_QSPIPS(obj) \ - OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) - static inline int num_effective_busses(XilinxSPIPS *s) { return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h new file mode 100644 index 0000000..31671ec --- /dev/null +++ b/include/hw/ssi/xilinx_spips.h @@ -0,0 +1,134 @@ +/* + * Header file for the Xilinx Zynq SPI controller + * + * Copyright (C) 2015 Xilinx Inc + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef XLNX_SPIPS_H +#define XLNX_SPIPS_H + +#include "hw/ssi/ssi.h" +#include "qemu/fifo8.h" + +typedef struct XilinxSPIPS XilinxSPIPS; + +/* config register */ +#define R_CONFIG (0x00 / 4) +#define IFMODE (1U << 31) +#define ENDIAN (1 << 26) +#define MODEFAIL_GEN_EN (1 << 17) +#define MAN_START_COM (1 << 16) +#define MAN_START_EN (1 << 15) +#define MANUAL_CS (1 << 14) +#define CS (0xF << 10) +#define CS_SHIFT (10) +#define PERI_SEL (1 << 9) +#define REF_CLK (1 << 8) +#define FIFO_WIDTH (3 << 6) +#define BAUD_RATE_DIV (7 << 3) +#define CLK_PH (1 << 2) +#define CLK_POL (1 << 1) +#define MODE_SEL (1 << 0) +#define R_CONFIG_RSVD (0x7bf40000) + +/* interrupt mechanism */ +#define R_INTR_STATUS (0x04 / 4) +#define R_INTR_EN (0x08 / 4) +#define R_INTR_DIS (0x0C / 4) +#define R_INTR_MASK (0x10 / 4) +#define IXR_TX_FIFO_UNDERFLOW (1 << 6) +#define IXR_RX_FIFO_FULL (1 << 5) +#define IXR_RX_FIFO_NOT_EMPTY (1 << 4) +#define IXR_TX_FIFO_FULL (1 << 3) +#define IXR_TX_FIFO_NOT_FULL (1 << 2) +#define IXR_TX_FIFO_MODE_FAIL (1 << 1) +#define IXR_RX_FIFO_OVERFLOW (1 << 0) +#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW << 1) - 1) + +#define R_EN (0x14 / 4) +#define R_DELAY (0x18 / 4) +#define R_TX_DATA (0x1C / 4) +#define R_RX_DATA (0x20 / 4) +#define R_SLAVE_IDLE_COUNT (0x24 / 4) +#define R_TX_THRES (0x28 / 4) +#define R_RX_THRES (0x2C / 4) +#define R_TXD1 (0x80 / 4) +#define R_TXD2 (0x84 / 4) +#define R_TXD3 (0x88 / 4) + +#define R_LQSPI_CFG (0xa0 / 4) +#define R_LQSPI_CFG_RESET 0x03A002EB +#define LQSPI_CFG_LQ_MODE (1U << 31) +#define LQSPI_CFG_TWO_MEM (1 << 30) +#define LQSPI_CFG_SEP_BUS (1 << 30) +#define LQSPI_CFG_U_PAGE (1 << 28) +#define LQSPI_CFG_MODE_EN (1 << 25) +#define LQSPI_CFG_MODE_WIDTH 8 +#define LQSPI_CFG_MODE_SHIFT 16 +#define LQSPI_CFG_DUMMY_WIDTH 3 +#define LQSPI_CFG_DUMMY_SHIFT 8 +#define LQSPI_CFG_INST_CODE 0xFF + +#define R_LQSPI_STS (0xA4 / 4) +#define LQSPI_STS_WR_RECVD (1 << 1) + +#define R_MOD_ID (0xFC / 4) + +#define R_MAX (R_MOD_ID + 1) + +struct XilinxSPIPS { + SysBusDevice parent_obj; + + MemoryRegion iomem; + MemoryRegion mmlqspi; + + qemu_irq irq; + int irqline; + + uint8_t num_cs; + uint8_t num_busses; + + uint8_t snoop_state; + qemu_irq *cs_lines; + SSIBus **spi; + + Fifo8 rx_fifo; + Fifo8 tx_fifo; + + uint8_t num_txrx_bytes; + + uint32_t regs[R_MAX]; +}; + +#define TYPE_XILINX_SPIPS "xlnx.ps7-spi" +#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" + +#define XILINX_SPIPS(obj) \ + OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) +#define XILINX_SPIPS_CLASS(klass) \ + OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS) +#define XILINX_SPIPS_GET_CLASS(obj) \ + OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS) + +#define XILINX_QSPIPS(obj) \ + OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) + +#endif /* XLNX_SPIPS_H */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v1 2/3] xilinx_spips: Seperate the state struct into a header 2015-09-29 23:03 ` [Qemu-devel] [PATCH v1 2/3] xilinx_spips: Seperate the state struct into a header Alistair Francis @ 2015-09-30 21:10 ` Peter Crosthwaite 2015-10-02 22:47 ` Alistair Francis 0 siblings, 1 reply; 13+ messages in thread From: Peter Crosthwaite @ 2015-09-30 21:10 UTC (permalink / raw) To: Alistair Francis Cc: Edgar Iglesias, Peter Maydell, qemu-devel@nongnu.org Developers, Edgar E. Iglesias On Tue, Sep 29, 2015 at 4:03 PM, Alistair Francis <alistair.francis@xilinx.com> wrote: > Seperate out the XilinxSPIPS struct into a seperate header > file. > > Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> > --- > > hw/ssi/xilinx_spips.c | 104 +------------------------------- > include/hw/ssi/xilinx_spips.h | 134 ++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 135 insertions(+), 103 deletions(-) > create mode 100644 include/hw/ssi/xilinx_spips.h > > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c > index e9471ff..417c581 100644 > --- a/hw/ssi/xilinx_spips.c > +++ b/hw/ssi/xilinx_spips.c > @@ -26,9 +26,8 @@ > #include "sysemu/sysemu.h" > #include "hw/ptimer.h" > #include "qemu/log.h" > -#include "qemu/fifo8.h" > -#include "hw/ssi/ssi.h" > #include "qemu/bitops.h" > +#include "hw/ssi/xilinx_spips.h" > > #ifndef XILINX_SPIPS_ERR_DEBUG > #define XILINX_SPIPS_ERR_DEBUG 0 > @@ -41,70 +40,6 @@ > } \ > } while (0); > > -/* config register */ > -#define R_CONFIG (0x00 / 4) > -#define IFMODE (1U << 31) > -#define ENDIAN (1 << 26) Some of these macro names are too generic for the global namespace. Until we have a proper solution on how to handle namespace collisions for programmers model macros, I suggest taking the bare minimum to the header (which is going to whatever is used for the struct def itself). Preface those defs with XLNX_SPIPS_ accordingly (if there are any - probably just R_MAX). Regards, Peter > -#define MODEFAIL_GEN_EN (1 << 17) > -#define MAN_START_COM (1 << 16) > -#define MAN_START_EN (1 << 15) > -#define MANUAL_CS (1 << 14) > -#define CS (0xF << 10) > -#define CS_SHIFT (10) > -#define PERI_SEL (1 << 9) > -#define REF_CLK (1 << 8) > -#define FIFO_WIDTH (3 << 6) > -#define BAUD_RATE_DIV (7 << 3) > -#define CLK_PH (1 << 2) > -#define CLK_POL (1 << 1) > -#define MODE_SEL (1 << 0) > -#define R_CONFIG_RSVD (0x7bf40000) > - > -/* interrupt mechanism */ > -#define R_INTR_STATUS (0x04 / 4) > -#define R_INTR_EN (0x08 / 4) > -#define R_INTR_DIS (0x0C / 4) > -#define R_INTR_MASK (0x10 / 4) > -#define IXR_TX_FIFO_UNDERFLOW (1 << 6) > -#define IXR_RX_FIFO_FULL (1 << 5) > -#define IXR_RX_FIFO_NOT_EMPTY (1 << 4) > -#define IXR_TX_FIFO_FULL (1 << 3) > -#define IXR_TX_FIFO_NOT_FULL (1 << 2) > -#define IXR_TX_FIFO_MODE_FAIL (1 << 1) > -#define IXR_RX_FIFO_OVERFLOW (1 << 0) > -#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) > - > -#define R_EN (0x14 / 4) > -#define R_DELAY (0x18 / 4) > -#define R_TX_DATA (0x1C / 4) > -#define R_RX_DATA (0x20 / 4) > -#define R_SLAVE_IDLE_COUNT (0x24 / 4) > -#define R_TX_THRES (0x28 / 4) > -#define R_RX_THRES (0x2C / 4) > -#define R_TXD1 (0x80 / 4) > -#define R_TXD2 (0x84 / 4) > -#define R_TXD3 (0x88 / 4) > - > -#define R_LQSPI_CFG (0xa0 / 4) > -#define R_LQSPI_CFG_RESET 0x03A002EB > -#define LQSPI_CFG_LQ_MODE (1U << 31) > -#define LQSPI_CFG_TWO_MEM (1 << 30) > -#define LQSPI_CFG_SEP_BUS (1 << 30) > -#define LQSPI_CFG_U_PAGE (1 << 28) > -#define LQSPI_CFG_MODE_EN (1 << 25) > -#define LQSPI_CFG_MODE_WIDTH 8 > -#define LQSPI_CFG_MODE_SHIFT 16 > -#define LQSPI_CFG_DUMMY_WIDTH 3 > -#define LQSPI_CFG_DUMMY_SHIFT 8 > -#define LQSPI_CFG_INST_CODE 0xFF > - > -#define R_LQSPI_STS (0xA4 / 4) > -#define LQSPI_STS_WR_RECVD (1 << 1) > - > -#define R_MOD_ID (0xFC / 4) > - > -#define R_MAX (R_MOD_ID+1) > - > /* size of TXRX FIFOs */ > #define RXFF_A 32 > #define TXFF_A 32 > @@ -135,30 +70,6 @@ typedef enum { > } FlashCMD; > > typedef struct { > - SysBusDevice parent_obj; > - > - MemoryRegion iomem; > - MemoryRegion mmlqspi; > - > - qemu_irq irq; > - int irqline; > - > - uint8_t num_cs; > - uint8_t num_busses; > - > - uint8_t snoop_state; > - qemu_irq *cs_lines; > - SSIBus **spi; > - > - Fifo8 rx_fifo; > - Fifo8 tx_fifo; > - > - uint8_t num_txrx_bytes; > - > - uint32_t regs[R_MAX]; > -} XilinxSPIPS; > - > -typedef struct { > XilinxSPIPS parent_obj; > > uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; > @@ -174,19 +85,6 @@ typedef struct XilinxSPIPSClass { > uint32_t tx_fifo_size; > } XilinxSPIPSClass; > > -#define TYPE_XILINX_SPIPS "xlnx.ps7-spi" > -#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" > - > -#define XILINX_SPIPS(obj) \ > - OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) > -#define XILINX_SPIPS_CLASS(klass) \ > - OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS) > -#define XILINX_SPIPS_GET_CLASS(obj) \ > - OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS) > - > -#define XILINX_QSPIPS(obj) \ > - OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) > - > static inline int num_effective_busses(XilinxSPIPS *s) > { > return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && > diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h > new file mode 100644 > index 0000000..31671ec > --- /dev/null > +++ b/include/hw/ssi/xilinx_spips.h > @@ -0,0 +1,134 @@ > +/* > + * Header file for the Xilinx Zynq SPI controller > + * > + * Copyright (C) 2015 Xilinx Inc > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#ifndef XLNX_SPIPS_H > +#define XLNX_SPIPS_H > + > +#include "hw/ssi/ssi.h" > +#include "qemu/fifo8.h" > + > +typedef struct XilinxSPIPS XilinxSPIPS; > + > +/* config register */ > +#define R_CONFIG (0x00 / 4) > +#define IFMODE (1U << 31) > +#define ENDIAN (1 << 26) > +#define MODEFAIL_GEN_EN (1 << 17) > +#define MAN_START_COM (1 << 16) > +#define MAN_START_EN (1 << 15) > +#define MANUAL_CS (1 << 14) > +#define CS (0xF << 10) > +#define CS_SHIFT (10) > +#define PERI_SEL (1 << 9) > +#define REF_CLK (1 << 8) > +#define FIFO_WIDTH (3 << 6) > +#define BAUD_RATE_DIV (7 << 3) > +#define CLK_PH (1 << 2) > +#define CLK_POL (1 << 1) > +#define MODE_SEL (1 << 0) > +#define R_CONFIG_RSVD (0x7bf40000) > + > +/* interrupt mechanism */ > +#define R_INTR_STATUS (0x04 / 4) > +#define R_INTR_EN (0x08 / 4) > +#define R_INTR_DIS (0x0C / 4) > +#define R_INTR_MASK (0x10 / 4) > +#define IXR_TX_FIFO_UNDERFLOW (1 << 6) > +#define IXR_RX_FIFO_FULL (1 << 5) > +#define IXR_RX_FIFO_NOT_EMPTY (1 << 4) > +#define IXR_TX_FIFO_FULL (1 << 3) > +#define IXR_TX_FIFO_NOT_FULL (1 << 2) > +#define IXR_TX_FIFO_MODE_FAIL (1 << 1) > +#define IXR_RX_FIFO_OVERFLOW (1 << 0) > +#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW << 1) - 1) > + > +#define R_EN (0x14 / 4) > +#define R_DELAY (0x18 / 4) > +#define R_TX_DATA (0x1C / 4) > +#define R_RX_DATA (0x20 / 4) > +#define R_SLAVE_IDLE_COUNT (0x24 / 4) > +#define R_TX_THRES (0x28 / 4) > +#define R_RX_THRES (0x2C / 4) > +#define R_TXD1 (0x80 / 4) > +#define R_TXD2 (0x84 / 4) > +#define R_TXD3 (0x88 / 4) > + > +#define R_LQSPI_CFG (0xa0 / 4) > +#define R_LQSPI_CFG_RESET 0x03A002EB > +#define LQSPI_CFG_LQ_MODE (1U << 31) > +#define LQSPI_CFG_TWO_MEM (1 << 30) > +#define LQSPI_CFG_SEP_BUS (1 << 30) > +#define LQSPI_CFG_U_PAGE (1 << 28) > +#define LQSPI_CFG_MODE_EN (1 << 25) > +#define LQSPI_CFG_MODE_WIDTH 8 > +#define LQSPI_CFG_MODE_SHIFT 16 > +#define LQSPI_CFG_DUMMY_WIDTH 3 > +#define LQSPI_CFG_DUMMY_SHIFT 8 > +#define LQSPI_CFG_INST_CODE 0xFF > + > +#define R_LQSPI_STS (0xA4 / 4) > +#define LQSPI_STS_WR_RECVD (1 << 1) > + > +#define R_MOD_ID (0xFC / 4) > + > +#define R_MAX (R_MOD_ID + 1) > + > +struct XilinxSPIPS { > + SysBusDevice parent_obj; > + > + MemoryRegion iomem; > + MemoryRegion mmlqspi; > + > + qemu_irq irq; > + int irqline; > + > + uint8_t num_cs; > + uint8_t num_busses; > + > + uint8_t snoop_state; > + qemu_irq *cs_lines; > + SSIBus **spi; > + > + Fifo8 rx_fifo; > + Fifo8 tx_fifo; > + > + uint8_t num_txrx_bytes; > + > + uint32_t regs[R_MAX]; > +}; > + > +#define TYPE_XILINX_SPIPS "xlnx.ps7-spi" > +#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" > + > +#define XILINX_SPIPS(obj) \ > + OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) > +#define XILINX_SPIPS_CLASS(klass) \ > + OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS) > +#define XILINX_SPIPS_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS) > + > +#define XILINX_QSPIPS(obj) \ > + OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) > + > +#endif /* XLNX_SPIPS_H */ > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v1 2/3] xilinx_spips: Seperate the state struct into a header 2015-09-30 21:10 ` Peter Crosthwaite @ 2015-10-02 22:47 ` Alistair Francis 0 siblings, 0 replies; 13+ messages in thread From: Alistair Francis @ 2015-10-02 22:47 UTC (permalink / raw) To: Peter Crosthwaite Cc: Edgar Iglesias, Peter Maydell, Edgar E. Iglesias, qemu-devel@nongnu.org Developers, Alistair Francis On Wed, Sep 30, 2015 at 2:10 PM, Peter Crosthwaite <crosthwaitepeter@gmail.com> wrote: > On Tue, Sep 29, 2015 at 4:03 PM, Alistair Francis > <alistair.francis@xilinx.com> wrote: >> Seperate out the XilinxSPIPS struct into a seperate header >> file. >> >> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> >> --- >> >> hw/ssi/xilinx_spips.c | 104 +------------------------------- >> include/hw/ssi/xilinx_spips.h | 134 ++++++++++++++++++++++++++++++++++++++++++ >> 2 files changed, 135 insertions(+), 103 deletions(-) >> create mode 100644 include/hw/ssi/xilinx_spips.h >> >> diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c >> index e9471ff..417c581 100644 >> --- a/hw/ssi/xilinx_spips.c >> +++ b/hw/ssi/xilinx_spips.c >> @@ -26,9 +26,8 @@ >> #include "sysemu/sysemu.h" >> #include "hw/ptimer.h" >> #include "qemu/log.h" >> -#include "qemu/fifo8.h" >> -#include "hw/ssi/ssi.h" >> #include "qemu/bitops.h" >> +#include "hw/ssi/xilinx_spips.h" >> >> #ifndef XILINX_SPIPS_ERR_DEBUG >> #define XILINX_SPIPS_ERR_DEBUG 0 >> @@ -41,70 +40,6 @@ >> } \ >> } while (0); >> >> -/* config register */ >> -#define R_CONFIG (0x00 / 4) >> -#define IFMODE (1U << 31) >> -#define ENDIAN (1 << 26) > > Some of these macro names are too generic for the global namespace. > Until we have a proper solution on how to handle namespace collisions > for programmers model macros, I suggest taking the bare minimum to the > header (which is going to whatever is used for the struct def itself). > Preface those defs with XLNX_SPIPS_ accordingly (if there are any - > probably just R_MAX). Ok, I have just taken the bare minimum into the header. The only problem with that is now some of the macros have XLNX_SPIS_* and some don't, but that isn't really a big problem. Thanks, Alistair > > Regards, > Peter > >> -#define MODEFAIL_GEN_EN (1 << 17) >> -#define MAN_START_COM (1 << 16) >> -#define MAN_START_EN (1 << 15) >> -#define MANUAL_CS (1 << 14) >> -#define CS (0xF << 10) >> -#define CS_SHIFT (10) >> -#define PERI_SEL (1 << 9) >> -#define REF_CLK (1 << 8) >> -#define FIFO_WIDTH (3 << 6) >> -#define BAUD_RATE_DIV (7 << 3) >> -#define CLK_PH (1 << 2) >> -#define CLK_POL (1 << 1) >> -#define MODE_SEL (1 << 0) >> -#define R_CONFIG_RSVD (0x7bf40000) >> - >> -/* interrupt mechanism */ >> -#define R_INTR_STATUS (0x04 / 4) >> -#define R_INTR_EN (0x08 / 4) >> -#define R_INTR_DIS (0x0C / 4) >> -#define R_INTR_MASK (0x10 / 4) >> -#define IXR_TX_FIFO_UNDERFLOW (1 << 6) >> -#define IXR_RX_FIFO_FULL (1 << 5) >> -#define IXR_RX_FIFO_NOT_EMPTY (1 << 4) >> -#define IXR_TX_FIFO_FULL (1 << 3) >> -#define IXR_TX_FIFO_NOT_FULL (1 << 2) >> -#define IXR_TX_FIFO_MODE_FAIL (1 << 1) >> -#define IXR_RX_FIFO_OVERFLOW (1 << 0) >> -#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) >> - >> -#define R_EN (0x14 / 4) >> -#define R_DELAY (0x18 / 4) >> -#define R_TX_DATA (0x1C / 4) >> -#define R_RX_DATA (0x20 / 4) >> -#define R_SLAVE_IDLE_COUNT (0x24 / 4) >> -#define R_TX_THRES (0x28 / 4) >> -#define R_RX_THRES (0x2C / 4) >> -#define R_TXD1 (0x80 / 4) >> -#define R_TXD2 (0x84 / 4) >> -#define R_TXD3 (0x88 / 4) >> - >> -#define R_LQSPI_CFG (0xa0 / 4) >> -#define R_LQSPI_CFG_RESET 0x03A002EB >> -#define LQSPI_CFG_LQ_MODE (1U << 31) >> -#define LQSPI_CFG_TWO_MEM (1 << 30) >> -#define LQSPI_CFG_SEP_BUS (1 << 30) >> -#define LQSPI_CFG_U_PAGE (1 << 28) >> -#define LQSPI_CFG_MODE_EN (1 << 25) >> -#define LQSPI_CFG_MODE_WIDTH 8 >> -#define LQSPI_CFG_MODE_SHIFT 16 >> -#define LQSPI_CFG_DUMMY_WIDTH 3 >> -#define LQSPI_CFG_DUMMY_SHIFT 8 >> -#define LQSPI_CFG_INST_CODE 0xFF >> - >> -#define R_LQSPI_STS (0xA4 / 4) >> -#define LQSPI_STS_WR_RECVD (1 << 1) >> - >> -#define R_MOD_ID (0xFC / 4) >> - >> -#define R_MAX (R_MOD_ID+1) >> - >> /* size of TXRX FIFOs */ >> #define RXFF_A 32 >> #define TXFF_A 32 >> @@ -135,30 +70,6 @@ typedef enum { >> } FlashCMD; >> >> typedef struct { >> - SysBusDevice parent_obj; >> - >> - MemoryRegion iomem; >> - MemoryRegion mmlqspi; >> - >> - qemu_irq irq; >> - int irqline; >> - >> - uint8_t num_cs; >> - uint8_t num_busses; >> - >> - uint8_t snoop_state; >> - qemu_irq *cs_lines; >> - SSIBus **spi; >> - >> - Fifo8 rx_fifo; >> - Fifo8 tx_fifo; >> - >> - uint8_t num_txrx_bytes; >> - >> - uint32_t regs[R_MAX]; >> -} XilinxSPIPS; >> - >> -typedef struct { >> XilinxSPIPS parent_obj; >> >> uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; >> @@ -174,19 +85,6 @@ typedef struct XilinxSPIPSClass { >> uint32_t tx_fifo_size; >> } XilinxSPIPSClass; >> >> -#define TYPE_XILINX_SPIPS "xlnx.ps7-spi" >> -#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" >> - >> -#define XILINX_SPIPS(obj) \ >> - OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) >> -#define XILINX_SPIPS_CLASS(klass) \ >> - OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS) >> -#define XILINX_SPIPS_GET_CLASS(obj) \ >> - OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS) >> - >> -#define XILINX_QSPIPS(obj) \ >> - OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) >> - >> static inline int num_effective_busses(XilinxSPIPS *s) >> { >> return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && >> diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h >> new file mode 100644 >> index 0000000..31671ec >> --- /dev/null >> +++ b/include/hw/ssi/xilinx_spips.h >> @@ -0,0 +1,134 @@ >> +/* >> + * Header file for the Xilinx Zynq SPI controller >> + * >> + * Copyright (C) 2015 Xilinx Inc >> + * >> + * Permission is hereby granted, free of charge, to any person obtaining a copy >> + * of this software and associated documentation files (the "Software"), to deal >> + * in the Software without restriction, including without limitation the rights >> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell >> + * copies of the Software, and to permit persons to whom the Software is >> + * furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice shall be included in >> + * all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, >> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN >> + * THE SOFTWARE. >> + */ >> + >> +#ifndef XLNX_SPIPS_H >> +#define XLNX_SPIPS_H >> + >> +#include "hw/ssi/ssi.h" >> +#include "qemu/fifo8.h" >> + >> +typedef struct XilinxSPIPS XilinxSPIPS; >> + >> +/* config register */ >> +#define R_CONFIG (0x00 / 4) >> +#define IFMODE (1U << 31) >> +#define ENDIAN (1 << 26) >> +#define MODEFAIL_GEN_EN (1 << 17) >> +#define MAN_START_COM (1 << 16) >> +#define MAN_START_EN (1 << 15) >> +#define MANUAL_CS (1 << 14) >> +#define CS (0xF << 10) >> +#define CS_SHIFT (10) >> +#define PERI_SEL (1 << 9) >> +#define REF_CLK (1 << 8) >> +#define FIFO_WIDTH (3 << 6) >> +#define BAUD_RATE_DIV (7 << 3) >> +#define CLK_PH (1 << 2) >> +#define CLK_POL (1 << 1) >> +#define MODE_SEL (1 << 0) >> +#define R_CONFIG_RSVD (0x7bf40000) >> + >> +/* interrupt mechanism */ >> +#define R_INTR_STATUS (0x04 / 4) >> +#define R_INTR_EN (0x08 / 4) >> +#define R_INTR_DIS (0x0C / 4) >> +#define R_INTR_MASK (0x10 / 4) >> +#define IXR_TX_FIFO_UNDERFLOW (1 << 6) >> +#define IXR_RX_FIFO_FULL (1 << 5) >> +#define IXR_RX_FIFO_NOT_EMPTY (1 << 4) >> +#define IXR_TX_FIFO_FULL (1 << 3) >> +#define IXR_TX_FIFO_NOT_FULL (1 << 2) >> +#define IXR_TX_FIFO_MODE_FAIL (1 << 1) >> +#define IXR_RX_FIFO_OVERFLOW (1 << 0) >> +#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW << 1) - 1) >> + >> +#define R_EN (0x14 / 4) >> +#define R_DELAY (0x18 / 4) >> +#define R_TX_DATA (0x1C / 4) >> +#define R_RX_DATA (0x20 / 4) >> +#define R_SLAVE_IDLE_COUNT (0x24 / 4) >> +#define R_TX_THRES (0x28 / 4) >> +#define R_RX_THRES (0x2C / 4) >> +#define R_TXD1 (0x80 / 4) >> +#define R_TXD2 (0x84 / 4) >> +#define R_TXD3 (0x88 / 4) >> + >> +#define R_LQSPI_CFG (0xa0 / 4) >> +#define R_LQSPI_CFG_RESET 0x03A002EB >> +#define LQSPI_CFG_LQ_MODE (1U << 31) >> +#define LQSPI_CFG_TWO_MEM (1 << 30) >> +#define LQSPI_CFG_SEP_BUS (1 << 30) >> +#define LQSPI_CFG_U_PAGE (1 << 28) >> +#define LQSPI_CFG_MODE_EN (1 << 25) >> +#define LQSPI_CFG_MODE_WIDTH 8 >> +#define LQSPI_CFG_MODE_SHIFT 16 >> +#define LQSPI_CFG_DUMMY_WIDTH 3 >> +#define LQSPI_CFG_DUMMY_SHIFT 8 >> +#define LQSPI_CFG_INST_CODE 0xFF >> + >> +#define R_LQSPI_STS (0xA4 / 4) >> +#define LQSPI_STS_WR_RECVD (1 << 1) >> + >> +#define R_MOD_ID (0xFC / 4) >> + >> +#define R_MAX (R_MOD_ID + 1) >> + >> +struct XilinxSPIPS { >> + SysBusDevice parent_obj; >> + >> + MemoryRegion iomem; >> + MemoryRegion mmlqspi; >> + >> + qemu_irq irq; >> + int irqline; >> + >> + uint8_t num_cs; >> + uint8_t num_busses; >> + >> + uint8_t snoop_state; >> + qemu_irq *cs_lines; >> + SSIBus **spi; >> + >> + Fifo8 rx_fifo; >> + Fifo8 tx_fifo; >> + >> + uint8_t num_txrx_bytes; >> + >> + uint32_t regs[R_MAX]; >> +}; >> + >> +#define TYPE_XILINX_SPIPS "xlnx.ps7-spi" >> +#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" >> + >> +#define XILINX_SPIPS(obj) \ >> + OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) >> +#define XILINX_SPIPS_CLASS(klass) \ >> + OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS) >> +#define XILINX_SPIPS_GET_CLASS(obj) \ >> + OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS) >> + >> +#define XILINX_QSPIPS(obj) \ >> + OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) >> + >> +#endif /* XLNX_SPIPS_H */ >> -- >> 1.9.1 >> > ^ permalink raw reply [flat|nested] 13+ messages in thread
[parent not found: <8bb979aa8ed92d7ee31f2625fa161699d4424268.1443567485.git.alistair.francis@xilinx.com>]
* Re: [Qemu-devel] [PATCH v1 3/3] xlnx-zynqmp: Connect the SPI devices [not found] ` <8bb979aa8ed92d7ee31f2625fa161699d4424268.1443567485.git.alistair.francis@xilinx.com> @ 2015-09-30 21:15 ` Peter Crosthwaite 2015-10-07 21:35 ` Alistair Francis 0 siblings, 1 reply; 13+ messages in thread From: Peter Crosthwaite @ 2015-09-30 21:15 UTC (permalink / raw) To: Alistair Francis Cc: Edgar Iglesias, Peter Maydell, qemu-devel@nongnu.org Developers, Edgar E. Iglesias On Tue, Sep 29, 2015 at 4:03 PM, Alistair Francis <alistair.francis@xilinx.com> wrote: > Connect the Xilinx SPI device to the ZynqMP model. > > Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> > --- > > hw/arm/xlnx-zynqmp.c | 46 +++++++++++++++++++++++++++++++++++++++++++- > include/hw/arm/xlnx-zynqmp.h | 4 ++++ > 2 files changed, 49 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c > index a9097f9..4b8d095 100644 > --- a/hw/arm/xlnx-zynqmp.c > +++ b/hw/arm/xlnx-zynqmp.c > @@ -48,6 +48,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { > 21, 22, > }; > > +static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { > + 0xFF040000, 0xFF050000, > +}; > + > +static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { > + 19, 20, > +}; > + > typedef struct XlnxZynqMPGICRegion { > int region_index; > uint32_t address; > @@ -97,13 +105,19 @@ static void xlnx_zynqmp_init(Object *obj) > > object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI); > qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default()); > + > + for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { > + object_initialize(&s->spi[i], sizeof(s->spi[i]), > + TYPE_XILINX_SPIPS); > + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); > + } > } > > static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) > { > XlnxZynqMPState *s = XLNX_ZYNQMP(dev); > MemoryRegion *system_memory = get_system_memory(); > - uint8_t i; > + uint8_t i, j; > const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; > qemu_irq gic_spi[GIC_NUM_SPI_INTR]; > Error *err = NULL; > @@ -258,6 +272,36 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) > > sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); > sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); > + > + for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { > + SSIBus *spi_bus; > + char bus_name[6]; > + > + object_property_set_int(OBJECT(&s->spi[i]), XLNX_ZYNQMP_NUM_SPIS, > + "num-busses", &error_abort); > + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); > + if (err) { > + error_propagate(errp, err); > + return; > + } > + > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, > + gic_spi[spi_intr[i]]); > + > + snprintf(bus_name, 6, "spi%d", i); > + spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->spi[i]), bus_name); > + > + for (j = 0; j < XLNX_ZYNQMP_NUM_SPI_FLASHES; ++j) { > + DeviceState *flash_dev = ssi_create_slave(spi_bus, "m25p80"); Are they actual m25p80's or are you trying to be generic? "M25P80' is overloaded, often used to mean the greater family of SPI flashes while also being a specific part. In this usage, it means the specific part. M25P80 is a very old part. This should however be on the machine level. The bus needs to be connected to the SoC object as a child bus, and the board level creates the flashes (ep108). Regards, Peter > + qemu_irq cs_line = qdev_get_gpio_in_named(flash_dev, > + SSI_GPIO_CS, 0); > + > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), > + i * XLNX_ZYNQMP_NUM_SPI_FLASHES + j, > + cs_line); > + } > + } > } > > static Property xlnx_zynqmp_props[] = { > diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h > index 4005a99..6d1d2a9 100644 > --- a/include/hw/arm/xlnx-zynqmp.h > +++ b/include/hw/arm/xlnx-zynqmp.h > @@ -24,6 +24,7 @@ > #include "hw/char/cadence_uart.h" > #include "hw/ide/pci.h" > #include "hw/ide/ahci.h" > +#include "hw/ssi/xilinx_spips.h" > > #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" > #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ > @@ -33,6 +34,8 @@ > #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 > #define XLNX_ZYNQMP_NUM_GEMS 4 > #define XLNX_ZYNQMP_NUM_UARTS 2 > +#define XLNX_ZYNQMP_NUM_SPIS 2 > +#define XLNX_ZYNQMP_NUM_SPI_FLASHES 4 > > #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 > #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 > @@ -63,6 +66,7 @@ typedef struct XlnxZynqMPState { > CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; > CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; > SysbusAHCIState sata; > + XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; > > char *boot_cpu; > ARMCPU *boot_cpu_ptr; > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v1 3/3] xlnx-zynqmp: Connect the SPI devices 2015-09-30 21:15 ` [Qemu-devel] [PATCH v1 3/3] xlnx-zynqmp: Connect the SPI devices Peter Crosthwaite @ 2015-10-07 21:35 ` Alistair Francis 0 siblings, 0 replies; 13+ messages in thread From: Alistair Francis @ 2015-10-07 21:35 UTC (permalink / raw) To: Peter Crosthwaite Cc: Edgar Iglesias, Peter Maydell, Edgar E. Iglesias, qemu-devel@nongnu.org Developers, Alistair Francis On Wed, Sep 30, 2015 at 2:15 PM, Peter Crosthwaite <crosthwaitepeter@gmail.com> wrote: > On Tue, Sep 29, 2015 at 4:03 PM, Alistair Francis > <alistair.francis@xilinx.com> wrote: >> Connect the Xilinx SPI device to the ZynqMP model. >> >> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> >> --- >> >> hw/arm/xlnx-zynqmp.c | 46 +++++++++++++++++++++++++++++++++++++++++++- >> include/hw/arm/xlnx-zynqmp.h | 4 ++++ >> 2 files changed, 49 insertions(+), 1 deletion(-) >> >> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c >> index a9097f9..4b8d095 100644 >> --- a/hw/arm/xlnx-zynqmp.c >> +++ b/hw/arm/xlnx-zynqmp.c >> @@ -48,6 +48,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { >> 21, 22, >> }; >> >> +static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = { >> + 0xFF040000, 0xFF050000, >> +}; >> + >> +static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = { >> + 19, 20, >> +}; >> + >> typedef struct XlnxZynqMPGICRegion { >> int region_index; >> uint32_t address; >> @@ -97,13 +105,19 @@ static void xlnx_zynqmp_init(Object *obj) >> >> object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI); >> qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default()); >> + >> + for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { >> + object_initialize(&s->spi[i], sizeof(s->spi[i]), >> + TYPE_XILINX_SPIPS); >> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); >> + } >> } >> >> static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) >> { >> XlnxZynqMPState *s = XLNX_ZYNQMP(dev); >> MemoryRegion *system_memory = get_system_memory(); >> - uint8_t i; >> + uint8_t i, j; >> const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; >> qemu_irq gic_spi[GIC_NUM_SPI_INTR]; >> Error *err = NULL; >> @@ -258,6 +272,36 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) >> >> sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR); >> sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]); >> + >> + for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) { >> + SSIBus *spi_bus; >> + char bus_name[6]; >> + >> + object_property_set_int(OBJECT(&s->spi[i]), XLNX_ZYNQMP_NUM_SPIS, >> + "num-busses", &error_abort); >> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); >> + if (err) { >> + error_propagate(errp, err); >> + return; >> + } >> + >> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]); >> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, >> + gic_spi[spi_intr[i]]); >> + >> + snprintf(bus_name, 6, "spi%d", i); >> + spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->spi[i]), bus_name); >> + >> + for (j = 0; j < XLNX_ZYNQMP_NUM_SPI_FLASHES; ++j) { >> + DeviceState *flash_dev = ssi_create_slave(spi_bus, "m25p80"); > > Are they actual m25p80's or are you trying to be generic? "M25P80' is > overloaded, often used to mean the greater family of SPI flashes while > also being a specific part. In this usage, it means the specific part. > M25P80 is a very old part. Good point, I'll update it with the actual part. > > This should however be on the machine level. The bus needs to be > connected to the SoC object as a child bus, and the board level > creates the flashes (ep108). Ok, fixed in v2. Thanks, Alistair > > Regards, > Peter > >> + qemu_irq cs_line = qdev_get_gpio_in_named(flash_dev, >> + SSI_GPIO_CS, 0); >> + >> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), >> + i * XLNX_ZYNQMP_NUM_SPI_FLASHES + j, >> + cs_line); >> + } >> + } >> } >> >> static Property xlnx_zynqmp_props[] = { >> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h >> index 4005a99..6d1d2a9 100644 >> --- a/include/hw/arm/xlnx-zynqmp.h >> +++ b/include/hw/arm/xlnx-zynqmp.h >> @@ -24,6 +24,7 @@ >> #include "hw/char/cadence_uart.h" >> #include "hw/ide/pci.h" >> #include "hw/ide/ahci.h" >> +#include "hw/ssi/xilinx_spips.h" >> >> #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" >> #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ >> @@ -33,6 +34,8 @@ >> #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 >> #define XLNX_ZYNQMP_NUM_GEMS 4 >> #define XLNX_ZYNQMP_NUM_UARTS 2 >> +#define XLNX_ZYNQMP_NUM_SPIS 2 >> +#define XLNX_ZYNQMP_NUM_SPI_FLASHES 4 >> >> #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 >> #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 >> @@ -63,6 +66,7 @@ typedef struct XlnxZynqMPState { >> CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; >> CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; >> SysbusAHCIState sata; >> + XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; >> >> char *boot_cpu; >> ARMCPU *boot_cpu_ptr; >> -- >> 1.9.1 >> > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/3] Connect the SPI devices to ZynqMP 2015-09-29 23:03 [Qemu-devel] [PATCH v1 0/3] Connect the SPI devices to ZynqMP Alistair Francis ` (2 preceding siblings ...) [not found] ` <8bb979aa8ed92d7ee31f2625fa161699d4424268.1443567485.git.alistair.francis@xilinx.com> @ 2015-10-01 11:31 ` Andrea Bolognani 2015-10-02 21:32 ` Alistair Francis 3 siblings, 1 reply; 13+ messages in thread From: Andrea Bolognani @ 2015-10-01 11:31 UTC (permalink / raw) To: Alistair Francis, qemu-devel On Tue, 2015-09-29 at 16:03 -0700, Alistair Francis wrote: > Connect the SPI devices to Xilinx's ZynqMP. > > I also need to make some changes to the actual SPI device to > imporove the fuctionality, but for the time being this works. > > Alistair Francis (3): > ssi: Move ssi.h into a seperate directory > xilinx_spips: Seperate the state struct into a header > xlnx-zynqmp: Connect the SPI devices s/eperate/eparate/g Cheers. -- Andrea Bolognani Software Engineer - Virtualization Team ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/3] Connect the SPI devices to ZynqMP 2015-10-01 11:31 ` [Qemu-devel] [PATCH v1 0/3] Connect the SPI devices to ZynqMP Andrea Bolognani @ 2015-10-02 21:32 ` Alistair Francis 0 siblings, 0 replies; 13+ messages in thread From: Alistair Francis @ 2015-10-02 21:32 UTC (permalink / raw) To: Andrea Bolognani; +Cc: qemu-devel@nongnu.org Developers, Alistair Francis On Thu, Oct 1, 2015 at 4:31 AM, Andrea Bolognani <abologna@redhat.com> wrote: > On Tue, 2015-09-29 at 16:03 -0700, Alistair Francis wrote: >> Connect the SPI devices to Xilinx's ZynqMP. >> >> I also need to make some changes to the actual SPI device to >> imporove the fuctionality, but for the time being this works. >> >> Alistair Francis (3): >> ssi: Move ssi.h into a seperate directory >> xilinx_spips: Seperate the state struct into a header >> xlnx-zynqmp: Connect the SPI devices > > s/eperate/eparate/g Good catch, fixed in version 2. Thanks, Alistair > > Cheers. > > -- > Andrea Bolognani > Software Engineer - Virtualization Team > > ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2015-10-07 21:51 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-09-29 23:03 [Qemu-devel] [PATCH v1 0/3] Connect the SPI devices to ZynqMP Alistair Francis
2015-09-29 23:03 ` [Qemu-devel] [PATCH v1 1/3] ssi: Move ssi.h into a seperate directory Alistair Francis
2015-09-30 21:06 ` Peter Crosthwaite
2015-10-01 17:19 ` Alistair Francis
2015-10-01 17:39 ` Peter Crosthwaite
2015-10-02 21:29 ` Alistair Francis
2015-09-29 23:03 ` [Qemu-devel] [PATCH v1 2/3] xilinx_spips: Seperate the state struct into a header Alistair Francis
2015-09-30 21:10 ` Peter Crosthwaite
2015-10-02 22:47 ` Alistair Francis
[not found] ` <8bb979aa8ed92d7ee31f2625fa161699d4424268.1443567485.git.alistair.francis@xilinx.com>
2015-09-30 21:15 ` [Qemu-devel] [PATCH v1 3/3] xlnx-zynqmp: Connect the SPI devices Peter Crosthwaite
2015-10-07 21:35 ` Alistair Francis
2015-10-01 11:31 ` [Qemu-devel] [PATCH v1 0/3] Connect the SPI devices to ZynqMP Andrea Bolognani
2015-10-02 21:32 ` Alistair Francis
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).