From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50226) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZkDIz-0005sa-T9 for qemu-devel@nongnu.org; Thu, 08 Oct 2015 11:40:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZkDIv-0005WI-TI for qemu-devel@nongnu.org; Thu, 08 Oct 2015 11:40:29 -0400 Received: from mail-qg0-x243.google.com ([2607:f8b0:400d:c04::243]:36048) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZkDIv-0005W8-Q6 for qemu-devel@nongnu.org; Thu, 08 Oct 2015 11:40:25 -0400 Received: by qget97 with SMTP id t97so5126167qge.3 for ; Thu, 08 Oct 2015 08:40:25 -0700 (PDT) From: Michael Davidsaver Date: Thu, 8 Oct 2015 11:40:00 -0400 Message-Id: Subject: [Qemu-devel] [PATCH] Exit on reset for armv7-m List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Michael Davidsaver Implement the SYSRESETREQ bit of the AIRCR register for armv7-m (ie. cortex-m3). A small patch to see if I have the submission process figured out. Michael Davidsaver (1): armv7-m: exit on external reset request hw/intc/armv7m_nvic.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.1.4