[Qemu-devel] [PATCH v1 0/4] AHCI patches + Allwinner SATA

[Qemu-devel] [PATCH v1 0/4] AHCI patches + Allwinner SATA

[Peter Crosthwaite]

This patch series adds bare-minimum Allwinner SATA support.

P1 is a trivial to help debug AHCI.

Changed since RFC:
Addressed Beniamino review.
Rebased to avoid bad deps (John Snow review)

Regards,
Peter


Peter Crosthwaite (4):
  ahci: Add some MMIO debug printfs
  ahci: split realize and init
  ahci: Add allwinner AHCI
  arm: allwinner-a10: Add SATA

 hw/arm/allwinner-a10.c         |  11 +++
 hw/ide/ahci.c                  | 152 +++++++++++++++++++++++++++++++++++------
 hw/ide/ahci.h                  |  19 +++++-
 hw/ide/ich.c                   |  10 ++-
 include/hw/arm/allwinner-a10.h |   4 ++
 include/qemu/typedefs.h        |   1 +
 6 files changed, 176 insertions(+), 21 deletions(-)

-- 
1.9.1

[Qemu-devel] [PATCH v1 1/4] ahci: Add some MMIO debug printfs

[Peter Crosthwaite]

These are useful for bringup of AHCI.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
---

 hw/ide/ahci.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 21f76ed..ed74253 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -378,17 +378,23 @@ static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size)
     int ofst = addr - aligned;
     uint64_t lo = ahci_mem_read_32(opaque, aligned);
     uint64_t hi;
+    uint64_t val;
 
     /* if < 8 byte read does not cross 4 byte boundary */
     if (ofst + size <= 4) {
-        return lo >> (ofst * 8);
+        val = lo >> (ofst * 8);
+    } else {
+        g_assert_cmpint(size, >, 1);
+
+        /* If the 64bit read is unaligned, we will produce undefined
+         * results. AHCI does not support unaligned 64bit reads. */
+        hi = ahci_mem_read_32(opaque, aligned + 4);
+        val = (hi << 32 | lo) >> (ofst * 8);
     }
-    g_assert_cmpint(size, >, 1);
 
-    /* If the 64bit read is unaligned, we will produce undefined
-     * results. AHCI does not support unaligned 64bit reads. */
-    hi = ahci_mem_read_32(opaque, aligned + 4);
-    return (hi << 32 | lo) >> (ofst * 8);
+    DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
+            addr, val, size);
+    return val;
 }
 
 
@@ -397,6 +403,9 @@ static void ahci_mem_write(void *opaque, hwaddr addr,
 {
     AHCIState *s = opaque;
 
+    DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
+            addr, val, size);
+
     /* Only aligned reads are allowed on AHCI */
     if (addr & 3) {
         fprintf(stderr, "ahci: Mis-aligned write to addr 0x"
-- 
1.9.1

[Qemu-devel] [PATCH v1 2/4] ahci: split realize and init

[Peter Crosthwaite]

Do the init level tasks asap and the realize later (mainly when
num_ports is available). This allows sub-class realize routines
to work with the device post-init.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
---

 hw/ide/ahci.c | 36 +++++++++++++++++++++++-------------
 hw/ide/ahci.h |  3 ++-
 hw/ide/ich.c  | 10 +++++++++-
 3 files changed, 34 insertions(+), 15 deletions(-)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index ed74253..5f41491 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -1436,24 +1436,26 @@ static const IDEDMAOps ahci_dma_ops = {
     .cmd_done = ahci_cmd_done,
 };
 
-void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
+void ahci_init(AHCIState *s, DeviceState *qdev)
 {
-    qemu_irq *irqs;
-    int i;
-
-    s->as = as;
-    s->ports = ports;
-    s->dev = g_new0(AHCIDevice, ports);
     s->container = qdev;
-    ahci_reg_init(s);
     /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
     memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s,
                           "ahci", AHCI_MEM_BAR_SIZE);
     memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s,
                           "ahci-idp", 32);
+}
 
-    irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
+void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
+{
+    qemu_irq *irqs;
+    int i;
 
+    s->as = as;
+    s->ports = ports;
+    s->dev = g_new0(AHCIDevice, ports);
+    ahci_reg_init(s);
+    irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
     for (i = 0; i < s->ports; i++) {
         AHCIDevice *ad = &s->dev[i];
 
@@ -1648,17 +1650,24 @@ static void sysbus_ahci_reset(DeviceState *dev)
     ahci_reset(&s->ahci);
 }
 
-static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
+static void sysbus_ahci_init(Object *obj)
 {
-    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
-    SysbusAHCIState *s = SYSBUS_AHCI(dev);
+    SysbusAHCIState *s = SYSBUS_AHCI(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 
-    ahci_init(&s->ahci, dev, &address_space_memory, s->num_ports);
+    ahci_init(&s->ahci, DEVICE(obj));
 
     sysbus_init_mmio(sbd, &s->ahci.mem);
     sysbus_init_irq(sbd, &s->ahci.irq);
 }
 
+static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
+{
+    SysbusAHCIState *s = SYSBUS_AHCI(dev);
+
+    ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports);
+}
+
 static Property sysbus_ahci_properties[] = {
     DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1),
     DEFINE_PROP_END_OF_LIST(),
@@ -1679,6 +1688,7 @@ static const TypeInfo sysbus_ahci_info = {
     .name          = TYPE_SYSBUS_AHCI,
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(SysbusAHCIState),
+    .instance_init = sysbus_ahci_init,
     .class_init    = sysbus_ahci_class_init,
 };
 
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index c9b3805..4ccaf5d 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -366,7 +366,8 @@ typedef struct SDBFIS {
     uint32_t payload;
 } QEMU_PACKED SDBFIS;
 
-void ahci_init(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);
+void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports);
+void ahci_init(AHCIState *s, DeviceState *qdev);
 void ahci_uninit(AHCIState *s);
 
 void ahci_reset(AHCIState *s);
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index 350c7f1..16925fa 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -97,6 +97,13 @@ static void pci_ich9_reset(DeviceState *dev)
     ahci_reset(&d->ahci);
 }
 
+static void pci_ich9_ahci_init(Object *obj)
+{
+    struct AHCIPCIState *d = ICH_AHCI(obj);
+
+    ahci_init(&d->ahci, DEVICE(obj));
+}
+
 static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
 {
     struct AHCIPCIState *d;
@@ -104,7 +111,7 @@ static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
     uint8_t *sata_cap;
     d = ICH_AHCI(dev);
 
-    ahci_init(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
+    ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
 
     pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
 
@@ -171,6 +178,7 @@ static const TypeInfo ich_ahci_info = {
     .name          = TYPE_ICH9_AHCI,
     .parent        = TYPE_PCI_DEVICE,
     .instance_size = sizeof(AHCIPCIState),
+    .instance_init = pci_ich9_ahci_init,
     .class_init    = ich_ahci_class_init,
 };
 
-- 
1.9.1

[Qemu-devel] [PATCH v1 3/4] ahci: Add allwinner AHCI

[Peter Crosthwaite]

Add a Sysbus AHCI subclass for the Allwinner AHCI. It has a few extra
vendor specific registers which are used for phy and power init.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
---
Changed since RFC:
Dropped un-needed macros (Beniamino)
Fixed VMSD section name (Beniamino)
Fixed commit message grammar.
Move typedef to typedefs.h

 hw/ide/ahci.c           | 95 +++++++++++++++++++++++++++++++++++++++++++++++++
 hw/ide/ahci.h           | 16 +++++++++
 include/qemu/typedefs.h |  1 +
 3 files changed, 112 insertions(+)

diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 5f41491..d872869 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -1692,9 +1692,104 @@ static const TypeInfo sysbus_ahci_info = {
     .class_init    = sysbus_ahci_class_init,
 };
 
+#define ALLWINNER_AHCI_BISTAFR    ((0xa0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_BISTCR     ((0xa4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_BISTFCTR   ((0xa8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_BISTSR     ((0xac - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_BISTDECR   ((0xb0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_DIAGNR0    ((0xb4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_DIAGNR1    ((0xb8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_OOBR       ((0xbc - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_PHYCS0R    ((0xc0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_PHYCS1R    ((0xc4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_PHYCS2R    ((0xc8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_TIMER1MS   ((0xe0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_GPARAM1R   ((0xe8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_GPARAM2R   ((0xec - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_PPARAMR    ((0xf0 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_TESTR      ((0xf4 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_VERSIONR   ((0xf8 - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_IDR        ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)
+#define ALLWINNER_AHCI_RWCR       ((0xfc - ALLWINNER_AHCI_MMIO_OFF) / 4)
+
+static uint64_t allwinner_ahci_mem_read(void *opaque, hwaddr addr,
+                                        unsigned size)
+{
+    AllwinnerAHCIState *a = opaque;
+    uint64_t val = a->regs[addr/4];
+
+    switch (addr / 4) {
+    case ALLWINNER_AHCI_PHYCS0R:
+        val |= 0x2 << 28;
+        break;
+    case ALLWINNER_AHCI_PHYCS2R:
+        val &= ~(0x1 << 24);
+        break;
+    }
+    DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
+            addr, val, size);
+    return  val;
+}
+
+static void allwinner_ahci_mem_write(void *opaque, hwaddr addr,
+                                     uint64_t val, unsigned size)
+{
+    AllwinnerAHCIState *a = opaque;
+
+    DPRINTF(-1, "addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 ", size=%d\n",
+            addr, val, size);
+    a->regs[addr/4] = val;
+}
+
+static const MemoryRegionOps allwinner_ahci_mem_ops = {
+    .read = allwinner_ahci_mem_read,
+    .write = allwinner_ahci_mem_write,
+    .valid.min_access_size = 4,
+    .valid.max_access_size = 4,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void allwinner_ahci_init(Object *obj)
+{
+    SysbusAHCIState *s = SYSBUS_AHCI(obj);
+    AllwinnerAHCIState *a = ALLWINNER_AHCI(obj);
+
+    memory_region_init_io(&a->mmio, OBJECT(obj), &allwinner_ahci_mem_ops, a,
+                          "allwinner-ahci", ALLWINNER_AHCI_MMIO_SIZE);
+    memory_region_add_subregion(&s->ahci.mem, ALLWINNER_AHCI_MMIO_OFF,
+                                &a->mmio);
+}
+
+static const VMStateDescription vmstate_allwinner_ahci = {
+    .name = "allwinner-ahci",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, AllwinnerAHCIState,
+                             ALLWINNER_AHCI_MMIO_SIZE/4),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void allwinner_ahci_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->vmsd = &vmstate_allwinner_ahci;
+}
+
+static const TypeInfo allwinner_ahci_info = {
+    .name          = TYPE_ALLWINNER_AHCI,
+    .parent        = TYPE_SYSBUS_AHCI,
+    .instance_size = sizeof(AllwinnerAHCIState),
+    .instance_init = allwinner_ahci_init,
+    .class_init    = allwinner_ahci_class_init,
+};
+
 static void sysbus_ahci_register_types(void)
 {
     type_register_static(&sysbus_ahci_info);
+    type_register_static(&allwinner_ahci_info);
 }
 
 type_init(sysbus_ahci_register_types)
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index 4ccaf5d..bc777ed 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -386,4 +386,20 @@ typedef struct SysbusAHCIState {
     uint32_t num_ports;
 } SysbusAHCIState;
 
+#define TYPE_ALLWINNER_AHCI "allwinner-ahci"
+#define ALLWINNER_AHCI(obj) OBJECT_CHECK(AllwinnerAHCIState, (obj), \
+                       TYPE_ALLWINNER_AHCI)
+
+#define ALLWINNER_AHCI_MMIO_OFF  0x80
+#define ALLWINNER_AHCI_MMIO_SIZE 0x80
+
+struct AllwinnerAHCIState {
+    /*< private >*/
+    SysbusAHCIState parent_obj;
+    /*< public >*/
+
+    MemoryRegion mmio;
+    uint32_t regs[ALLWINNER_AHCI_MMIO_SIZE/4];
+};
+
 #endif /* HW_IDE_AHCI_H */
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index d4a8f7a..a789f90 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -9,6 +9,7 @@ struct Monitor;
 typedef struct AdapterInfo AdapterInfo;
 typedef struct AddressSpace AddressSpace;
 typedef struct AioContext AioContext;
+typedef struct AllwinnerAHCIState AllwinnerAHCIState;
 typedef struct AudioState AudioState;
 typedef struct BlockBackend BlockBackend;
 typedef struct BlockDriverState BlockDriverState;
-- 
1.9.1

[Qemu-devel] [PATCH v1 4/4] arm: allwinner-a10: Add SATA

[Peter Crosthwaite]

Add the Allwinner A10 AHCI controller module to the SoC.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
---

 hw/arm/allwinner-a10.c         | 11 +++++++++++
 include/hw/arm/allwinner-a10.h |  4 ++++
 2 files changed, 15 insertions(+)

diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 43dc0a1..b0ca81c 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -39,6 +39,9 @@ static void aw_a10_init(Object *obj)
         qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
         qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
     }
+
+    object_initialize(&s->sata, sizeof(s->sata), TYPE_ALLWINNER_AHCI);
+    qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
 }
 
 static void aw_a10_realize(DeviceState *dev, Error **errp)
@@ -93,6 +96,14 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
     sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
 
+    object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
+
     /* FIXME use a qdev chardev prop instead of serial_hds[] */
     serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
                    115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index 01a189b..6b32a99 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -7,6 +7,8 @@
 #include "hw/timer/allwinner-a10-pit.h"
 #include "hw/intc/allwinner-a10-pic.h"
 #include "hw/net/allwinner_emac.h"
+#include "hw/ide/pci.h"
+#include "hw/ide/ahci.h"
 
 #include "sysemu/sysemu.h"
 #include "exec/address-spaces.h"
@@ -16,6 +18,7 @@
 #define AW_A10_PIT_REG_BASE     0x01c20c00
 #define AW_A10_UART0_REG_BASE   0x01c28000
 #define AW_A10_EMAC_BASE        0x01c0b000
+#define AW_A10_SATA_BASE        0x01c18000
 
 #define AW_A10_SDRAM_BASE       0x40000000
 
@@ -32,6 +35,7 @@ typedef struct AwA10State {
     AwA10PITState timer;
     AwA10PICState intc;
     AwEmacState emac;
+    AllwinnerAHCIState sata;
 } AwA10State;
 
 #define ALLWINNER_H_
-- 
1.9.1

Re: [Qemu-devel] [PATCH v1 0/4] AHCI patches + Allwinner SATA

[Peter Maydell]

On 27 October 2015 at 04:02, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> This patch series adds bare-minimum Allwinner SATA support.
>
> P1 is a trivial to help debug AHCI.
>
> Changed since RFC:
> Addressed Beniamino review.
> Rebased to avoid bad deps (John Snow review)
>
> Regards,
> Peter
>
>
> Peter Crosthwaite (4):
>   ahci: Add some MMIO debug printfs
>   ahci: split realize and init
>   ahci: Add allwinner AHCI
>   arm: allwinner-a10: Add SATA

Are you hoping for this to go in for 2.5? I think the RFC
made it onto the list before softfreeze...

thanks
-- PMM

Re: [Qemu-devel] [PATCH v1 0/4] AHCI patches + Allwinner SATA

[Peter Crosthwaite]

On Fri, Oct 30, 2015 at 2:28 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 27 October 2015 at 04:02, Peter Crosthwaite
> <crosthwaitepeter@gmail.com> wrote:
>> This patch series adds bare-minimum Allwinner SATA support.
>>
>> P1 is a trivial to help debug AHCI.
>>
>> Changed since RFC:
>> Addressed Beniamino review.
>> Rebased to avoid bad deps (John Snow review)
>>
>> Regards,
>> Peter
>>
>>
>> Peter Crosthwaite (4):
>>   ahci: Add some MMIO debug printfs
>>   ahci: split realize and init
>>   ahci: Add allwinner AHCI
>>   arm: allwinner-a10: Add SATA
>
> Are you hoping for this to go in for 2.5? I think the RFC
> made it onto the list before softfreeze...
>

Yes, Is John Snow doing another round before HF?

Regards,
Peter

> thanks
> -- PMM

Re: [Qemu-devel] [PATCH v1 0/4] AHCI patches + Allwinner SATA

[John Snow]

On 10/30/2015 05:33 PM, Peter Crosthwaite wrote:
> On Fri, Oct 30, 2015 at 2:28 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
>> On 27 October 2015 at 04:02, Peter Crosthwaite
>> <crosthwaitepeter@gmail.com> wrote:
>>> This patch series adds bare-minimum Allwinner SATA support.
>>>
>>> P1 is a trivial to help debug AHCI.
>>>
>>> Changed since RFC:
>>> Addressed Beniamino review.
>>> Rebased to avoid bad deps (John Snow review)
>>>
>>> Regards,
>>> Peter
>>>
>>>
>>> Peter Crosthwaite (4):
>>>   ahci: Add some MMIO debug printfs
>>>   ahci: split realize and init
>>>   ahci: Add allwinner AHCI
>>>   arm: allwinner-a10: Add SATA
>>
>> Are you hoping for this to go in for 2.5? I think the RFC
>> made it onto the list before softfreeze...
>>
> 
> Yes, Is John Snow doing another round before HF?
> 
> Regards,
> Peter
> 
>> thanks
>> -- PMM

Yes, I intend to help you with this for 2.5.

--js

Re: [Qemu-devel] [PATCH v1 0/4] AHCI patches + Allwinner SATA

[Peter Maydell]

On 30 October 2015 at 21:34, John Snow <jsnow@redhat.com> wrote:
>
>
> On 10/30/2015 05:33 PM, Peter Crosthwaite wrote:
>> On Fri, Oct 30, 2015 at 2:28 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
>>> On 27 October 2015 at 04:02, Peter Crosthwaite
>>> <crosthwaitepeter@gmail.com> wrote:
>>>> Peter Crosthwaite (4):
>>>>   ahci: Add some MMIO debug printfs
>>>>   ahci: split realize and init
>>>>   ahci: Add allwinner AHCI
>>>>   arm: allwinner-a10: Add SATA
>>>
>>> Are you hoping for this to go in for 2.5? I think the RFC
>>> made it onto the list before softfreeze...
>>>
>>
>> Yes, Is John Snow doing another round before HF?

> Yes, I intend to help you with this for 2.5.

Given the diffstat, are you planning to take this through
the IDE tree? I'm happy for you to do that, I can just take
this off my to-review list then :-)

thanks
-- PMM

Re: [Qemu-devel] [PATCH v1 0/4] AHCI patches + Allwinner SATA

[John Snow]

On 10/30/2015 05:37 PM, Peter Maydell wrote:
> On 30 October 2015 at 21:34, John Snow <jsnow@redhat.com> wrote:
>>
>>
>> On 10/30/2015 05:33 PM, Peter Crosthwaite wrote:
>>> On Fri, Oct 30, 2015 at 2:28 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
>>>> On 27 October 2015 at 04:02, Peter Crosthwaite
>>>> <crosthwaitepeter@gmail.com> wrote:
>>>>> Peter Crosthwaite (4):
>>>>>   ahci: Add some MMIO debug printfs
>>>>>   ahci: split realize and init
>>>>>   ahci: Add allwinner AHCI
>>>>>   arm: allwinner-a10: Add SATA
>>>>
>>>> Are you hoping for this to go in for 2.5? I think the RFC
>>>> made it onto the list before softfreeze...
>>>>
>>>
>>> Yes, Is John Snow doing another round before HF?
> 
>> Yes, I intend to help you with this for 2.5.
> 
> Given the diffstat, are you planning to take this through
> the IDE tree? I'm happy for you to do that, I can just take
> this off my to-review list then :-)
> 
> thanks
> -- PMM
> 

If nobody has objections, I assumed that would be the natural
destination for the series.

You might still want to take a peek to make sure the overall qdev
plumbing makes sense, but I can still take it through my tree if it
passes the sniff test for you.

--js

Re: [Qemu-devel] [PATCH v1 0/4] AHCI patches + Allwinner SATA

[Peter Maydell]

On 30 October 2015 at 21:40, John Snow <jsnow@redhat.com> wrote:
> On 10/30/2015 05:37 PM, Peter Maydell wrote:
>> Given the diffstat, are you planning to take this through
>> the IDE tree? I'm happy for you to do that, I can just take
>> this off my to-review list then :-)

> If nobody has objections, I assumed that would be the natural
> destination for the series.
>
> You might still want to take a peek to make sure the overall qdev
> plumbing makes sense, but I can still take it through my tree if it
> passes the sniff test for you.

I just had a quick scan through the patches and they look OK to me.
I'll leave the rest of the review and getting them into master
to you, then.

thanks
-- PMM

Re: [Qemu-devel] [PATCH v1 0/4] AHCI patches + Allwinner SATA

[John Snow]

On 10/27/2015 12:02 AM, Peter Crosthwaite wrote:
> This patch series adds bare-minimum Allwinner SATA support.
> 
> P1 is a trivial to help debug AHCI.
> 
> Changed since RFC:
> Addressed Beniamino review.
> Rebased to avoid bad deps (John Snow review)
> 
> Regards,
> Peter
> 
> 
> Peter Crosthwaite (4):
>   ahci: Add some MMIO debug printfs
>   ahci: split realize and init
>   ahci: Add allwinner AHCI
>   arm: allwinner-a10: Add SATA
> 
>  hw/arm/allwinner-a10.c         |  11 +++
>  hw/ide/ahci.c                  | 152 +++++++++++++++++++++++++++++++++++------
>  hw/ide/ahci.h                  |  19 +++++-
>  hw/ide/ich.c                   |  10 ++-
>  include/hw/arm/allwinner-a10.h |   4 ++
>  include/qemu/typedefs.h        |   1 +
>  6 files changed, 176 insertions(+), 21 deletions(-)
> 

Benefit of the doubt on the Allwinner-specific registers:

Reviewed-by: John Snow <jsnow@redhat.com>

Will stage for 2.5 later.

Thanks,
--js

Re: [Qemu-devel] [PATCH v1 0/4] AHCI patches + Allwinner SATA

[John Snow]

On 10/27/2015 12:02 AM, Peter Crosthwaite wrote:
> This patch series adds bare-minimum Allwinner SATA support.
> 
> P1 is a trivial to help debug AHCI.
> 
> Changed since RFC:
> Addressed Beniamino review.
> Rebased to avoid bad deps (John Snow review)
> 
> Regards,
> Peter
> 
> 
> Peter Crosthwaite (4):
>   ahci: Add some MMIO debug printfs
>   ahci: split realize and init
>   ahci: Add allwinner AHCI
>   arm: allwinner-a10: Add SATA
> 
>  hw/arm/allwinner-a10.c         |  11 +++
>  hw/ide/ahci.c                  | 152 +++++++++++++++++++++++++++++++++++------
>  hw/ide/ahci.h                  |  19 +++++-
>  hw/ide/ich.c                   |  10 ++-
>  include/hw/arm/allwinner-a10.h |   4 ++
>  include/qemu/typedefs.h        |   1 +
>  6 files changed, 176 insertions(+), 21 deletions(-)
> 

I patched up some minor context on 3/4.

Thanks, applied to my IDE tree:

https://github.com/jnsnow/qemu/commits/ide
https://github.com/jnsnow/qemu.git

--js