From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37872) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aR7vK-0001Hb-Rh for qemu-devel@nongnu.org; Wed, 03 Feb 2016 19:37:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aR7vH-00033y-Lq for qemu-devel@nongnu.org; Wed, 03 Feb 2016 19:37:26 -0500 Received: from mail-cys01nam02on0086.outbound.protection.outlook.com ([104.47.37.86]:42393 helo=NAM02-CY1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aR7vH-000328-GN for qemu-devel@nongnu.org; Wed, 03 Feb 2016 19:37:23 -0500 From: Alistair Francis Date: Wed, 3 Feb 2016 16:34:44 -0800 Message-ID: MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v1 0/3] Extend the performance monitoring registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, alindsay@codeaurora.org, alistair.francis@xilinx.com, crosthwaitepeter@gmail.com, cov@codeaurora.org, nathan@nathanrossi.com This patch set is based on the patch sent by Christopher Covington and written by Aaron Lindsay which was sent as an RFC (Implement remaining PMU functionality). It adds a few performance monitoring related registers. Alistair Francis (3): target-arm: Add the pmceid0 and pmceid1 registers target-arm: Add Some of the performance monitor registers target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers target-arm/cpu-qom.h | 2 + target-arm/cpu.c | 2 + target-arm/cpu.h | 6 +++ target-arm/cpu64.c | 2 + target-arm/helper.c | 109 +++++++++++++++++++++++++++++++++++++++++++++------ 5 files changed, 110 insertions(+), 11 deletions(-) -- 2.5.0