From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38487) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aRrCK-0004A4-3C for qemu-devel@nongnu.org; Fri, 05 Feb 2016 19:58:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aRrCG-0001TR-SQ for qemu-devel@nongnu.org; Fri, 05 Feb 2016 19:58:00 -0500 Received: from mail-bl2nam02on0088.outbound.protection.outlook.com ([104.47.38.88]:44304 helo=NAM02-BL2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aRrCG-0001SZ-Nr for qemu-devel@nongnu.org; Fri, 05 Feb 2016 19:57:56 -0500 From: Alistair Francis Date: Fri, 5 Feb 2016 16:55:14 -0800 Message-ID: MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 0/5] Extend the performance monitoring registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, alindsay@codeaurora.org, alistair.francis@xilinx.com, crosthwaitepeter@gmail.com, cov@codeaurora.org, nathan@nathanrossi.com This patch set is based on the patch sent by Christopher Covington and written by Aaron Lindsay which was sent as an RFC (Implement remaining PMU functionality). It adds a few performance monitoring related registers. V2: - Add Aaron to the signed off lines - Add the tested-by lines from Nathan - Add two more patches from Chris Alistair Francis (5): target-arm: Add the pmceid0 and pmceid1 registers target-arm: Add Some of the performance monitor registers target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers target-arm: Add PMUSERENR_EL0 register target-arm: Unmask PMU bits in debug feature register target-arm/cpu-qom.h | 2 + target-arm/cpu.c | 2 + target-arm/cpu.h | 6 +++ target-arm/cpu64.c | 2 + target-arm/helper.c | 122 ++++++++++++++++++++++++++++++++++++++++++++------- 5 files changed, 117 insertions(+), 17 deletions(-) -- 2.5.0