From: Alistair Francis <alistair.francis@xilinx.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, alindsay@codeaurora.org,
alistair.francis@xilinx.com, crosthwaitepeter@gmail.com,
cov@codeaurora.org, nathan@nathanrossi.com
Subject: [Qemu-devel] [PATCH v3 0/3] Extend the performance monitoring registers
Date: Tue, 9 Feb 2016 15:47:14 -0800 [thread overview]
Message-ID: <cover.1455060548.git.alistair.francis@xilinx.com> (raw)
This patch set is based on the patch sent by Christopher Covington and
written by Aaron Lindsay which was sent as an RFC (Implement remaining
PMU functionality).
It adds a few performance monitoring related registers.
V3:
- Fixes pased on Peter Maydell's feedback
- Remove patch 2 and 5 to get these accepted first
V2:
- Add Aaron to the signed off lines
- Add the tested-by lines from Nathan
- Add two more patches from Chris
Alistair Francis (3):
target-arm: Add the pmceid0 and pmceid1 registers
target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers
target-arm: Add PMUSERENR_EL0 register
target-arm/cpu-qom.h | 2 ++
target-arm/cpu.c | 2 ++
target-arm/cpu64.c | 2 ++
target-arm/helper.c | 34 ++++++++++++++++++++++++++++++++++
4 files changed, 40 insertions(+)
--
2.5.0
next reply other threads:[~2016-02-09 23:49 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-09 23:47 Alistair Francis [this message]
2016-02-09 23:47 ` [Qemu-devel] [PATCH v3 1/3] target-arm: Add the pmceid0 and pmceid1 registers Alistair Francis
2016-02-09 23:47 ` [Qemu-devel] [PATCH v3 2/3] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers Alistair Francis
2016-02-09 23:47 ` [Qemu-devel] [PATCH v3 3/3] target-arm: Add PMUSERENR_EL0 register Alistair Francis
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