From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55533) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aUcic-0005Pv-0O for qemu-devel@nongnu.org; Sat, 13 Feb 2016 11:06:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aUciY-00012F-N0 for qemu-devel@nongnu.org; Sat, 13 Feb 2016 11:06:45 -0500 Received: from zose-mta03.web4all.fr ([185.49.20.44]:41337) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aUciY-00011y-Ge for qemu-devel@nongnu.org; Sat, 13 Feb 2016 11:06:42 -0500 From: Jean-Christophe Dubois Date: Sat, 13 Feb 2016 17:06:34 +0100 Message-Id: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 0/3] Add support for i.MX SPI Controller List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, crosthwaite.peter@gmail.com Cc: Jean-Christophe Dubois This patch serie adds support for the i.MX SPI controller. The controller is then added to the i.MX6 SOC implementation to=20 avoid Linux hang during boot because there is no support for the SPI controller and it is waiting for some SPI device response. This patch also adds a FIFO32 implementation as it is part of the=20 i.MX SPI controller basic mechanisms. The FIFO32 is build on top of the existing FIFO8. Jean-Christophe Dubois (3): FIFO: Add a FIFO32 implementation i.MX: Add the Freescale SPI Controller i.MX: Add SPI controllers to i.MX6 SOC hw/arm/fsl-imx6.c | 32 ++++ hw/ssi/Makefile.objs | 1 + hw/ssi/imx_spi.c | 449 ++++++++++++++++++++++++++++++++++++++++= ++++++ include/hw/arm/fsl-imx6.h | 3 + include/hw/ssi/imx_spi.h | 104 +++++++++++ include/qemu/fifo32.h | 206 +++++++++++++++++++++ 6 files changed, 795 insertions(+) create mode 100644 hw/ssi/imx_spi.c create mode 100644 include/hw/ssi/imx_spi.h create mode 100644 include/qemu/fifo32.h --=20 2.5.0