From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55796) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b0zQ6-00069F-FQ for qemu-devel@nongnu.org; Thu, 12 May 2016 18:49:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b0zQ2-0002Gj-3x for qemu-devel@nongnu.org; Thu, 12 May 2016 18:49:25 -0400 Received: from mail-bl2nam02on0081.outbound.protection.outlook.com ([104.47.38.81]:50963 helo=NAM02-BL2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b0zQ1-0002Gd-U1 for qemu-devel@nongnu.org; Thu, 12 May 2016 18:49:22 -0400 From: Alistair Francis Date: Thu, 12 May 2016 15:45:51 -0700 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v6 00/13] data-driven device registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair.francis@xilinx.com, crosthwaitepeter@gmail.com, edgar.iglesias@xilinx.com, edgar.iglesias@gmail.com, afaerber@suse.de, fred.konrad@greensocs.com, alex.bennee@linaro.org This patch series is based on Peter C's original register API. His original cover letter is below. Future work: Allow support for memory attributes. V6: - Small changes to the API based on Alex's comments - Remove 'register: Add support for decoding information' patch - Move prefix and debug into the RegisterInfoArray as it is the same for every register. V5: - Only create a single memory region instead of a memory region for each register - General tidyups based on Alex's comments V4: - Rebase and fix build issue - Simplify the register write logic - Other small fixes suggested by Alex Bennee V3: - Small changes reported by Fred V2: - Rebase - Fix up IOU SLCR connections - Add the memory_region_add_subregion_no_print() function and use it for the registers Changes since RFC: - Connect the ZynqMP IOU SLCR device - Rebase Original cover letter From Peter: Hi All. This is a new scheme I've come up with handling device registers in= a data driven way. My motivation for this is to factor out a lot of the acces= s checking that seems to be replicated in every device. See P1 commit message= for further discussion. P1 is the main patch, adds the register definition functionality P2-3,6 add helpers that glue the register API to the Memory API P4 Defines a set of macros that minimise register and field definitions P5 is QOMfication P7 is a trivial P10-13 Work up to GPIO support P8,9,14 add new devices (the Xilinx Zynq devcfg & ZynqMP SLCR) that use thi= s scheme. P15: Connect the ZynqMP SLCR device This Zynq devcfg device was particularly finnicky with per-bit restrictions= . I'm also looking for a higher-than-usual modelling fidelity on the register space, with semantics defined for random reserved bits in-between otherwise consistent fields. Here's an example of the qemu_log output for the devcfg device. This is pro= duced by now generic sharable code: /machine/unattached/device[44]:Addr 0x000008:CFG: write of value 00000508 /machine/unattached/device[44]:Addr 0x000080:MCTRL: write of value 00800010 /machine/unattached/device[44]:Addr 0x000010:INT_MASK: write of value fffff= fff /machine/unattached/device[44]:Addr 00000000:CTRL: write of value 0c00607f And an example of a rogue guest banging on a bad bit: /machine/unattached/device[44]:Addr 0x000014:STATUS bits 0x000001 may not b= e \ written to 1 A future feature I am interested in is implementing TCG optimisation of side-effectless registers. The register API allows clear definition of what registers have txn side effects and which ones don't. You could even go a step further and translate such side-effectless accesses based on the data pointer for the register. Alistair Francis (6): bitops: Add MAKE_64BIT_MASK macro register: Add Register API register: Add Memory API glue dma: Add Xilinx Zynq devcfg device model register: Add GPIO API xlnx-zynqmp: Connect the ZynqMP IOU SLCR Peter Crosthwaite (7): register: Define REG and FIELD macros register: QOMify register: Add block initialise helper xilinx_zynq: Connect devcfg to the Zynq machine model qdev: Define qdev_get_gpio_out irq: Add opaque setter routine misc: Introduce ZynqMP IOU SLCR default-configs/arm-softmmu.mak | 1 + hw/arm/xilinx_zynq.c | 8 + hw/arm/xlnx-zynqmp.c | 13 ++ hw/core/Makefile.objs | 1 + hw/core/irq.c | 5 + hw/core/qdev.c | 12 + hw/core/register.c | 376 +++++++++++++++++++++++++++++= ++ hw/dma/Makefile.objs | 1 + hw/dma/xlnx-zynq-devcfg.c | 396 +++++++++++++++++++++++++++++= ++++ hw/misc/Makefile.objs | 1 + hw/misc/xlnx-zynqmp-iou-slcr.c | 115 ++++++++++ include/hw/arm/xlnx-zynqmp.h | 2 + include/hw/dma/xlnx-zynq-devcfg.h | 62 ++++++ include/hw/irq.h | 2 + include/hw/misc/xlnx-zynqmp-iou-slcr.h | 47 ++++ include/hw/qdev-core.h | 2 + include/hw/register.h | 262 ++++++++++++++++++++++ include/qemu/bitops.h | 3 + 18 files changed, 1309 insertions(+) create mode 100644 hw/core/register.c create mode 100644 hw/dma/xlnx-zynq-devcfg.c create mode 100644 hw/misc/xlnx-zynqmp-iou-slcr.c create mode 100644 include/hw/dma/xlnx-zynq-devcfg.h create mode 100644 include/hw/misc/xlnx-zynqmp-iou-slcr.h create mode 100644 include/hw/register.h --=20 2.7.4