* [Qemu-devel] [PATCH v7 12/13] sm501: Add vmstate descriptor
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
@ 2017-04-21 15:18 ` BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 13/13] ppc: Add SM501 device in ppc softmmu targets default configs BALATON Zoltan
` (13 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2017-04-21 15:18 UTC (permalink / raw)
To: qemu-devel, qemu-trivial
Cc: Magnus Damm, Aurelien Jarno, Peter Maydell, David Gibson
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
---
v3: Added local_mem_size_index to vmstate, add vmstate for sysbus version too
hw/display/sm501.c | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 99 insertions(+), 1 deletion(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 4e09d8a..2094adb 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -66,6 +66,7 @@
#define MMIO_BASE_OFFSET 0x3e00000
#define MMIO_SIZE 0x200000
+#define DC_PALETTE_ENTRIES (0x400 * 3)
/* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
@@ -492,7 +493,7 @@ typedef struct SM501State {
uint32_t uart0_mcr;
uint32_t uart0_scr;
- uint8_t dc_palette[0x400 * 3];
+ uint8_t dc_palette[DC_PALETTE_ENTRIES];
uint32_t dc_panel_control;
uint32_t dc_panel_panning_control;
@@ -1618,6 +1619,78 @@ static void sm501_init(SM501State *s, DeviceState *dev,
s->con = graphic_console_init(DEVICE(dev), 0, &sm501_ops, s);
}
+static const VMStateDescription vmstate_sm501_state = {
+ .name = "sm501-state",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(local_mem_size_index, SM501State),
+ VMSTATE_UINT32(system_control, SM501State),
+ VMSTATE_UINT32(misc_control, SM501State),
+ VMSTATE_UINT32(gpio_31_0_control, SM501State),
+ VMSTATE_UINT32(gpio_63_32_control, SM501State),
+ VMSTATE_UINT32(dram_control, SM501State),
+ VMSTATE_UINT32(arbitration_control, SM501State),
+ VMSTATE_UINT32(irq_mask, SM501State),
+ VMSTATE_UINT32(misc_timing, SM501State),
+ VMSTATE_UINT32(power_mode_control, SM501State),
+ VMSTATE_UINT32(uart0_ier, SM501State),
+ VMSTATE_UINT32(uart0_lcr, SM501State),
+ VMSTATE_UINT32(uart0_mcr, SM501State),
+ VMSTATE_UINT32(uart0_scr, SM501State),
+ VMSTATE_UINT8_ARRAY(dc_palette, SM501State, DC_PALETTE_ENTRIES),
+ VMSTATE_UINT32(dc_panel_control, SM501State),
+ VMSTATE_UINT32(dc_panel_panning_control, SM501State),
+ VMSTATE_UINT32(dc_panel_fb_addr, SM501State),
+ VMSTATE_UINT32(dc_panel_fb_offset, SM501State),
+ VMSTATE_UINT32(dc_panel_fb_width, SM501State),
+ VMSTATE_UINT32(dc_panel_fb_height, SM501State),
+ VMSTATE_UINT32(dc_panel_tl_location, SM501State),
+ VMSTATE_UINT32(dc_panel_br_location, SM501State),
+ VMSTATE_UINT32(dc_panel_h_total, SM501State),
+ VMSTATE_UINT32(dc_panel_h_sync, SM501State),
+ VMSTATE_UINT32(dc_panel_v_total, SM501State),
+ VMSTATE_UINT32(dc_panel_v_sync, SM501State),
+ VMSTATE_UINT32(dc_panel_hwc_addr, SM501State),
+ VMSTATE_UINT32(dc_panel_hwc_location, SM501State),
+ VMSTATE_UINT32(dc_panel_hwc_color_1_2, SM501State),
+ VMSTATE_UINT32(dc_panel_hwc_color_3, SM501State),
+ VMSTATE_UINT32(dc_video_control, SM501State),
+ VMSTATE_UINT32(dc_crt_control, SM501State),
+ VMSTATE_UINT32(dc_crt_fb_addr, SM501State),
+ VMSTATE_UINT32(dc_crt_fb_offset, SM501State),
+ VMSTATE_UINT32(dc_crt_h_total, SM501State),
+ VMSTATE_UINT32(dc_crt_h_sync, SM501State),
+ VMSTATE_UINT32(dc_crt_v_total, SM501State),
+ VMSTATE_UINT32(dc_crt_v_sync, SM501State),
+ VMSTATE_UINT32(dc_crt_hwc_addr, SM501State),
+ VMSTATE_UINT32(dc_crt_hwc_location, SM501State),
+ VMSTATE_UINT32(dc_crt_hwc_color_1_2, SM501State),
+ VMSTATE_UINT32(dc_crt_hwc_color_3, SM501State),
+ VMSTATE_UINT32(twoD_source, SM501State),
+ VMSTATE_UINT32(twoD_destination, SM501State),
+ VMSTATE_UINT32(twoD_dimension, SM501State),
+ VMSTATE_UINT32(twoD_control, SM501State),
+ VMSTATE_UINT32(twoD_pitch, SM501State),
+ VMSTATE_UINT32(twoD_foreground, SM501State),
+ VMSTATE_UINT32(twoD_background, SM501State),
+ VMSTATE_UINT32(twoD_stretch, SM501State),
+ VMSTATE_UINT32(twoD_color_compare, SM501State),
+ VMSTATE_UINT32(twoD_color_compare_mask, SM501State),
+ VMSTATE_UINT32(twoD_mask, SM501State),
+ VMSTATE_UINT32(twoD_clip_tl, SM501State),
+ VMSTATE_UINT32(twoD_clip_br, SM501State),
+ VMSTATE_UINT32(twoD_mono_pattern_low, SM501State),
+ VMSTATE_UINT32(twoD_mono_pattern_high, SM501State),
+ VMSTATE_UINT32(twoD_window_width, SM501State),
+ VMSTATE_UINT32(twoD_source_base, SM501State),
+ VMSTATE_UINT32(twoD_destination_base, SM501State),
+ VMSTATE_UINT32(twoD_alpha, SM501State),
+ VMSTATE_UINT32(twoD_wrap, SM501State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
#define TYPE_SYSBUS_SM501 "sysbus-sm501"
#define SYSBUS_SM501(obj) \
OBJECT_CHECK(SM501SysBusState, (obj), TYPE_SYSBUS_SM501)
@@ -1677,6 +1750,17 @@ static void sm501_reset_sysbus(DeviceState *dev)
sm501_reset(&s->state);
}
+static const VMStateDescription vmstate_sm501_sysbus = {
+ .name = TYPE_SYSBUS_SM501,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT(state, SM501SysBusState, 1,
+ vmstate_sm501_state, SM501State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1686,6 +1770,7 @@ static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
dc->desc = "SM501 Multimedia Companion";
dc->props = sm501_sysbus_properties;
dc->reset = sm501_reset_sysbus;
+ dc->vmsd = &vmstate_sm501_sysbus;
/* Note: pointer property "chr-state" may remain null, thus
* no need for dc->cannot_instantiate_with_device_add_yet = true;
*/
@@ -1738,6 +1823,18 @@ static void sm501_reset_pci(DeviceState *dev)
s->state.misc_control |= 1;
}
+static const VMStateDescription vmstate_sm501_pci = {
+ .name = TYPE_PCI_SM501,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_PCI_DEVICE(parent_obj, SM501PCIState),
+ VMSTATE_STRUCT(state, SM501PCIState, 1,
+ vmstate_sm501_state, SM501State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void sm501_pci_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1752,6 +1849,7 @@ static void sm501_pci_class_init(ObjectClass *klass, void *data)
dc->props = sm501_pci_properties;
dc->reset = sm501_reset_pci;
dc->hotpluggable = false;
+ dc->vmsd = &vmstate_sm501_pci;
}
static const TypeInfo sm501_pci_info = {
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH v7 13/13] ppc: Add SM501 device in ppc softmmu targets default configs
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 12/13] sm501: Add vmstate descriptor BALATON Zoltan
@ 2017-04-21 15:18 ` BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 11/13] sm501: Add some more missing registers BALATON Zoltan
` (12 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2017-04-21 15:18 UTC (permalink / raw)
To: qemu-devel, qemu-trivial
Cc: Magnus Damm, Aurelien Jarno, Peter Maydell, David Gibson
This is not used by default on any emulated machine yet but it is
still useful to have it compiled so it can be added from the command
line for clients that can use it (e.g. MorphOS has no driver for any
other emulated video cards but can output via SM501)
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
---
v5: Added sm501 also to ppc64-softmmu default config
default-configs/ppc-softmmu.mak | 1 +
default-configs/ppc64-softmmu.mak | 1 +
default-configs/ppcemb-softmmu.mak | 1 +
3 files changed, 3 insertions(+)
diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
index 09c1d45..1f1cd85 100644
--- a/default-configs/ppc-softmmu.mak
+++ b/default-configs/ppc-softmmu.mak
@@ -45,6 +45,7 @@ CONFIG_OPENPIC_KVM=$(and $(CONFIG_E500),$(CONFIG_KVM))
CONFIG_PLATFORM_BUS=y
CONFIG_ETSEC=y
CONFIG_LIBDECNUMBER=y
+CONFIG_SM501=y
# For PReP
CONFIG_SERIAL_ISA=y
CONFIG_MC146818RTC=y
diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak
index 05c8335..f6ccb1b 100644
--- a/default-configs/ppc64-softmmu.mak
+++ b/default-configs/ppc64-softmmu.mak
@@ -47,6 +47,7 @@ CONFIG_OPENPIC_KVM=$(and $(CONFIG_E500),$(CONFIG_KVM))
CONFIG_PLATFORM_BUS=y
CONFIG_ETSEC=y
CONFIG_LIBDECNUMBER=y
+CONFIG_SM501=y
# For pSeries
CONFIG_XICS=$(CONFIG_PSERIES)
CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
diff --git a/default-configs/ppcemb-softmmu.mak b/default-configs/ppcemb-softmmu.mak
index 7f56004..94340de 100644
--- a/default-configs/ppcemb-softmmu.mak
+++ b/default-configs/ppcemb-softmmu.mak
@@ -15,3 +15,4 @@ CONFIG_I8259=y
CONFIG_XILINX=y
CONFIG_XILINX_ETHLITE=y
CONFIG_LIBDECNUMBER=y
+CONFIG_SM501=y
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH v7 11/13] sm501: Add some more missing registers
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 12/13] sm501: Add vmstate descriptor BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 13/13] ppc: Add SM501 device in ppc softmmu targets default configs BALATON Zoltan
@ 2017-04-21 15:18 ` BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 04/13] sm501: QOMify BALATON Zoltan
` (11 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2017-04-21 15:18 UTC (permalink / raw)
To: qemu-devel, qemu-trivial
Cc: Magnus Damm, Aurelien Jarno, Peter Maydell, David Gibson
This is to allow clients to initialise these without failing as long
as no 2D engine function is called that would use the written value.
Saved values are not used yet (may get used when more of 2D engine is
added sometimes) and clients normally only write to most of these
registers, nothing is known to ever read them but they are documented
as read/write so also implement read for these.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
---
v2: Fixed mask of video_control register for a read only bit
Changed IRQ status register to write ignored as IRQ is not implemented
v3: Squashed read implementation into this patch
v4: Add reset for all 2D engine registers (although these are
documented to be 0 on reset, a comment in U-Boot source suggests that
they are really undefined so the previous version might have been enough)
hw/display/sm501.c | 126 ++++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 125 insertions(+), 1 deletion(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 7f2e899..4e09d8a 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -512,6 +512,8 @@ typedef struct SM501State {
uint32_t dc_panel_hwc_color_1_2;
uint32_t dc_panel_hwc_color_3;
+ uint32_t dc_video_control;
+
uint32_t dc_crt_control;
uint32_t dc_crt_fb_addr;
uint32_t dc_crt_fb_offset;
@@ -531,13 +533,20 @@ typedef struct SM501State {
uint32_t twoD_control;
uint32_t twoD_pitch;
uint32_t twoD_foreground;
+ uint32_t twoD_background;
uint32_t twoD_stretch;
+ uint32_t twoD_color_compare;
uint32_t twoD_color_compare_mask;
uint32_t twoD_mask;
+ uint32_t twoD_clip_tl;
+ uint32_t twoD_clip_br;
+ uint32_t twoD_mono_pattern_low;
+ uint32_t twoD_mono_pattern_high;
uint32_t twoD_window_width;
uint32_t twoD_source_base;
uint32_t twoD_destination_base;
-
+ uint32_t twoD_alpha;
+ uint32_t twoD_wrap;
} SM501State;
static uint32_t get_local_mem_size_index(uint32_t size)
@@ -946,6 +955,10 @@ static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
ret = s->dc_panel_v_sync;
break;
+ case SM501_DC_VIDEO_CONTROL:
+ ret = s->dc_video_control;
+ break;
+
case SM501_DC_CRT_CONTROL:
ret = s->dc_crt_control;
break;
@@ -1061,6 +1074,10 @@ static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
s->dc_panel_hwc_color_3 = value & 0x0000FFFF;
break;
+ case SM501_DC_VIDEO_CONTROL:
+ s->dc_video_control = value & 0x00037FFF;
+ break;
+
case SM501_DC_CRT_CONTROL:
s->dc_crt_control = value & 0x0003FFFF;
break;
@@ -1133,9 +1150,69 @@ static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr);
switch (addr) {
+ case SM501_2D_SOURCE:
+ ret = s->twoD_source;
+ break;
+ case SM501_2D_DESTINATION:
+ ret = s->twoD_destination;
+ break;
+ case SM501_2D_DIMENSION:
+ ret = s->twoD_dimension;
+ break;
+ case SM501_2D_CONTROL:
+ ret = s->twoD_control;
+ break;
+ case SM501_2D_PITCH:
+ ret = s->twoD_pitch;
+ break;
+ case SM501_2D_FOREGROUND:
+ ret = s->twoD_foreground;
+ break;
+ case SM501_2D_BACKGROUND:
+ ret = s->twoD_background;
+ break;
+ case SM501_2D_STRETCH:
+ ret = s->twoD_stretch;
+ break;
+ case SM501_2D_COLOR_COMPARE:
+ ret = s->twoD_color_compare;
+ break;
+ case SM501_2D_COLOR_COMPARE_MASK:
+ ret = s->twoD_color_compare_mask;
+ break;
+ case SM501_2D_MASK:
+ ret = s->twoD_mask;
+ break;
+ case SM501_2D_CLIP_TL:
+ ret = s->twoD_clip_tl;
+ break;
+ case SM501_2D_CLIP_BR:
+ ret = s->twoD_clip_br;
+ break;
+ case SM501_2D_MONO_PATTERN_LOW:
+ ret = s->twoD_mono_pattern_low;
+ break;
+ case SM501_2D_MONO_PATTERN_HIGH:
+ ret = s->twoD_mono_pattern_high;
+ break;
+ case SM501_2D_WINDOW_WIDTH:
+ ret = s->twoD_window_width;
+ break;
case SM501_2D_SOURCE_BASE:
ret = s->twoD_source_base;
break;
+ case SM501_2D_DESTINATION_BASE:
+ ret = s->twoD_destination_base;
+ break;
+ case SM501_2D_ALPHA:
+ ret = s->twoD_alpha;
+ break;
+ case SM501_2D_WRAP:
+ ret = s->twoD_wrap;
+ break;
+ case SM501_2D_STATUS:
+ ret = 0; /* Should return interrupt status */
+ break;
default:
printf("sm501 disp ctrl : not implemented register read."
" addr=%x\n", (int)addr);
@@ -1178,15 +1255,33 @@ static void sm501_2d_engine_write(void *opaque, hwaddr addr,
case SM501_2D_FOREGROUND:
s->twoD_foreground = value;
break;
+ case SM501_2D_BACKGROUND:
+ s->twoD_background = value;
+ break;
case SM501_2D_STRETCH:
s->twoD_stretch = value;
break;
+ case SM501_2D_COLOR_COMPARE:
+ s->twoD_color_compare = value;
+ break;
case SM501_2D_COLOR_COMPARE_MASK:
s->twoD_color_compare_mask = value;
break;
case SM501_2D_MASK:
s->twoD_mask = value;
break;
+ case SM501_2D_CLIP_TL:
+ s->twoD_clip_tl = value;
+ break;
+ case SM501_2D_CLIP_BR:
+ s->twoD_clip_br = value;
+ break;
+ case SM501_2D_MONO_PATTERN_LOW:
+ s->twoD_mono_pattern_low = value;
+ break;
+ case SM501_2D_MONO_PATTERN_HIGH:
+ s->twoD_mono_pattern_high = value;
+ break;
case SM501_2D_WINDOW_WIDTH:
s->twoD_window_width = value;
break;
@@ -1196,6 +1291,15 @@ static void sm501_2d_engine_write(void *opaque, hwaddr addr,
case SM501_2D_DESTINATION_BASE:
s->twoD_destination_base = value;
break;
+ case SM501_2D_ALPHA:
+ s->twoD_alpha = value;
+ break;
+ case SM501_2D_WRAP:
+ s->twoD_wrap = value;
+ break;
+ case SM501_2D_STATUS:
+ /* ignored, writing 0 should clear interrupt status */
+ break;
default:
printf("sm501 2d engine : not implemented register write."
" addr=%x, val=%x\n", (int)addr, (unsigned)value);
@@ -1454,8 +1558,28 @@ static void sm501_reset(SM501State *s)
s->misc_timing = 0;
s->power_mode_control = 0;
s->dc_panel_control = 0x00010000; /* FIFO level 3 */
+ s->dc_video_control = 0;
s->dc_crt_control = 0x00010000;
+ s->twoD_source = 0;
+ s->twoD_destination = 0;
+ s->twoD_dimension = 0;
s->twoD_control = 0;
+ s->twoD_pitch = 0;
+ s->twoD_foreground = 0;
+ s->twoD_background = 0;
+ s->twoD_stretch = 0;
+ s->twoD_color_compare = 0;
+ s->twoD_color_compare_mask = 0;
+ s->twoD_mask = 0;
+ s->twoD_clip_tl = 0;
+ s->twoD_clip_br = 0;
+ s->twoD_mono_pattern_low = 0;
+ s->twoD_mono_pattern_high = 0;
+ s->twoD_window_width = 0;
+ s->twoD_source_base = 0;
+ s->twoD_destination_base = 0;
+ s->twoD_alpha = 0;
+ s->twoD_wrap = 0;
}
static void sm501_init(SM501State *s, DeviceState *dev,
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH v7 04/13] sm501: QOMify
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
` (2 preceding siblings ...)
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 11/13] sm501: Add some more missing registers BALATON Zoltan
@ 2017-04-21 15:18 ` BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 05/13] sm501: Get rid of base address in draw_hwc_line BALATON Zoltan
` (10 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2017-04-21 15:18 UTC (permalink / raw)
To: qemu-devel, qemu-trivial
Cc: Magnus Damm, Aurelien Jarno, Peter Maydell, David Gibson
Adding vmstate saving is not in this patch because the state structure
will be changed in further patches, then another patch will add
vmstate descriptor after those changes.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
---
v2: Add memory regions to device state instead of allocating them
v3: Added reset function and make sure to use adjusted mem size when
creating local mem region (also print a warning when mem size was
adjusted)
v4: Replace warning for corrected memory size with a hard error
hw/display/sm501.c | 170 +++++++++++++++++++++++++++++++++++++--------------
hw/sh4/r2d.c | 11 +++-
include/hw/devices.h | 5 --
3 files changed, 133 insertions(+), 53 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 6e74200..571a7e6 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -59,8 +59,8 @@
#define SM501_DPRINTF(fmt, ...) do {} while (0)
#endif
-
#define MMIO_BASE_OFFSET 0x3e00000
+#define MMIO_SIZE 0x200000
/* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
@@ -465,6 +465,10 @@ typedef struct SM501State {
uint32_t local_mem_size_index;
uint8_t *local_mem;
MemoryRegion local_mem_region;
+ MemoryRegion mmio_region;
+ MemoryRegion system_config_region;
+ MemoryRegion disp_ctrl_region;
+ MemoryRegion twoD_engine_region;
uint32_t last_width;
uint32_t last_height;
@@ -1404,21 +1408,8 @@ static const GraphicHwOps sm501_ops = {
.gfx_update = sm501_update_display,
};
-void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
- uint32_t local_mem_bytes, qemu_irq irq, Chardev *chr)
+static void sm501_reset(SM501State *s)
{
- SM501State *s;
- DeviceState *dev;
- MemoryRegion *sm501_system_config = g_new(MemoryRegion, 1);
- MemoryRegion *sm501_disp_ctrl = g_new(MemoryRegion, 1);
- MemoryRegion *sm501_2d_engine = g_new(MemoryRegion, 1);
-
- /* allocate management data region */
- s = g_new0(SM501State, 1);
- s->base = base;
- s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
- SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
- s->local_mem_size_index);
s->system_control = 0x00100000; /* 2D engine FIFO empty */
/* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
* to be determined at reset by GPIO lines which set config bits.
@@ -1429,51 +1420,138 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
* BUS = 0 : Hitachi SH3/SH4
*/
s->misc_control = SM501_MISC_DAC_POWER;
+ s->gpio_31_0_control = 0;
+ s->gpio_63_32_control = 0;
+ s->dram_control = 0;
s->arbitration_control = 0x05146732;
+ s->irq_mask = 0;
+ s->misc_timing = 0;
+ s->power_mode_control = 0;
s->dc_panel_control = 0x00010000; /* FIFO level 3 */
s->dc_crt_control = 0x00010000;
+ s->twoD_control = 0;
+}
- /* allocate local memory */
- memory_region_init_ram(&s->local_mem_region, NULL, "sm501.local",
- local_mem_bytes, &error_fatal);
+static void sm501_init(SM501State *s, DeviceState *dev, uint32_t base,
+ uint32_t local_mem_bytes)
+{
+ s->base = base;
+ s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
+ SM501_DPRINTF("sm501 local mem size=%x. index=%d\n", get_local_mem_size(s),
+ s->local_mem_size_index);
+
+ /* local memory */
+ memory_region_init_ram(&s->local_mem_region, OBJECT(dev), "sm501.local",
+ get_local_mem_size(s), &error_fatal);
vmstate_register_ram_global(&s->local_mem_region);
memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA);
s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region);
- memory_region_add_subregion(address_space_mem, base, &s->local_mem_region);
-
- /* map mmio */
- memory_region_init_io(sm501_system_config, NULL, &sm501_system_config_ops,
- s, "sm501-system-config", 0x6c);
- memory_region_add_subregion(address_space_mem, base + MMIO_BASE_OFFSET,
- sm501_system_config);
- memory_region_init_io(sm501_disp_ctrl, NULL, &sm501_disp_ctrl_ops, s,
+
+ /* mmio */
+ memory_region_init(&s->mmio_region, OBJECT(dev), "sm501.mmio", MMIO_SIZE);
+ memory_region_init_io(&s->system_config_region, OBJECT(dev),
+ &sm501_system_config_ops, s,
+ "sm501-system-config", 0x6c);
+ memory_region_add_subregion(&s->mmio_region, SM501_SYS_CONFIG,
+ &s->system_config_region);
+ memory_region_init_io(&s->disp_ctrl_region, OBJECT(dev),
+ &sm501_disp_ctrl_ops, s,
"sm501-disp-ctrl", 0x1000);
- memory_region_add_subregion(address_space_mem,
- base + MMIO_BASE_OFFSET + SM501_DC,
- sm501_disp_ctrl);
- memory_region_init_io(sm501_2d_engine, NULL, &sm501_2d_engine_ops, s,
+ memory_region_add_subregion(&s->mmio_region, SM501_DC,
+ &s->disp_ctrl_region);
+ memory_region_init_io(&s->twoD_engine_region, OBJECT(dev),
+ &sm501_2d_engine_ops, s,
"sm501-2d-engine", 0x54);
- memory_region_add_subregion(address_space_mem,
- base + MMIO_BASE_OFFSET + SM501_2D_ENGINE,
- sm501_2d_engine);
+ memory_region_add_subregion(&s->mmio_region, SM501_2D_ENGINE,
+ &s->twoD_engine_region);
+
+ /* create qemu graphic console */
+ s->con = graphic_console_init(DEVICE(dev), 0, &sm501_ops, s);
+}
+
+#define TYPE_SYSBUS_SM501 "sysbus-sm501"
+#define SYSBUS_SM501(obj) \
+ OBJECT_CHECK(SM501SysBusState, (obj), TYPE_SYSBUS_SM501)
+
+typedef struct {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+ SM501State state;
+ uint32_t vram_size;
+ uint32_t base;
+ void *chr_state;
+} SM501SysBusState;
+
+static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
+{
+ SM501SysBusState *s = SYSBUS_SM501(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ DeviceState *usb_dev;
+
+ sm501_init(&s->state, dev, s->base, s->vram_size);
+ if (get_local_mem_size(&s->state) != s->vram_size) {
+ error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32,
+ get_local_mem_size(&s->state));
+ return;
+ }
+ sysbus_init_mmio(sbd, &s->state.local_mem_region);
+ sysbus_init_mmio(sbd, &s->state.mmio_region);
/* bridge to usb host emulation module */
- dev = qdev_create(NULL, "sysbus-ohci");
- qdev_prop_set_uint32(dev, "num-ports", 2);
- qdev_prop_set_uint64(dev, "dma-offset", base);
- qdev_init_nofail(dev);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
- base + MMIO_BASE_OFFSET + SM501_USB_HOST);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
+ usb_dev = qdev_create(NULL, "sysbus-ohci");
+ qdev_prop_set_uint32(usb_dev, "num-ports", 2);
+ qdev_prop_set_uint64(usb_dev, "dma-offset", s->base);
+ qdev_init_nofail(usb_dev);
+ memory_region_add_subregion(&s->state.mmio_region, SM501_USB_HOST,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(usb_dev), 0));
+ sysbus_pass_irq(sbd, SYS_BUS_DEVICE(usb_dev));
/* bridge to serial emulation module */
- if (chr) {
- serial_mm_init(address_space_mem,
- base + MMIO_BASE_OFFSET + SM501_UART0, 2,
+ if (s->chr_state) {
+ serial_mm_init(&s->state.mmio_region, SM501_UART0, 2,
NULL, /* TODO : chain irq to IRL */
- 115200, chr, DEVICE_NATIVE_ENDIAN);
+ 115200, s->chr_state, DEVICE_NATIVE_ENDIAN);
}
+}
- /* create qemu graphic console */
- s->con = graphic_console_init(DEVICE(dev), 0, &sm501_ops, s);
+static Property sm501_sysbus_properties[] = {
+ DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0),
+ DEFINE_PROP_UINT32("base", SM501SysBusState, base, 0),
+ DEFINE_PROP_PTR("chr-state", SM501SysBusState, chr_state),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void sm501_reset_sysbus(DeviceState *dev)
+{
+ SM501SysBusState *s = SYSBUS_SM501(dev);
+ sm501_reset(&s->state);
}
+
+static void sm501_sysbus_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = sm501_realize_sysbus;
+ set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
+ dc->desc = "SM501 Multimedia Companion";
+ dc->props = sm501_sysbus_properties;
+ dc->reset = sm501_reset_sysbus;
+ /* Note: pointer property "chr-state" may remain null, thus
+ * no need for dc->cannot_instantiate_with_device_add_yet = true;
+ */
+}
+
+static const TypeInfo sm501_sysbus_info = {
+ .name = TYPE_SYSBUS_SM501,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SM501SysBusState),
+ .class_init = sm501_sysbus_class_init,
+};
+
+static void sm501_register_types(void)
+{
+ type_register_static(&sm501_sysbus_info);
+}
+
+type_init(sm501_register_types)
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 6d06968..8f520ce 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -277,8 +277,15 @@ static void r2d_init(MachineState *machine)
sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);
- sm501_init(address_space_mem, 0x10000000, SM501_VRAM_SIZE,
- irq[SM501], serial_hds[2]);
+ dev = qdev_create(NULL, "sysbus-sm501");
+ busdev = SYS_BUS_DEVICE(dev);
+ qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE);
+ qdev_prop_set_uint32(dev, "base", 0x10000000);
+ qdev_prop_set_ptr(dev, "chr-state", serial_hds[2]);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map(busdev, 0, 0x10000000);
+ sysbus_mmio_map(busdev, 1, 0x13e00000);
+ sysbus_connect_irq(busdev, 0, irq[SM501]);
/* onboard CF (True IDE mode, Master only). */
dinfo = drive_get(IF_IDE, 0, 0);
diff --git a/include/hw/devices.h b/include/hw/devices.h
index 7475b71..861ddea 100644
--- a/include/hw/devices.h
+++ b/include/hw/devices.h
@@ -62,9 +62,4 @@ void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s);
qemu_irq tc6393xb_l3v_get(TC6393xbState *s);
-/* sm501.c */
-void sm501_init(struct MemoryRegion *address_space_mem, uint32_t base,
- uint32_t local_mem_bytes, qemu_irq irq,
- Chardev *chr);
-
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH v7 05/13] sm501: Get rid of base address in draw_hwc_line
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
` (3 preceding siblings ...)
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 04/13] sm501: QOMify BALATON Zoltan
@ 2017-04-21 15:18 ` BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 10/13] sm501: Add support for panel layer BALATON Zoltan
` (9 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2017-04-21 15:18 UTC (permalink / raw)
To: qemu-devel, qemu-trivial
Cc: Magnus Damm, Aurelien Jarno, Peter Maydell, David Gibson
Do not use the base address to access data in local memory. This is in
preparation to allow chip connected via PCI where base address depends
on where the BAR is mapped so it will be unknown.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
---
hw/display/sm501.c | 6 ++----
hw/display/sm501_template.h | 8 ++++----
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 571a7e6..09c023d 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -461,7 +461,6 @@ typedef struct SM501State {
QemuConsole *con;
/* status & internal resources */
- hwaddr base;
uint32_t local_mem_size_index;
uint8_t *local_mem;
MemoryRegion local_mem_region;
@@ -1432,10 +1431,9 @@ static void sm501_reset(SM501State *s)
s->twoD_control = 0;
}
-static void sm501_init(SM501State *s, DeviceState *dev, uint32_t base,
+static void sm501_init(SM501State *s, DeviceState *dev,
uint32_t local_mem_bytes)
{
- s->base = base;
s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
SM501_DPRINTF("sm501 local mem size=%x. index=%d\n", get_local_mem_size(s),
s->local_mem_size_index);
@@ -1489,7 +1487,7 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
DeviceState *usb_dev;
- sm501_init(&s->state, dev, s->base, s->vram_size);
+ sm501_init(&s->state, dev, s->vram_size);
if (get_local_mem_size(&s->state) != s->vram_size) {
error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32,
get_local_mem_size(&s->state));
diff --git a/hw/display/sm501_template.h b/hw/display/sm501_template.h
index 16e500b..832ee61 100644
--- a/hw/display/sm501_template.h
+++ b/hw/display/sm501_template.h
@@ -103,13 +103,13 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State *s, int crt,
uint8_t *palette, int c_y, uint8_t *d, int width)
{
int x, i;
- uint8_t bitset = 0;
+ uint8_t *pixval, bitset = 0;
/* get hardware cursor pattern */
uint32_t cursor_addr = get_hwc_address(s, crt);
assert(0 <= c_y && c_y < SM501_HWC_HEIGHT);
cursor_addr += SM501_HWC_WIDTH * c_y / 4; /* 4 pixels per byte */
- cursor_addr += s->base;
+ pixval = s->local_mem + cursor_addr;
/* get cursor position */
x = get_hwc_x(s, crt);
@@ -120,8 +120,8 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State *s, int crt,
/* get pixel value */
if (i % 4 == 0) {
- bitset = ldub_phys(&address_space_memory, cursor_addr);
- cursor_addr++;
+ bitset = ldub_p(pixval);
+ pixval++;
}
v = bitset & 3;
bitset >>= 2;
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH v7 10/13] sm501: Add support for panel layer
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
` (4 preceding siblings ...)
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 05/13] sm501: Get rid of base address in draw_hwc_line BALATON Zoltan
@ 2017-04-21 15:18 ` BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 03/13] sm501: Add missing arbitration control register BALATON Zoltan
` (8 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2017-04-21 15:18 UTC (permalink / raw)
To: qemu-devel, qemu-trivial
Cc: Magnus Damm, Aurelien Jarno, Peter Maydell, David Gibson
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
---
v2: Split off renaming a variable to separate clean up patch
hw/display/sm501.c | 63 +++++++++++++++++++++++++++---------------------------
1 file changed, 32 insertions(+), 31 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 3974821..7f2e899 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -2,6 +2,7 @@
* QEMU SM501 Device
*
* Copyright (c) 2008 Shin-ichiro KAWASAKI
+ * Copyright (c) 2016 BALATON Zoltan
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -42,8 +43,11 @@
* - Minimum implementation for Linux console : mmio regs and CRT layer.
* - 2D graphics acceleration partially supported : only fill rectangle.
*
- * TODO:
+ * Status: 2016/12/04
+ * - Misc fixes: endianness, hardware cursor
* - Panel support
+ *
+ * TODO:
* - Touch panel support
* - USB support
* - UART support
@@ -1301,18 +1305,16 @@ static inline int get_depth_index(DisplaySurface *surface)
}
}
-static void sm501_draw_crt(SM501State *s)
+static void sm501_update_display(void *opaque)
{
+ SM501State *s = (SM501State *)opaque;
DisplaySurface *surface = qemu_console_surface(s->con);
int y, c_x = 0, c_y = 0;
- uint8_t *hwc_src = NULL, *src = s->local_mem;
- int width = get_width(s, 1);
- int height = get_height(s, 1);
- int src_bpp = get_bpp(s, 1);
+ int crt = (s->dc_crt_control & SM501_DC_CRT_CONTROL_SEL) ? 1 : 0;
+ int width = get_width(s, crt);
+ int height = get_height(s, crt);
+ int src_bpp = get_bpp(s, crt);
int dst_bpp = surface_bytes_per_pixel(surface);
- uint32_t *palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE -
- SM501_DC_PANEL_PALETTE];
- uint8_t hwc_palette[3 * 3];
int dst_depth_index = get_depth_index(surface);
draw_line_func *draw_line = NULL;
draw_hwc_line_func *draw_hwc_line = NULL;
@@ -1320,7 +1322,19 @@ static void sm501_draw_crt(SM501State *s)
int y_start = -1;
ram_addr_t page_min = ~0l;
ram_addr_t page_max = 0l;
- ram_addr_t offset = 0;
+ ram_addr_t offset;
+ uint32_t *palette;
+ uint8_t hwc_palette[3 * 3];
+ uint8_t *hwc_src = NULL;
+
+ if (!((crt ? s->dc_crt_control : s->dc_panel_control)
+ & SM501_DC_CRT_CONTROL_ENABLE)) {
+ return;
+ }
+
+ palette = (uint32_t *)(crt ? &s->dc_palette[SM501_DC_CRT_PALETTE -
+ SM501_DC_PANEL_PALETTE]
+ : &s->dc_palette[0]);
/* choose draw_line function */
switch (src_bpp) {
@@ -1334,20 +1348,19 @@ static void sm501_draw_crt(SM501State *s)
draw_line = draw_line32_funcs[dst_depth_index];
break;
default:
- printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
- s->dc_crt_control);
+ printf("sm501 update display : invalid control register value.\n");
abort();
break;
}
/* set up to draw hardware cursor */
- if (is_hwc_enabled(s, 1)) {
+ if (is_hwc_enabled(s, crt)) {
/* choose cursor draw line function */
draw_hwc_line = draw_hwc_line_funcs[dst_depth_index];
- hwc_src = get_hwc_address(s, 1);
- c_x = get_hwc_x(s, 1);
- c_y = get_hwc_y(s, 1);
- get_hwc_palette(s, 1, hwc_palette);
+ hwc_src = get_hwc_address(s, crt);
+ c_x = get_hwc_x(s, crt);
+ c_y = get_hwc_y(s, crt);
+ get_hwc_palette(s, crt, hwc_palette);
}
/* adjust console size */
@@ -1361,7 +1374,7 @@ static void sm501_draw_crt(SM501State *s)
/* draw each line according to conditions */
memory_region_sync_dirty_bitmap(&s->local_mem_region);
- for (y = 0; y < height; y++) {
+ for (y = 0, offset = 0; y < height; y++, offset += width * src_bpp) {
int update, update_hwc;
ram_addr_t page0 = offset;
ram_addr_t page1 = offset + width * src_bpp - 1;
@@ -1379,7 +1392,7 @@ static void sm501_draw_crt(SM501State *s)
d += y * width * dst_bpp;
/* draw graphics layer */
- draw_line(d, src, width, palette);
+ draw_line(d, s->local_mem + offset, width, palette);
/* draw hardware cursor */
if (update_hwc) {
@@ -1402,9 +1415,6 @@ static void sm501_draw_crt(SM501State *s)
y_start = -1;
}
}
-
- src += width * src_bpp;
- offset += width * src_bpp;
}
/* complete flush to display */
@@ -1420,15 +1430,6 @@ static void sm501_draw_crt(SM501State *s)
}
}
-static void sm501_update_display(void *opaque)
-{
- SM501State *s = (SM501State *)opaque;
-
- if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE) {
- sm501_draw_crt(s);
- }
-}
-
static const GraphicHwOps sm501_ops = {
.gfx_update = sm501_update_display,
};
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH v7 03/13] sm501: Add missing arbitration control register
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
` (5 preceding siblings ...)
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 10/13] sm501: Add support for panel layer BALATON Zoltan
@ 2017-04-21 15:18 ` BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 02/13] sm501: Use defined constants instead of literal values where available BALATON Zoltan
` (7 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2017-04-21 15:18 UTC (permalink / raw)
To: qemu-devel, qemu-trivial
Cc: Magnus Damm, Aurelien Jarno, Peter Maydell, David Gibson
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
---
hw/display/sm501.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 6b72964..6e74200 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -474,6 +474,7 @@ typedef struct SM501State {
uint32_t gpio_31_0_control;
uint32_t gpio_63_32_control;
uint32_t dram_control;
+ uint32_t arbitration_control;
uint32_t irq_mask;
uint32_t misc_timing;
uint32_t power_mode_control;
@@ -757,6 +758,9 @@ static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
case SM501_DRAM_CONTROL:
ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
break;
+ case SM501_ARBTRTN_CONTROL:
+ ret = s->arbitration_control;
+ break;
case SM501_IRQ_MASK:
ret = s->irq_mask;
break;
@@ -809,6 +813,9 @@ static void sm501_system_config_write(void *opaque, hwaddr addr,
/* TODO : check validity of size change */
s->dram_control |= value & 0x7FFFFFC3;
break;
+ case SM501_ARBTRTN_CONTROL:
+ s->arbitration_control = value & 0x37777777;
+ break;
case SM501_IRQ_MASK:
s->irq_mask = value;
break;
@@ -1422,6 +1429,7 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
* BUS = 0 : Hitachi SH3/SH4
*/
s->misc_control = SM501_MISC_DAC_POWER;
+ s->arbitration_control = 0x05146732;
s->dc_panel_control = 0x00010000; /* FIFO level 3 */
s->dc_crt_control = 0x00010000;
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH v7 02/13] sm501: Use defined constants instead of literal values where available
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
` (6 preceding siblings ...)
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 03/13] sm501: Add missing arbitration control register BALATON Zoltan
@ 2017-04-21 15:18 ` BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 07/13] sm501: Fix device endianness BALATON Zoltan
` (6 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2017-04-21 15:18 UTC (permalink / raw)
To: qemu-devel, qemu-trivial
Cc: Magnus Damm, Aurelien Jarno, Peter Maydell, David Gibson
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
---
v3: Fix initial value of misc_control register as Peter Maydell suggested
Also use M_BYTE constant from cutils.h
hw/display/sm501.c | 29 +++++++++++++++++++----------
hw/display/sm501_template.h | 2 +-
2 files changed, 20 insertions(+), 11 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 4f40dee..6b72964 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -23,6 +23,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
@@ -446,12 +447,12 @@
/* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
static const uint32_t sm501_mem_local_size[] = {
- [0] = 4 * 1024 * 1024,
- [1] = 8 * 1024 * 1024,
- [2] = 16 * 1024 * 1024,
- [3] = 32 * 1024 * 1024,
- [4] = 64 * 1024 * 1024,
- [5] = 2 * 1024 * 1024,
+ [0] = 4 * M_BYTE,
+ [1] = 8 * M_BYTE,
+ [2] = 16 * M_BYTE,
+ [3] = 32 * M_BYTE,
+ [4] = 64 * M_BYTE,
+ [5] = 2 * M_BYTE,
};
#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
@@ -555,7 +556,7 @@ static uint32_t get_local_mem_size_index(uint32_t size)
static inline int is_hwc_enabled(SM501State *state, int crt)
{
uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr;
- return addr & 0x80000000;
+ return addr & SM501_HWC_EN;
}
/**
@@ -1411,9 +1412,17 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
s->local_mem_size_index);
- s->system_control = 0x00100000;
- s->misc_control = 0x00001000; /* assumes SH, active=low */
- s->dc_panel_control = 0x00010000;
+ s->system_control = 0x00100000; /* 2D engine FIFO empty */
+ /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
+ * to be determined at reset by GPIO lines which set config bits.
+ * We hardwire them:
+ * SH = 0 : Hitachi Ready Polarity == Active Low
+ * CDR = 0 : do not reset clock divider
+ * TEST = 0 : Normal mode (not testing the silicon)
+ * BUS = 0 : Hitachi SH3/SH4
+ */
+ s->misc_control = SM501_MISC_DAC_POWER;
+ s->dc_panel_control = 0x00010000; /* FIFO level 3 */
s->dc_crt_control = 0x00010000;
/* allocate local memory */
diff --git a/hw/display/sm501_template.h b/hw/display/sm501_template.h
index aeeac5d..16e500b 100644
--- a/hw/display/sm501_template.h
+++ b/hw/display/sm501_template.h
@@ -108,7 +108,7 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State *s, int crt,
/* get hardware cursor pattern */
uint32_t cursor_addr = get_hwc_address(s, crt);
assert(0 <= c_y && c_y < SM501_HWC_HEIGHT);
- cursor_addr += 64 * c_y / 4; /* 4 pixels per byte */
+ cursor_addr += SM501_HWC_WIDTH * c_y / 4; /* 4 pixels per byte */
cursor_addr += s->base;
/* get cursor position */
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH v7 07/13] sm501: Fix device endianness
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
` (7 preceding siblings ...)
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 02/13] sm501: Use defined constants instead of literal values where available BALATON Zoltan
@ 2017-04-21 15:18 ` BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 08/13] sm501: Fix hardware cursor BALATON Zoltan
` (5 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2017-04-21 15:18 UTC (permalink / raw)
To: qemu-devel, qemu-trivial
Cc: Magnus Damm, Aurelien Jarno, Peter Maydell, David Gibson
We only emulate the sysbus device in its default LE mode and PCI is LE
as well so specify this for registers and framebuffer memory.
Note that though the Linux kernel driver has code which claims to
handle both big and little endian, it is obviously bogus for 16 bit
and cannot be trusted as a source of information on the framebuffer
pixel format. This is our best guess about device behaviour based on
the specs and testing with MorphOS that is known to work on real HW.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
---
v2: Split off small clean up to other patch
v4: Set serial part to little endian as well
v5: Make framebuffer always LE as suggested by Peter Maydell
v6: Extended commit message
hw/display/sm501.c | 8 ++++----
hw/display/sm501_template.h | 19 ++++++-------------
2 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index c92a5fa..a628ef1 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -850,7 +850,7 @@ static const MemoryRegionOps sm501_system_config_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
@@ -1086,7 +1086,7 @@ static const MemoryRegionOps sm501_disp_ctrl_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
@@ -1174,7 +1174,7 @@ static const MemoryRegionOps sm501_2d_engine_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
- .endianness = DEVICE_NATIVE_ENDIAN,
+ .endianness = DEVICE_LITTLE_ENDIAN,
};
/* draw line functions for all console modes */
@@ -1510,7 +1510,7 @@ static void sm501_realize_sysbus(DeviceState *dev, Error **errp)
if (s->chr_state) {
serial_mm_init(&s->state.mmio_region, SM501_UART0, 2,
NULL, /* TODO : chain irq to IRL */
- 115200, s->chr_state, DEVICE_NATIVE_ENDIAN);
+ 115200, s->chr_state, DEVICE_LITTLE_ENDIAN);
}
}
diff --git a/hw/display/sm501_template.h b/hw/display/sm501_template.h
index 832ee61..54807bd 100644
--- a/hw/display/sm501_template.h
+++ b/hw/display/sm501_template.h
@@ -64,10 +64,10 @@ static void glue(draw_line16_, PIXEL_NAME)(
uint8_t r, g, b;
do {
- rgb565 = lduw_p(s);
- r = ((rgb565 >> 11) & 0x1f) << 3;
- g = ((rgb565 >> 5) & 0x3f) << 2;
- b = ((rgb565 >> 0) & 0x1f) << 3;
+ rgb565 = lduw_le_p(s);
+ r = (rgb565 >> 8) & 0xf8;
+ g = (rgb565 >> 3) & 0xfc;
+ b = (rgb565 << 3) & 0xf8;
*(PIXEL_TYPE *)d = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
s += 2;
d += BPP;
@@ -80,16 +80,9 @@ static void glue(draw_line32_, PIXEL_NAME)(
uint8_t r, g, b;
do {
- ldub_p(s);
-#if defined(TARGET_WORDS_BIGENDIAN)
- r = s[1];
- g = s[2];
- b = s[3];
-#else
- b = s[0];
- g = s[1];
r = s[2];
-#endif
+ g = s[1];
+ b = s[0];
*(PIXEL_TYPE *)d = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
s += 4;
d += BPP;
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH v7 08/13] sm501: Fix hardware cursor
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
` (8 preceding siblings ...)
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 07/13] sm501: Fix device endianness BALATON Zoltan
@ 2017-04-21 15:18 ` BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 09/13] sm501: Misc clean ups BALATON Zoltan
` (4 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2017-04-21 15:18 UTC (permalink / raw)
To: qemu-devel, qemu-trivial
Cc: Magnus Damm, Aurelien Jarno, Peter Maydell, David Gibson
Rework HWC handling to simplify it and fix cursor not updating on
screen as needed. Previously cursor was not updated because checking
for changes in a line overrode the update flag set for the cursor but
fixing this is not enough because the cursor should also be updated if
its shape or location changes. Introduce hwc_invalidate() function to
handle that similar to other display controller models.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
---
v3: simplify return expression in get_bpp
v7: Avoid some (invalid) warnings with gcc 6 or 7
hw/display/sm501.c | 169 +++++++++++++++++++++++++-------------------
hw/display/sm501_template.h | 25 +++----
2 files changed, 107 insertions(+), 87 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index a628ef1..72e86ba 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -554,6 +554,24 @@ static uint32_t get_local_mem_size_index(uint32_t size)
return index;
}
+static inline int get_width(SM501State *s, int crt)
+{
+ int width = crt ? s->dc_crt_h_total : s->dc_panel_h_total;
+ return (width & 0x00000FFF) + 1;
+}
+
+static inline int get_height(SM501State *s, int crt)
+{
+ int height = crt ? s->dc_crt_v_total : s->dc_panel_v_total;
+ return (height & 0x00000FFF) + 1;
+}
+
+static inline int get_bpp(SM501State *s, int crt)
+{
+ int bpp = crt ? s->dc_crt_control : s->dc_panel_control;
+ return 1 << (bpp & 3);
+}
+
/**
* Check the availability of hardware cursor.
* @param crt 0 for PANEL, 1 for CRT.
@@ -568,10 +586,10 @@ static inline int is_hwc_enabled(SM501State *state, int crt)
* Get the address which holds cursor pattern data.
* @param crt 0 for PANEL, 1 for CRT.
*/
-static inline uint32_t get_hwc_address(SM501State *state, int crt)
+static inline uint8_t *get_hwc_address(SM501State *state, int crt)
{
uint32_t addr = crt ? state->dc_crt_hwc_addr : state->dc_panel_hwc_addr;
- return (addr & 0x03FFFFF0)/* >> 4*/;
+ return state->local_mem + (addr & 0x03FFFFF0);
}
/**
@@ -597,50 +615,48 @@ static inline uint32_t get_hwc_x(SM501State *state, int crt)
}
/**
- * Get the cursor position in x coordinate.
+ * Get the hardware cursor palette.
* @param crt 0 for PANEL, 1 for CRT.
- * @param index 0, 1, 2 or 3 which specifies color of corsor dot.
+ * @param palette pointer to a [3 * 3] array to store color values in
*/
-static inline uint16_t get_hwc_color(SM501State *state, int crt, int index)
+static inline void get_hwc_palette(SM501State *state, int crt, uint8_t *palette)
{
- uint32_t color_reg = 0;
- uint16_t color_565 = 0;
-
- if (index == 0) {
- return 0;
- }
-
- switch (index) {
- case 1:
- case 2:
- color_reg = crt ? state->dc_crt_hwc_color_1_2
- : state->dc_panel_hwc_color_1_2;
- break;
- case 3:
- color_reg = crt ? state->dc_crt_hwc_color_3
- : state->dc_panel_hwc_color_3;
- break;
- default:
- printf("invalid hw cursor color.\n");
- abort();
- }
+ int i;
+ uint32_t color_reg;
+ uint16_t rgb565;
+
+ for (i = 0; i < 3; i++) {
+ if (i + 1 == 3) {
+ color_reg = crt ? state->dc_crt_hwc_color_3
+ : state->dc_panel_hwc_color_3;
+ } else {
+ color_reg = crt ? state->dc_crt_hwc_color_1_2
+ : state->dc_panel_hwc_color_1_2;
+ }
- switch (index) {
- case 1:
- case 3:
- color_565 = (uint16_t)(color_reg & 0xFFFF);
- break;
- case 2:
- color_565 = (uint16_t)((color_reg >> 16) & 0xFFFF);
- break;
+ if (i + 1 == 2) {
+ rgb565 = (color_reg >> 16) & 0xFFFF;
+ } else {
+ rgb565 = color_reg & 0xFFFF;
+ }
+ palette[i * 3 + 0] = (rgb565 << 3) & 0xf8; /* red */
+ palette[i * 3 + 1] = (rgb565 >> 3) & 0xfc; /* green */
+ palette[i * 3 + 2] = (rgb565 >> 8) & 0xf8; /* blue */
}
- return color_565;
}
-static int within_hwc_y_range(SM501State *state, int y, int crt)
+static inline void hwc_invalidate(SM501State *s, int crt)
{
- int hwc_y = get_hwc_y(state, crt);
- return (hwc_y <= y && y < hwc_y + SM501_HWC_HEIGHT);
+ int w = get_width(s, crt);
+ int h = get_height(s, crt);
+ int bpp = get_bpp(s, crt);
+ int start = get_hwc_y(s, crt);
+ int end = MIN(h, start + SM501_HWC_HEIGHT) + 1;
+
+ start *= w * bpp;
+ end *= w * bpp;
+
+ memory_region_set_dirty(&s->local_mem_region, start, end - start);
}
static void sm501_2d_operation(SM501State *s)
@@ -1021,10 +1037,18 @@ static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
break;
case SM501_DC_PANEL_HWC_ADDR:
- s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
+ value &= 0x8FFFFFF0;
+ if (value != s->dc_panel_hwc_addr) {
+ hwc_invalidate(s, 0);
+ s->dc_panel_hwc_addr = value;
+ }
break;
case SM501_DC_PANEL_HWC_LOC:
- s->dc_panel_hwc_location = value & 0x0FFF0FFF;
+ value &= 0x0FFF0FFF;
+ if (value != s->dc_panel_hwc_location) {
+ hwc_invalidate(s, 0);
+ s->dc_panel_hwc_location = value;
+ }
break;
case SM501_DC_PANEL_HWC_COLOR_1_2:
s->dc_panel_hwc_color_1_2 = value;
@@ -1056,10 +1080,18 @@ static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
break;
case SM501_DC_CRT_HWC_ADDR:
- s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
+ value &= 0x8FFFFFF0;
+ if (value != s->dc_crt_hwc_addr) {
+ hwc_invalidate(s, 1);
+ s->dc_crt_hwc_addr = value;
+ }
break;
case SM501_DC_CRT_HWC_LOC:
- s->dc_crt_hwc_location = value & 0x0FFF0FFF;
+ value &= 0x0FFF0FFF;
+ if (value != s->dc_crt_hwc_location) {
+ hwc_invalidate(s, 1);
+ s->dc_crt_hwc_location = value;
+ }
break;
case SM501_DC_CRT_HWC_COLOR_1_2:
s->dc_crt_hwc_color_1_2 = value;
@@ -1182,8 +1214,9 @@ static const MemoryRegionOps sm501_2d_engine_ops = {
typedef void draw_line_func(uint8_t *d, const uint8_t *s,
int width, const uint32_t *pal);
-typedef void draw_hwc_line_func(SM501State *s, int crt, uint8_t *palette,
- int c_y, uint8_t *d, int width);
+typedef void draw_hwc_line_func(uint8_t *d, const uint8_t *s,
+ int width, const uint8_t *palette,
+ int c_x, int c_y);
#define DEPTH 8
#include "sm501_template.h"
@@ -1271,12 +1304,11 @@ static inline int get_depth_index(DisplaySurface *surface)
static void sm501_draw_crt(SM501State *s)
{
DisplaySurface *surface = qemu_console_surface(s->con);
- int y;
- int width = (s->dc_crt_h_total & 0x00000FFF) + 1;
- int height = (s->dc_crt_v_total & 0x00000FFF) + 1;
-
- uint8_t *src = s->local_mem;
- int src_bpp = 0;
+ int y, c_x = 0, c_y = 0;
+ uint8_t *hwc_src = NULL, *src = s->local_mem;
+ int width = get_width(s, 1);
+ int height = get_height(s, 1);
+ int src_bpp = get_bpp(s, 1);
int dst_bpp = surface_bytes_per_pixel(surface);
uint32_t *palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE -
SM501_DC_PANEL_PALETTE];
@@ -1291,17 +1323,14 @@ static void sm501_draw_crt(SM501State *s)
ram_addr_t offset = 0;
/* choose draw_line function */
- switch (s->dc_crt_control & 3) {
- case SM501_DC_CRT_CONTROL_8BPP:
- src_bpp = 1;
+ switch (src_bpp) {
+ case 1:
draw_line = draw_line8_funcs[ds_depth_index];
break;
- case SM501_DC_CRT_CONTROL_16BPP:
- src_bpp = 2;
+ case 2:
draw_line = draw_line16_funcs[ds_depth_index];
break;
- case SM501_DC_CRT_CONTROL_32BPP:
- src_bpp = 4;
+ case 4:
draw_line = draw_line32_funcs[ds_depth_index];
break;
default:
@@ -1313,18 +1342,12 @@ static void sm501_draw_crt(SM501State *s)
/* set up to draw hardware cursor */
if (is_hwc_enabled(s, 1)) {
- int i;
-
- /* get cursor palette */
- for (i = 0; i < 3; i++) {
- uint16_t rgb565 = get_hwc_color(s, 1, i + 1);
- hwc_palette[i * 3 + 0] = (rgb565 & 0xf800) >> 8; /* red */
- hwc_palette[i * 3 + 1] = (rgb565 & 0x07e0) >> 3; /* green */
- hwc_palette[i * 3 + 2] = (rgb565 & 0x001f) << 3; /* blue */
- }
-
/* choose cursor draw line function */
draw_hwc_line = draw_hwc_line_funcs[ds_depth_index];
+ hwc_src = get_hwc_address(s, 1);
+ c_x = get_hwc_x(s, 1);
+ c_y = get_hwc_y(s, 1);
+ get_hwc_palette(s, 1, hwc_palette);
}
/* adjust console size */
@@ -1339,14 +1362,16 @@ static void sm501_draw_crt(SM501State *s)
/* draw each line according to conditions */
memory_region_sync_dirty_bitmap(&s->local_mem_region);
for (y = 0; y < height; y++) {
- int update_hwc = draw_hwc_line ? within_hwc_y_range(s, y, 1) : 0;
- int update = full_update || update_hwc;
+ int update, update_hwc;
ram_addr_t page0 = offset;
ram_addr_t page1 = offset + width * src_bpp - 1;
+ /* check if hardware cursor is enabled and we're within its range */
+ update_hwc = draw_hwc_line && c_y <= y && y < c_y + SM501_HWC_HEIGHT;
+ update = full_update || update_hwc;
/* check dirty flags for each line */
- update = memory_region_get_dirty(&s->local_mem_region, page0,
- page1 - page0, DIRTY_MEMORY_VGA);
+ update |= memory_region_get_dirty(&s->local_mem_region, page0,
+ page1 - page0, DIRTY_MEMORY_VGA);
/* draw line and change status */
if (update) {
@@ -1358,7 +1383,7 @@ static void sm501_draw_crt(SM501State *s)
/* draw hardware cursor */
if (update_hwc) {
- draw_hwc_line(s, 1, hwc_palette, y - get_hwc_y(s, 1), d, width);
+ draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y);
}
if (y_start < 0) {
diff --git a/hw/display/sm501_template.h b/hw/display/sm501_template.h
index 54807bd..fa0d6a9 100644
--- a/hw/display/sm501_template.h
+++ b/hw/display/sm501_template.h
@@ -92,29 +92,24 @@ static void glue(draw_line32_, PIXEL_NAME)(
/**
* Draw hardware cursor image on the given line.
*/
-static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State *s, int crt,
- uint8_t *palette, int c_y, uint8_t *d, int width)
+static void glue(draw_hwc_line_, PIXEL_NAME)(uint8_t *d, const uint8_t *s,
+ int width, const uint8_t *palette, int c_x, int c_y)
{
- int x, i;
- uint8_t *pixval, bitset = 0;
-
- /* get hardware cursor pattern */
- uint32_t cursor_addr = get_hwc_address(s, crt);
- assert(0 <= c_y && c_y < SM501_HWC_HEIGHT);
- cursor_addr += SM501_HWC_WIDTH * c_y / 4; /* 4 pixels per byte */
- pixval = s->local_mem + cursor_addr;
+ int i;
+ uint8_t bitset = 0;
/* get cursor position */
- x = get_hwc_x(s, crt);
- d += x * BPP;
+ assert(0 <= c_y && c_y < SM501_HWC_HEIGHT);
+ s += SM501_HWC_WIDTH * c_y / 4; /* 4 pixels per byte */
+ d += c_x * BPP;
- for (i = 0; i < SM501_HWC_WIDTH && x + i < width; i++) {
+ for (i = 0; i < SM501_HWC_WIDTH && c_x + i < width; i++) {
uint8_t v;
/* get pixel value */
if (i % 4 == 0) {
- bitset = ldub_p(pixval);
- pixval++;
+ bitset = ldub_p(s);
+ s++;
}
v = bitset & 3;
bitset >>= 2;
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH v7 09/13] sm501: Misc clean ups
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
` (9 preceding siblings ...)
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 08/13] sm501: Fix hardware cursor BALATON Zoltan
@ 2017-04-21 15:18 ` BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 06/13] sm501: Add emulation of chip connected via PCI BALATON Zoltan
` (3 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2017-04-21 15:18 UTC (permalink / raw)
To: qemu-devel, qemu-trivial
Cc: Magnus Damm, Aurelien Jarno, Peter Maydell, David Gibson
- Rename a variable
- Move variable declarations out of loop to the beginning in draw_hwc_line
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
---
hw/display/sm501.c | 10 +++++-----
hw/display/sm501_template.h | 10 ++++------
2 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 72e86ba..3974821 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -1313,7 +1313,7 @@ static void sm501_draw_crt(SM501State *s)
uint32_t *palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE -
SM501_DC_PANEL_PALETTE];
uint8_t hwc_palette[3 * 3];
- int ds_depth_index = get_depth_index(surface);
+ int dst_depth_index = get_depth_index(surface);
draw_line_func *draw_line = NULL;
draw_hwc_line_func *draw_hwc_line = NULL;
int full_update = 0;
@@ -1325,13 +1325,13 @@ static void sm501_draw_crt(SM501State *s)
/* choose draw_line function */
switch (src_bpp) {
case 1:
- draw_line = draw_line8_funcs[ds_depth_index];
+ draw_line = draw_line8_funcs[dst_depth_index];
break;
case 2:
- draw_line = draw_line16_funcs[ds_depth_index];
+ draw_line = draw_line16_funcs[dst_depth_index];
break;
case 4:
- draw_line = draw_line32_funcs[ds_depth_index];
+ draw_line = draw_line32_funcs[dst_depth_index];
break;
default:
printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
@@ -1343,7 +1343,7 @@ static void sm501_draw_crt(SM501State *s)
/* set up to draw hardware cursor */
if (is_hwc_enabled(s, 1)) {
/* choose cursor draw line function */
- draw_hwc_line = draw_hwc_line_funcs[ds_depth_index];
+ draw_hwc_line = draw_hwc_line_funcs[dst_depth_index];
hwc_src = get_hwc_address(s, 1);
c_x = get_hwc_x(s, 1);
c_y = get_hwc_y(s, 1);
diff --git a/hw/display/sm501_template.h b/hw/display/sm501_template.h
index fa0d6a9..a60abad 100644
--- a/hw/display/sm501_template.h
+++ b/hw/display/sm501_template.h
@@ -96,7 +96,7 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(uint8_t *d, const uint8_t *s,
int width, const uint8_t *palette, int c_x, int c_y)
{
int i;
- uint8_t bitset = 0;
+ uint8_t r, g, b, v, bitset = 0;
/* get cursor position */
assert(0 <= c_y && c_y < SM501_HWC_HEIGHT);
@@ -104,8 +104,6 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(uint8_t *d, const uint8_t *s,
d += c_x * BPP;
for (i = 0; i < SM501_HWC_WIDTH && c_x + i < width; i++) {
- uint8_t v;
-
/* get pixel value */
if (i % 4 == 0) {
bitset = ldub_p(s);
@@ -117,9 +115,9 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(uint8_t *d, const uint8_t *s,
/* write pixel */
if (v) {
v--;
- uint8_t r = palette[v * 3 + 0];
- uint8_t g = palette[v * 3 + 1];
- uint8_t b = palette[v * 3 + 2];
+ r = palette[v * 3 + 0];
+ g = palette[v * 3 + 1];
+ b = palette[v * 3 + 2];
*(PIXEL_TYPE *)d = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
}
d += BPP;
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH v7 06/13] sm501: Add emulation of chip connected via PCI
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
` (10 preceding siblings ...)
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 09/13] sm501: Misc clean ups BALATON Zoltan
@ 2017-04-21 15:18 ` BALATON Zoltan
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 01/13] sm501: Fixed code style and a few typos in comments BALATON Zoltan
` (2 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2017-04-21 15:18 UTC (permalink / raw)
To: qemu-devel, qemu-trivial
Cc: Magnus Damm, Aurelien Jarno, Peter Maydell, David Gibson
Only the display controller part is created automatically on PCI
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
---
v2: Split off removing dependency on base address to separate patch
v3: Added reset function and PCI ID constant definitions in pci_ids.h
v4: Return error for invalid VRAM size, set bit in misc_control for PCI bus
hw/display/sm501.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/pci/pci_ids.h | 3 +++
2 files changed, 68 insertions(+)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 09c023d..c92a5fa 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -32,6 +32,7 @@
#include "ui/console.h"
#include "hw/devices.h"
#include "hw/sysbus.h"
+#include "hw/pci/pci.h"
#include "qemu/range.h"
#include "ui/pixel_ops.h"
#include "exec/address-spaces.h"
@@ -1547,9 +1548,73 @@ static const TypeInfo sm501_sysbus_info = {
.class_init = sm501_sysbus_class_init,
};
+#define TYPE_PCI_SM501 "sm501"
+#define PCI_SM501(obj) OBJECT_CHECK(SM501PCIState, (obj), TYPE_PCI_SM501)
+
+typedef struct {
+ /*< private >*/
+ PCIDevice parent_obj;
+ /*< public >*/
+ SM501State state;
+ uint32_t vram_size;
+} SM501PCIState;
+
+static void sm501_realize_pci(PCIDevice *dev, Error **errp)
+{
+ SM501PCIState *s = PCI_SM501(dev);
+
+ sm501_init(&s->state, DEVICE(dev), s->vram_size);
+ if (get_local_mem_size(&s->state) != s->vram_size) {
+ error_setg(errp, "Invalid VRAM size, nearest valid size is %" PRIu32,
+ get_local_mem_size(&s->state));
+ return;
+ }
+ pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY,
+ &s->state.local_mem_region);
+ pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY,
+ &s->state.mmio_region);
+}
+
+static Property sm501_pci_properties[] = {
+ DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * M_BYTE),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void sm501_reset_pci(DeviceState *dev)
+{
+ SM501PCIState *s = PCI_SM501(dev);
+ sm501_reset(&s->state);
+ /* Bits 2:0 of misc_control register is 001 for PCI */
+ s->state.misc_control |= 1;
+}
+
+static void sm501_pci_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->realize = sm501_realize_pci;
+ k->vendor_id = PCI_VENDOR_ID_SILICON_MOTION;
+ k->device_id = PCI_DEVICE_ID_SM501;
+ k->class_id = PCI_CLASS_DISPLAY_OTHER;
+ set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
+ dc->desc = "SM501 Display Controller";
+ dc->props = sm501_pci_properties;
+ dc->reset = sm501_reset_pci;
+ dc->hotpluggable = false;
+}
+
+static const TypeInfo sm501_pci_info = {
+ .name = TYPE_PCI_SM501,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(SM501PCIState),
+ .class_init = sm501_pci_class_init,
+};
+
static void sm501_register_types(void)
{
type_register_static(&sm501_sysbus_info);
+ type_register_static(&sm501_pci_info);
}
type_init(sm501_register_types)
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
index d22ad8d..3752ddc 100644
--- a/include/hw/pci/pci_ids.h
+++ b/include/hw/pci/pci_ids.h
@@ -207,6 +207,9 @@
#define PCI_VENDOR_ID_MARVELL 0x11ab
+#define PCI_VENDOR_ID_SILICON_MOTION 0x126f
+#define PCI_DEVICE_ID_SM501 0x0501
+
#define PCI_VENDOR_ID_ENSONIQ 0x1274
#define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH v7 01/13] sm501: Fixed code style and a few typos in comments
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
` (11 preceding siblings ...)
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 06/13] sm501: Add emulation of chip connected via PCI BALATON Zoltan
@ 2017-04-21 15:18 ` BALATON Zoltan
2017-04-22 15:41 ` [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation Aurelien Jarno
2017-04-24 12:09 ` Peter Maydell
14 siblings, 0 replies; 16+ messages in thread
From: BALATON Zoltan @ 2017-04-21 15:18 UTC (permalink / raw)
To: qemu-devel, qemu-trivial
Cc: Magnus Damm, Aurelien Jarno, Peter Maydell, David Gibson
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
---
hw/display/sm501.c | 1132 ++++++++++++++++++++++---------------------
hw/display/sm501_template.h | 52 +-
2 files changed, 594 insertions(+), 590 deletions(-)
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 040a0b9..4f40dee 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -38,7 +38,7 @@
/*
* Status: 2010/05/07
* - Minimum implementation for Linux console : mmio regs and CRT layer.
- * - 2D grapihcs acceleration partially supported : only fill rectangle.
+ * - 2D graphics acceleration partially supported : only fill rectangle.
*
* TODO:
* - Panel support
@@ -49,13 +49,13 @@
* - Performance tuning
*/
-//#define DEBUG_SM501
-//#define DEBUG_BITBLT
+/*#define DEBUG_SM501*/
+/*#define DEBUG_BITBLT*/
#ifdef DEBUG_SM501
#define SM501_DPRINTF(fmt, ...) printf(fmt, ## __VA_ARGS__)
#else
-#define SM501_DPRINTF(fmt, ...) do {} while(0)
+#define SM501_DPRINTF(fmt, ...) do {} while (0)
#endif
@@ -65,379 +65,379 @@
/* System Configuration area */
/* System config base */
-#define SM501_SYS_CONFIG (0x000000)
+#define SM501_SYS_CONFIG (0x000000)
/* config 1 */
-#define SM501_SYSTEM_CONTROL (0x000000)
+#define SM501_SYSTEM_CONTROL (0x000000)
-#define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
-#define SM501_SYSCTRL_MEM_TRISTATE (1<<1)
-#define SM501_SYSCTRL_CRT_TRISTATE (1<<2)
+#define SM501_SYSCTRL_PANEL_TRISTATE (1 << 0)
+#define SM501_SYSCTRL_MEM_TRISTATE (1 << 1)
+#define SM501_SYSCTRL_CRT_TRISTATE (1 << 2)
-#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
-#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
-#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4)
-#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4)
-#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 << 4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 << 4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 << 4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 << 4)
+#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 << 4)
-#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6)
-#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7)
-#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11)
-#define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15)
+#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 << 6)
+#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 << 7)
+#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 << 11)
+#define SM501_SYSCTRL_PCI_BURST_READ_EN (1 << 15)
/* miscellaneous control */
-#define SM501_MISC_CONTROL (0x000004)
+#define SM501_MISC_CONTROL (0x000004)
-#define SM501_MISC_BUS_SH (0x0)
-#define SM501_MISC_BUS_PCI (0x1)
-#define SM501_MISC_BUS_XSCALE (0x2)
-#define SM501_MISC_BUS_NEC (0x6)
-#define SM501_MISC_BUS_MASK (0x7)
+#define SM501_MISC_BUS_SH (0x0)
+#define SM501_MISC_BUS_PCI (0x1)
+#define SM501_MISC_BUS_XSCALE (0x2)
+#define SM501_MISC_BUS_NEC (0x6)
+#define SM501_MISC_BUS_MASK (0x7)
-#define SM501_MISC_VR_62MB (1<<3)
-#define SM501_MISC_CDR_RESET (1<<7)
-#define SM501_MISC_USB_LB (1<<8)
-#define SM501_MISC_USB_SLAVE (1<<9)
-#define SM501_MISC_BL_1 (1<<10)
-#define SM501_MISC_MC (1<<11)
-#define SM501_MISC_DAC_POWER (1<<12)
-#define SM501_MISC_IRQ_INVERT (1<<16)
-#define SM501_MISC_SH (1<<17)
+#define SM501_MISC_VR_62MB (1 << 3)
+#define SM501_MISC_CDR_RESET (1 << 7)
+#define SM501_MISC_USB_LB (1 << 8)
+#define SM501_MISC_USB_SLAVE (1 << 9)
+#define SM501_MISC_BL_1 (1 << 10)
+#define SM501_MISC_MC (1 << 11)
+#define SM501_MISC_DAC_POWER (1 << 12)
+#define SM501_MISC_IRQ_INVERT (1 << 16)
+#define SM501_MISC_SH (1 << 17)
-#define SM501_MISC_HOLD_EMPTY (0<<18)
-#define SM501_MISC_HOLD_8 (1<<18)
-#define SM501_MISC_HOLD_16 (2<<18)
-#define SM501_MISC_HOLD_24 (3<<18)
-#define SM501_MISC_HOLD_32 (4<<18)
-#define SM501_MISC_HOLD_MASK (7<<18)
+#define SM501_MISC_HOLD_EMPTY (0 << 18)
+#define SM501_MISC_HOLD_8 (1 << 18)
+#define SM501_MISC_HOLD_16 (2 << 18)
+#define SM501_MISC_HOLD_24 (3 << 18)
+#define SM501_MISC_HOLD_32 (4 << 18)
+#define SM501_MISC_HOLD_MASK (7 << 18)
-#define SM501_MISC_FREQ_12 (1<<24)
-#define SM501_MISC_PNL_24BIT (1<<25)
-#define SM501_MISC_8051_LE (1<<26)
+#define SM501_MISC_FREQ_12 (1 << 24)
+#define SM501_MISC_PNL_24BIT (1 << 25)
+#define SM501_MISC_8051_LE (1 << 26)
-#define SM501_GPIO31_0_CONTROL (0x000008)
-#define SM501_GPIO63_32_CONTROL (0x00000C)
-#define SM501_DRAM_CONTROL (0x000010)
+#define SM501_GPIO31_0_CONTROL (0x000008)
+#define SM501_GPIO63_32_CONTROL (0x00000C)
+#define SM501_DRAM_CONTROL (0x000010)
/* command list */
-#define SM501_ARBTRTN_CONTROL (0x000014)
+#define SM501_ARBTRTN_CONTROL (0x000014)
/* command list */
-#define SM501_COMMAND_LIST_STATUS (0x000024)
+#define SM501_COMMAND_LIST_STATUS (0x000024)
/* interrupt debug */
-#define SM501_RAW_IRQ_STATUS (0x000028)
-#define SM501_RAW_IRQ_CLEAR (0x000028)
-#define SM501_IRQ_STATUS (0x00002C)
-#define SM501_IRQ_MASK (0x000030)
-#define SM501_DEBUG_CONTROL (0x000034)
+#define SM501_RAW_IRQ_STATUS (0x000028)
+#define SM501_RAW_IRQ_CLEAR (0x000028)
+#define SM501_IRQ_STATUS (0x00002C)
+#define SM501_IRQ_MASK (0x000030)
+#define SM501_DEBUG_CONTROL (0x000034)
/* power management */
-#define SM501_POWERMODE_P2X_SRC (1<<29)
-#define SM501_POWERMODE_V2X_SRC (1<<20)
-#define SM501_POWERMODE_M_SRC (1<<12)
-#define SM501_POWERMODE_M1_SRC (1<<4)
-
-#define SM501_CURRENT_GATE (0x000038)
-#define SM501_CURRENT_CLOCK (0x00003C)
-#define SM501_POWER_MODE_0_GATE (0x000040)
-#define SM501_POWER_MODE_0_CLOCK (0x000044)
-#define SM501_POWER_MODE_1_GATE (0x000048)
-#define SM501_POWER_MODE_1_CLOCK (0x00004C)
-#define SM501_SLEEP_MODE_GATE (0x000050)
-#define SM501_POWER_MODE_CONTROL (0x000054)
+#define SM501_POWERMODE_P2X_SRC (1 << 29)
+#define SM501_POWERMODE_V2X_SRC (1 << 20)
+#define SM501_POWERMODE_M_SRC (1 << 12)
+#define SM501_POWERMODE_M1_SRC (1 << 4)
+
+#define SM501_CURRENT_GATE (0x000038)
+#define SM501_CURRENT_CLOCK (0x00003C)
+#define SM501_POWER_MODE_0_GATE (0x000040)
+#define SM501_POWER_MODE_0_CLOCK (0x000044)
+#define SM501_POWER_MODE_1_GATE (0x000048)
+#define SM501_POWER_MODE_1_CLOCK (0x00004C)
+#define SM501_SLEEP_MODE_GATE (0x000050)
+#define SM501_POWER_MODE_CONTROL (0x000054)
/* power gates for units within the 501 */
-#define SM501_GATE_HOST (0)
-#define SM501_GATE_MEMORY (1)
-#define SM501_GATE_DISPLAY (2)
-#define SM501_GATE_2D_ENGINE (3)
-#define SM501_GATE_CSC (4)
-#define SM501_GATE_ZVPORT (5)
-#define SM501_GATE_GPIO (6)
-#define SM501_GATE_UART0 (7)
-#define SM501_GATE_UART1 (8)
-#define SM501_GATE_SSP (10)
-#define SM501_GATE_USB_HOST (11)
-#define SM501_GATE_USB_GADGET (12)
-#define SM501_GATE_UCONTROLLER (17)
-#define SM501_GATE_AC97 (18)
+#define SM501_GATE_HOST (0)
+#define SM501_GATE_MEMORY (1)
+#define SM501_GATE_DISPLAY (2)
+#define SM501_GATE_2D_ENGINE (3)
+#define SM501_GATE_CSC (4)
+#define SM501_GATE_ZVPORT (5)
+#define SM501_GATE_GPIO (6)
+#define SM501_GATE_UART0 (7)
+#define SM501_GATE_UART1 (8)
+#define SM501_GATE_SSP (10)
+#define SM501_GATE_USB_HOST (11)
+#define SM501_GATE_USB_GADGET (12)
+#define SM501_GATE_UCONTROLLER (17)
+#define SM501_GATE_AC97 (18)
/* panel clock */
-#define SM501_CLOCK_P2XCLK (24)
+#define SM501_CLOCK_P2XCLK (24)
/* crt clock */
-#define SM501_CLOCK_V2XCLK (16)
+#define SM501_CLOCK_V2XCLK (16)
/* main clock */
-#define SM501_CLOCK_MCLK (8)
+#define SM501_CLOCK_MCLK (8)
/* SDRAM controller clock */
-#define SM501_CLOCK_M1XCLK (0)
+#define SM501_CLOCK_M1XCLK (0)
/* config 2 */
-#define SM501_PCI_MASTER_BASE (0x000058)
-#define SM501_ENDIAN_CONTROL (0x00005C)
-#define SM501_DEVICEID (0x000060)
+#define SM501_PCI_MASTER_BASE (0x000058)
+#define SM501_ENDIAN_CONTROL (0x00005C)
+#define SM501_DEVICEID (0x000060)
/* 0x050100A0 */
-#define SM501_DEVICEID_SM501 (0x05010000)
-#define SM501_DEVICEID_IDMASK (0xffff0000)
-#define SM501_DEVICEID_REVMASK (0x000000ff)
+#define SM501_DEVICEID_SM501 (0x05010000)
+#define SM501_DEVICEID_IDMASK (0xffff0000)
+#define SM501_DEVICEID_REVMASK (0x000000ff)
-#define SM501_PLLCLOCK_COUNT (0x000064)
-#define SM501_MISC_TIMING (0x000068)
-#define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
+#define SM501_PLLCLOCK_COUNT (0x000064)
+#define SM501_MISC_TIMING (0x000068)
+#define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
-#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
+#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
/* GPIO base */
-#define SM501_GPIO (0x010000)
-#define SM501_GPIO_DATA_LOW (0x00)
-#define SM501_GPIO_DATA_HIGH (0x04)
-#define SM501_GPIO_DDR_LOW (0x08)
-#define SM501_GPIO_DDR_HIGH (0x0C)
-#define SM501_GPIO_IRQ_SETUP (0x10)
-#define SM501_GPIO_IRQ_STATUS (0x14)
-#define SM501_GPIO_IRQ_RESET (0x14)
+#define SM501_GPIO (0x010000)
+#define SM501_GPIO_DATA_LOW (0x00)
+#define SM501_GPIO_DATA_HIGH (0x04)
+#define SM501_GPIO_DDR_LOW (0x08)
+#define SM501_GPIO_DDR_HIGH (0x0C)
+#define SM501_GPIO_IRQ_SETUP (0x10)
+#define SM501_GPIO_IRQ_STATUS (0x14)
+#define SM501_GPIO_IRQ_RESET (0x14)
/* I2C controller base */
-#define SM501_I2C (0x010040)
-#define SM501_I2C_BYTE_COUNT (0x00)
-#define SM501_I2C_CONTROL (0x01)
-#define SM501_I2C_STATUS (0x02)
-#define SM501_I2C_RESET (0x02)
-#define SM501_I2C_SLAVE_ADDRESS (0x03)
-#define SM501_I2C_DATA (0x04)
+#define SM501_I2C (0x010040)
+#define SM501_I2C_BYTE_COUNT (0x00)
+#define SM501_I2C_CONTROL (0x01)
+#define SM501_I2C_STATUS (0x02)
+#define SM501_I2C_RESET (0x02)
+#define SM501_I2C_SLAVE_ADDRESS (0x03)
+#define SM501_I2C_DATA (0x04)
/* SSP base */
-#define SM501_SSP (0x020000)
+#define SM501_SSP (0x020000)
/* Uart 0 base */
-#define SM501_UART0 (0x030000)
+#define SM501_UART0 (0x030000)
/* Uart 1 base */
-#define SM501_UART1 (0x030020)
+#define SM501_UART1 (0x030020)
/* USB host port base */
-#define SM501_USB_HOST (0x040000)
+#define SM501_USB_HOST (0x040000)
/* USB slave/gadget base */
-#define SM501_USB_GADGET (0x060000)
+#define SM501_USB_GADGET (0x060000)
/* USB slave/gadget data port base */
-#define SM501_USB_GADGET_DATA (0x070000)
+#define SM501_USB_GADGET_DATA (0x070000)
/* Display controller/video engine base */
-#define SM501_DC (0x080000)
+#define SM501_DC (0x080000)
/* common defines for the SM501 address registers */
-#define SM501_ADDR_FLIP (1<<31)
-#define SM501_ADDR_EXT (1<<27)
-#define SM501_ADDR_CS1 (1<<26)
-#define SM501_ADDR_MASK (0x3f << 26)
+#define SM501_ADDR_FLIP (1 << 31)
+#define SM501_ADDR_EXT (1 << 27)
+#define SM501_ADDR_CS1 (1 << 26)
+#define SM501_ADDR_MASK (0x3f << 26)
-#define SM501_FIFO_MASK (0x3 << 16)
-#define SM501_FIFO_1 (0x0 << 16)
-#define SM501_FIFO_3 (0x1 << 16)
-#define SM501_FIFO_7 (0x2 << 16)
-#define SM501_FIFO_11 (0x3 << 16)
+#define SM501_FIFO_MASK (0x3 << 16)
+#define SM501_FIFO_1 (0x0 << 16)
+#define SM501_FIFO_3 (0x1 << 16)
+#define SM501_FIFO_7 (0x2 << 16)
+#define SM501_FIFO_11 (0x3 << 16)
/* common registers for panel and the crt */
-#define SM501_OFF_DC_H_TOT (0x000)
-#define SM501_OFF_DC_V_TOT (0x008)
-#define SM501_OFF_DC_H_SYNC (0x004)
-#define SM501_OFF_DC_V_SYNC (0x00C)
-
-#define SM501_DC_PANEL_CONTROL (0x000)
-
-#define SM501_DC_PANEL_CONTROL_FPEN (1<<27)
-#define SM501_DC_PANEL_CONTROL_BIAS (1<<26)
-#define SM501_DC_PANEL_CONTROL_DATA (1<<25)
-#define SM501_DC_PANEL_CONTROL_VDD (1<<24)
-#define SM501_DC_PANEL_CONTROL_DP (1<<23)
-
-#define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21)
-#define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21)
-#define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21)
-
-#define SM501_DC_PANEL_CONTROL_DE (1<<20)
-
-#define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18)
-#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
-#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
-
-#define SM501_DC_PANEL_CONTROL_CP (1<<14)
-#define SM501_DC_PANEL_CONTROL_VSP (1<<13)
-#define SM501_DC_PANEL_CONTROL_HSP (1<<12)
-#define SM501_DC_PANEL_CONTROL_CK (1<<9)
-#define SM501_DC_PANEL_CONTROL_TE (1<<8)
-#define SM501_DC_PANEL_CONTROL_VPD (1<<7)
-#define SM501_DC_PANEL_CONTROL_VP (1<<6)
-#define SM501_DC_PANEL_CONTROL_HPD (1<<5)
-#define SM501_DC_PANEL_CONTROL_HP (1<<4)
-#define SM501_DC_PANEL_CONTROL_GAMMA (1<<3)
-#define SM501_DC_PANEL_CONTROL_EN (1<<2)
-
-#define SM501_DC_PANEL_CONTROL_8BPP (0<<0)
-#define SM501_DC_PANEL_CONTROL_16BPP (1<<0)
-#define SM501_DC_PANEL_CONTROL_32BPP (2<<0)
-
-
-#define SM501_DC_PANEL_PANNING_CONTROL (0x004)
-#define SM501_DC_PANEL_COLOR_KEY (0x008)
-#define SM501_DC_PANEL_FB_ADDR (0x00C)
-#define SM501_DC_PANEL_FB_OFFSET (0x010)
-#define SM501_DC_PANEL_FB_WIDTH (0x014)
-#define SM501_DC_PANEL_FB_HEIGHT (0x018)
-#define SM501_DC_PANEL_TL_LOC (0x01C)
-#define SM501_DC_PANEL_BR_LOC (0x020)
-#define SM501_DC_PANEL_H_TOT (0x024)
-#define SM501_DC_PANEL_H_SYNC (0x028)
-#define SM501_DC_PANEL_V_TOT (0x02C)
-#define SM501_DC_PANEL_V_SYNC (0x030)
-#define SM501_DC_PANEL_CUR_LINE (0x034)
-
-#define SM501_DC_VIDEO_CONTROL (0x040)
-#define SM501_DC_VIDEO_FB0_ADDR (0x044)
-#define SM501_DC_VIDEO_FB_WIDTH (0x048)
-#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
-#define SM501_DC_VIDEO_TL_LOC (0x050)
-#define SM501_DC_VIDEO_BR_LOC (0x054)
-#define SM501_DC_VIDEO_SCALE (0x058)
-#define SM501_DC_VIDEO_INIT_SCALE (0x05C)
-#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
-#define SM501_DC_VIDEO_FB1_ADDR (0x064)
-#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
-
-#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
-#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
-#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
-#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
-#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
-#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
-#define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
-#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
-#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
-#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
-
-#define SM501_DC_PANEL_HWC_BASE (0x0F0)
-#define SM501_DC_PANEL_HWC_ADDR (0x0F0)
-#define SM501_DC_PANEL_HWC_LOC (0x0F4)
-#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
-#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
-
-#define SM501_HWC_EN (1<<31)
-
-#define SM501_OFF_HWC_ADDR (0x00)
-#define SM501_OFF_HWC_LOC (0x04)
-#define SM501_OFF_HWC_COLOR_1_2 (0x08)
-#define SM501_OFF_HWC_COLOR_3 (0x0C)
-
-#define SM501_DC_ALPHA_CONTROL (0x100)
-#define SM501_DC_ALPHA_FB_ADDR (0x104)
-#define SM501_DC_ALPHA_FB_OFFSET (0x108)
-#define SM501_DC_ALPHA_TL_LOC (0x10C)
-#define SM501_DC_ALPHA_BR_LOC (0x110)
-#define SM501_DC_ALPHA_CHROMA_KEY (0x114)
-#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
-
-#define SM501_DC_CRT_CONTROL (0x200)
-
-#define SM501_DC_CRT_CONTROL_TVP (1<<15)
-#define SM501_DC_CRT_CONTROL_CP (1<<14)
-#define SM501_DC_CRT_CONTROL_VSP (1<<13)
-#define SM501_DC_CRT_CONTROL_HSP (1<<12)
-#define SM501_DC_CRT_CONTROL_VS (1<<11)
-#define SM501_DC_CRT_CONTROL_BLANK (1<<10)
-#define SM501_DC_CRT_CONTROL_SEL (1<<9)
-#define SM501_DC_CRT_CONTROL_TE (1<<8)
+#define SM501_OFF_DC_H_TOT (0x000)
+#define SM501_OFF_DC_V_TOT (0x008)
+#define SM501_OFF_DC_H_SYNC (0x004)
+#define SM501_OFF_DC_V_SYNC (0x00C)
+
+#define SM501_DC_PANEL_CONTROL (0x000)
+
+#define SM501_DC_PANEL_CONTROL_FPEN (1 << 27)
+#define SM501_DC_PANEL_CONTROL_BIAS (1 << 26)
+#define SM501_DC_PANEL_CONTROL_DATA (1 << 25)
+#define SM501_DC_PANEL_CONTROL_VDD (1 << 24)
+#define SM501_DC_PANEL_CONTROL_DP (1 << 23)
+
+#define SM501_DC_PANEL_CONTROL_TFT_888 (0 << 21)
+#define SM501_DC_PANEL_CONTROL_TFT_333 (1 << 21)
+#define SM501_DC_PANEL_CONTROL_TFT_444 (2 << 21)
+
+#define SM501_DC_PANEL_CONTROL_DE (1 << 20)
+
+#define SM501_DC_PANEL_CONTROL_LCD_TFT (0 << 18)
+#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 << 18)
+#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 << 18)
+
+#define SM501_DC_PANEL_CONTROL_CP (1 << 14)
+#define SM501_DC_PANEL_CONTROL_VSP (1 << 13)
+#define SM501_DC_PANEL_CONTROL_HSP (1 << 12)
+#define SM501_DC_PANEL_CONTROL_CK (1 << 9)
+#define SM501_DC_PANEL_CONTROL_TE (1 << 8)
+#define SM501_DC_PANEL_CONTROL_VPD (1 << 7)
+#define SM501_DC_PANEL_CONTROL_VP (1 << 6)
+#define SM501_DC_PANEL_CONTROL_HPD (1 << 5)
+#define SM501_DC_PANEL_CONTROL_HP (1 << 4)
+#define SM501_DC_PANEL_CONTROL_GAMMA (1 << 3)
+#define SM501_DC_PANEL_CONTROL_EN (1 << 2)
+
+#define SM501_DC_PANEL_CONTROL_8BPP (0 << 0)
+#define SM501_DC_PANEL_CONTROL_16BPP (1 << 0)
+#define SM501_DC_PANEL_CONTROL_32BPP (2 << 0)
+
+
+#define SM501_DC_PANEL_PANNING_CONTROL (0x004)
+#define SM501_DC_PANEL_COLOR_KEY (0x008)
+#define SM501_DC_PANEL_FB_ADDR (0x00C)
+#define SM501_DC_PANEL_FB_OFFSET (0x010)
+#define SM501_DC_PANEL_FB_WIDTH (0x014)
+#define SM501_DC_PANEL_FB_HEIGHT (0x018)
+#define SM501_DC_PANEL_TL_LOC (0x01C)
+#define SM501_DC_PANEL_BR_LOC (0x020)
+#define SM501_DC_PANEL_H_TOT (0x024)
+#define SM501_DC_PANEL_H_SYNC (0x028)
+#define SM501_DC_PANEL_V_TOT (0x02C)
+#define SM501_DC_PANEL_V_SYNC (0x030)
+#define SM501_DC_PANEL_CUR_LINE (0x034)
+
+#define SM501_DC_VIDEO_CONTROL (0x040)
+#define SM501_DC_VIDEO_FB0_ADDR (0x044)
+#define SM501_DC_VIDEO_FB_WIDTH (0x048)
+#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
+#define SM501_DC_VIDEO_TL_LOC (0x050)
+#define SM501_DC_VIDEO_BR_LOC (0x054)
+#define SM501_DC_VIDEO_SCALE (0x058)
+#define SM501_DC_VIDEO_INIT_SCALE (0x05C)
+#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
+#define SM501_DC_VIDEO_FB1_ADDR (0x064)
+#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
+
+#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
+#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
+#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
+#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
+#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
+#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
+#define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
+#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
+#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
+#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
+
+#define SM501_DC_PANEL_HWC_BASE (0x0F0)
+#define SM501_DC_PANEL_HWC_ADDR (0x0F0)
+#define SM501_DC_PANEL_HWC_LOC (0x0F4)
+#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
+#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
+
+#define SM501_HWC_EN (1 << 31)
+
+#define SM501_OFF_HWC_ADDR (0x00)
+#define SM501_OFF_HWC_LOC (0x04)
+#define SM501_OFF_HWC_COLOR_1_2 (0x08)
+#define SM501_OFF_HWC_COLOR_3 (0x0C)
+
+#define SM501_DC_ALPHA_CONTROL (0x100)
+#define SM501_DC_ALPHA_FB_ADDR (0x104)
+#define SM501_DC_ALPHA_FB_OFFSET (0x108)
+#define SM501_DC_ALPHA_TL_LOC (0x10C)
+#define SM501_DC_ALPHA_BR_LOC (0x110)
+#define SM501_DC_ALPHA_CHROMA_KEY (0x114)
+#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
+
+#define SM501_DC_CRT_CONTROL (0x200)
+
+#define SM501_DC_CRT_CONTROL_TVP (1 << 15)
+#define SM501_DC_CRT_CONTROL_CP (1 << 14)
+#define SM501_DC_CRT_CONTROL_VSP (1 << 13)
+#define SM501_DC_CRT_CONTROL_HSP (1 << 12)
+#define SM501_DC_CRT_CONTROL_VS (1 << 11)
+#define SM501_DC_CRT_CONTROL_BLANK (1 << 10)
+#define SM501_DC_CRT_CONTROL_SEL (1 << 9)
+#define SM501_DC_CRT_CONTROL_TE (1 << 8)
#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
-#define SM501_DC_CRT_CONTROL_GAMMA (1<<3)
-#define SM501_DC_CRT_CONTROL_ENABLE (1<<2)
+#define SM501_DC_CRT_CONTROL_GAMMA (1 << 3)
+#define SM501_DC_CRT_CONTROL_ENABLE (1 << 2)
-#define SM501_DC_CRT_CONTROL_8BPP (0<<0)
-#define SM501_DC_CRT_CONTROL_16BPP (1<<0)
-#define SM501_DC_CRT_CONTROL_32BPP (2<<0)
+#define SM501_DC_CRT_CONTROL_8BPP (0 << 0)
+#define SM501_DC_CRT_CONTROL_16BPP (1 << 0)
+#define SM501_DC_CRT_CONTROL_32BPP (2 << 0)
-#define SM501_DC_CRT_FB_ADDR (0x204)
-#define SM501_DC_CRT_FB_OFFSET (0x208)
-#define SM501_DC_CRT_H_TOT (0x20C)
-#define SM501_DC_CRT_H_SYNC (0x210)
-#define SM501_DC_CRT_V_TOT (0x214)
-#define SM501_DC_CRT_V_SYNC (0x218)
-#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
-#define SM501_DC_CRT_CUR_LINE (0x220)
-#define SM501_DC_CRT_MONITOR_DETECT (0x224)
+#define SM501_DC_CRT_FB_ADDR (0x204)
+#define SM501_DC_CRT_FB_OFFSET (0x208)
+#define SM501_DC_CRT_H_TOT (0x20C)
+#define SM501_DC_CRT_H_SYNC (0x210)
+#define SM501_DC_CRT_V_TOT (0x214)
+#define SM501_DC_CRT_V_SYNC (0x218)
+#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
+#define SM501_DC_CRT_CUR_LINE (0x220)
+#define SM501_DC_CRT_MONITOR_DETECT (0x224)
-#define SM501_DC_CRT_HWC_BASE (0x230)
-#define SM501_DC_CRT_HWC_ADDR (0x230)
-#define SM501_DC_CRT_HWC_LOC (0x234)
-#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
-#define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
+#define SM501_DC_CRT_HWC_BASE (0x230)
+#define SM501_DC_CRT_HWC_ADDR (0x230)
+#define SM501_DC_CRT_HWC_LOC (0x234)
+#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
+#define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
-#define SM501_DC_PANEL_PALETTE (0x400)
+#define SM501_DC_PANEL_PALETTE (0x400)
-#define SM501_DC_VIDEO_PALETTE (0x800)
+#define SM501_DC_VIDEO_PALETTE (0x800)
-#define SM501_DC_CRT_PALETTE (0xC00)
+#define SM501_DC_CRT_PALETTE (0xC00)
/* Zoom Video port base */
-#define SM501_ZVPORT (0x090000)
+#define SM501_ZVPORT (0x090000)
/* AC97/I2S base */
-#define SM501_AC97 (0x0A0000)
+#define SM501_AC97 (0x0A0000)
/* 8051 micro controller base */
-#define SM501_UCONTROLLER (0x0B0000)
+#define SM501_UCONTROLLER (0x0B0000)
/* 8051 micro controller SRAM base */
-#define SM501_UCONTROLLER_SRAM (0x0C0000)
+#define SM501_UCONTROLLER_SRAM (0x0C0000)
/* DMA base */
-#define SM501_DMA (0x0D0000)
+#define SM501_DMA (0x0D0000)
/* 2d engine base */
-#define SM501_2D_ENGINE (0x100000)
-#define SM501_2D_SOURCE (0x00)
-#define SM501_2D_DESTINATION (0x04)
-#define SM501_2D_DIMENSION (0x08)
-#define SM501_2D_CONTROL (0x0C)
-#define SM501_2D_PITCH (0x10)
-#define SM501_2D_FOREGROUND (0x14)
-#define SM501_2D_BACKGROUND (0x18)
-#define SM501_2D_STRETCH (0x1C)
-#define SM501_2D_COLOR_COMPARE (0x20)
-#define SM501_2D_COLOR_COMPARE_MASK (0x24)
-#define SM501_2D_MASK (0x28)
-#define SM501_2D_CLIP_TL (0x2C)
-#define SM501_2D_CLIP_BR (0x30)
-#define SM501_2D_MONO_PATTERN_LOW (0x34)
-#define SM501_2D_MONO_PATTERN_HIGH (0x38)
-#define SM501_2D_WINDOW_WIDTH (0x3C)
-#define SM501_2D_SOURCE_BASE (0x40)
-#define SM501_2D_DESTINATION_BASE (0x44)
-#define SM501_2D_ALPHA (0x48)
-#define SM501_2D_WRAP (0x4C)
-#define SM501_2D_STATUS (0x50)
-
-#define SM501_CSC_Y_SOURCE_BASE (0xC8)
-#define SM501_CSC_CONSTANTS (0xCC)
-#define SM501_CSC_Y_SOURCE_X (0xD0)
-#define SM501_CSC_Y_SOURCE_Y (0xD4)
-#define SM501_CSC_U_SOURCE_BASE (0xD8)
-#define SM501_CSC_V_SOURCE_BASE (0xDC)
-#define SM501_CSC_SOURCE_DIMENSION (0xE0)
-#define SM501_CSC_SOURCE_PITCH (0xE4)
-#define SM501_CSC_DESTINATION (0xE8)
-#define SM501_CSC_DESTINATION_DIMENSION (0xEC)
-#define SM501_CSC_DESTINATION_PITCH (0xF0)
-#define SM501_CSC_SCALE_FACTOR (0xF4)
-#define SM501_CSC_DESTINATION_BASE (0xF8)
-#define SM501_CSC_CONTROL (0xFC)
+#define SM501_2D_ENGINE (0x100000)
+#define SM501_2D_SOURCE (0x00)
+#define SM501_2D_DESTINATION (0x04)
+#define SM501_2D_DIMENSION (0x08)
+#define SM501_2D_CONTROL (0x0C)
+#define SM501_2D_PITCH (0x10)
+#define SM501_2D_FOREGROUND (0x14)
+#define SM501_2D_BACKGROUND (0x18)
+#define SM501_2D_STRETCH (0x1C)
+#define SM501_2D_COLOR_COMPARE (0x20)
+#define SM501_2D_COLOR_COMPARE_MASK (0x24)
+#define SM501_2D_MASK (0x28)
+#define SM501_2D_CLIP_TL (0x2C)
+#define SM501_2D_CLIP_BR (0x30)
+#define SM501_2D_MONO_PATTERN_LOW (0x34)
+#define SM501_2D_MONO_PATTERN_HIGH (0x38)
+#define SM501_2D_WINDOW_WIDTH (0x3C)
+#define SM501_2D_SOURCE_BASE (0x40)
+#define SM501_2D_DESTINATION_BASE (0x44)
+#define SM501_2D_ALPHA (0x48)
+#define SM501_2D_WRAP (0x4C)
+#define SM501_2D_STATUS (0x50)
+
+#define SM501_CSC_Y_SOURCE_BASE (0xC8)
+#define SM501_CSC_CONSTANTS (0xCC)
+#define SM501_CSC_Y_SOURCE_X (0xD0)
+#define SM501_CSC_Y_SOURCE_Y (0xD4)
+#define SM501_CSC_U_SOURCE_BASE (0xD8)
+#define SM501_CSC_V_SOURCE_BASE (0xDC)
+#define SM501_CSC_SOURCE_DIMENSION (0xE0)
+#define SM501_CSC_SOURCE_PITCH (0xE4)
+#define SM501_CSC_DESTINATION (0xE8)
+#define SM501_CSC_DESTINATION_DIMENSION (0xEC)
+#define SM501_CSC_DESTINATION_PITCH (0xF0)
+#define SM501_CSC_SCALE_FACTOR (0xF4)
+#define SM501_CSC_DESTINATION_BASE (0xF8)
+#define SM501_CSC_CONTROL (0xFC)
/* 2d engine data port base */
-#define SM501_2D_ENGINE_DATA (0x110000)
+#define SM501_2D_ENGINE_DATA (0x110000)
/* end of register definitions */
@@ -446,12 +446,12 @@
/* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
static const uint32_t sm501_mem_local_size[] = {
- [0] = 4*1024*1024,
- [1] = 8*1024*1024,
- [2] = 16*1024*1024,
- [3] = 32*1024*1024,
- [4] = 64*1024*1024,
- [5] = 2*1024*1024,
+ [0] = 4 * 1024 * 1024,
+ [1] = 8 * 1024 * 1024,
+ [2] = 16 * 1024 * 1024,
+ [3] = 32 * 1024 * 1024,
+ [4] = 64 * 1024 * 1024,
+ [5] = 2 * 1024 * 1024,
};
#define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
@@ -462,7 +462,7 @@ typedef struct SM501State {
/* status & internal resources */
hwaddr base;
uint32_t local_mem_size_index;
- uint8_t * local_mem;
+ uint8_t *local_mem;
MemoryRegion local_mem_region;
uint32_t last_width;
uint32_t last_height;
@@ -536,13 +536,13 @@ static uint32_t get_local_mem_size_index(uint32_t size)
int i, index = 0;
for (i = 0; i < ARRAY_SIZE(sm501_mem_local_size); i++) {
- uint32_t new_size = sm501_mem_local_size[i];
- if (new_size >= size) {
- if (norm_size == 0 || norm_size > new_size) {
- norm_size = new_size;
- index = i;
- }
- }
+ uint32_t new_size = sm501_mem_local_size[i];
+ if (new_size >= size) {
+ if (norm_size == 0 || norm_size > new_size) {
+ norm_size = new_size;
+ index = i;
+ }
+ }
}
return index;
@@ -637,7 +637,7 @@ static int within_hwc_y_range(SM501State *state, int y, int crt)
return (hwc_y <= y && y < hwc_y + SM501_HWC_HEIGHT);
}
-static void sm501_2d_operation(SM501State * s)
+static void sm501_2d_operation(SM501State *s)
{
/* obtain operation parameters */
int operation = (s->twoD_control >> 16) & 0x1f;
@@ -653,8 +653,8 @@ static void sm501_2d_operation(SM501State * s)
int addressing = (s->twoD_stretch >> 16) & 0xF;
/* get frame buffer info */
- uint8_t * src = s->local_mem + (s->twoD_source_base & 0x03FFFFFF);
- uint8_t * dst = s->local_mem + (s->twoD_destination_base & 0x03FFFFFF);
+ uint8_t *src = s->local_mem + (s->twoD_source_base & 0x03FFFFFF);
+ uint8_t *dst = s->local_mem + (s->twoD_destination_base & 0x03FFFFFF);
int src_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
int dst_width = (s->dc_crt_h_total & 0x00000FFF) + 1;
@@ -671,20 +671,20 @@ static void sm501_2d_operation(SM501State * s)
switch (operation) {
case 0x00: /* copy area */
-#define COPY_AREA(_bpp, _pixel_type, rtl) { \
- int y, x, index_d, index_s; \
- for (y = 0; y < operation_height; y++) { \
- for (x = 0; x < operation_width; x++) { \
- if (rtl) { \
- index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \
- index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \
- } else { \
- index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \
- index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
- } \
- *(_pixel_type*)&dst[index_d] = *(_pixel_type*)&src[index_s];\
- } \
- } \
+#define COPY_AREA(_bpp, _pixel_type, rtl) { \
+ int y, x, index_d, index_s; \
+ for (y = 0; y < operation_height; y++) { \
+ for (x = 0; x < operation_width; x++) { \
+ if (rtl) { \
+ index_s = ((src_y - y) * src_width + src_x - x) * _bpp; \
+ index_d = ((dst_y - y) * dst_width + dst_x - x) * _bpp; \
+ } else { \
+ index_s = ((src_y + y) * src_width + src_x + x) * _bpp; \
+ index_d = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
+ } \
+ *(_pixel_type *)&dst[index_d] = *(_pixel_type *)&src[index_s];\
+ } \
+ } \
}
switch (format_flags) {
case 0:
@@ -705,7 +705,7 @@ static void sm501_2d_operation(SM501State * s)
for (y = 0; y < operation_height; y++) { \
for (x = 0; x < operation_width; x++) { \
int index = ((dst_y + y) * dst_width + dst_x + x) * _bpp; \
- *(_pixel_type*)&dst[index] = (_pixel_type)color; \
+ *(_pixel_type *)&dst[index] = (_pixel_type)color; \
} \
} \
}
@@ -733,50 +733,50 @@ static void sm501_2d_operation(SM501State * s)
static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
unsigned size)
{
- SM501State * s = (SM501State *)opaque;
+ SM501State *s = (SM501State *)opaque;
uint32_t ret = 0;
SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr);
- switch(addr) {
+ switch (addr) {
case SM501_SYSTEM_CONTROL:
- ret = s->system_control;
- break;
+ ret = s->system_control;
+ break;
case SM501_MISC_CONTROL:
- ret = s->misc_control;
- break;
+ ret = s->misc_control;
+ break;
case SM501_GPIO31_0_CONTROL:
- ret = s->gpio_31_0_control;
- break;
+ ret = s->gpio_31_0_control;
+ break;
case SM501_GPIO63_32_CONTROL:
- ret = s->gpio_63_32_control;
- break;
+ ret = s->gpio_63_32_control;
+ break;
case SM501_DEVICEID:
- ret = 0x050100A0;
- break;
+ ret = 0x050100A0;
+ break;
case SM501_DRAM_CONTROL:
- ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
- break;
+ ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
+ break;
case SM501_IRQ_MASK:
- ret = s->irq_mask;
- break;
+ ret = s->irq_mask;
+ break;
case SM501_MISC_TIMING:
- /* TODO : simulate gate control */
- ret = s->misc_timing;
- break;
+ /* TODO : simulate gate control */
+ ret = s->misc_timing;
+ break;
case SM501_CURRENT_GATE:
- /* TODO : simulate gate control */
- ret = 0x00021807;
- break;
+ /* TODO : simulate gate control */
+ ret = 0x00021807;
+ break;
case SM501_CURRENT_CLOCK:
- ret = 0x2A1A0A09;
- break;
+ ret = 0x2A1A0A09;
+ break;
case SM501_POWER_MODE_CONTROL:
- ret = s->power_mode_control;
- break;
+ ret = s->power_mode_control;
+ break;
default:
- printf("sm501 system config : not implemented register read."
- " addr=%x\n", (int)addr);
+ printf("sm501 system config : not implemented register read."
+ " addr=%x\n", (int)addr);
abort();
}
@@ -786,47 +786,47 @@ static uint64_t sm501_system_config_read(void *opaque, hwaddr addr,
static void sm501_system_config_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- SM501State * s = (SM501State *)opaque;
+ SM501State *s = (SM501State *)opaque;
SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
- (uint32_t)addr, (uint32_t)value);
+ (uint32_t)addr, (uint32_t)value);
- switch(addr) {
+ switch (addr) {
case SM501_SYSTEM_CONTROL:
- s->system_control = value & 0xE300B8F7;
- break;
+ s->system_control = value & 0xE300B8F7;
+ break;
case SM501_MISC_CONTROL:
- s->misc_control = value & 0xFF7FFF20;
- break;
+ s->misc_control = value & 0xFF7FFF20;
+ break;
case SM501_GPIO31_0_CONTROL:
- s->gpio_31_0_control = value;
- break;
+ s->gpio_31_0_control = value;
+ break;
case SM501_GPIO63_32_CONTROL:
- s->gpio_63_32_control = value;
- break;
+ s->gpio_63_32_control = value;
+ break;
case SM501_DRAM_CONTROL:
- s->local_mem_size_index = (value >> 13) & 0x7;
- /* rODO : check validity of size change */
- s->dram_control |= value & 0x7FFFFFC3;
- break;
+ s->local_mem_size_index = (value >> 13) & 0x7;
+ /* TODO : check validity of size change */
+ s->dram_control |= value & 0x7FFFFFC3;
+ break;
case SM501_IRQ_MASK:
- s->irq_mask = value;
- break;
+ s->irq_mask = value;
+ break;
case SM501_MISC_TIMING:
- s->misc_timing = value & 0xF31F1FFF;
- break;
+ s->misc_timing = value & 0xF31F1FFF;
+ break;
case SM501_POWER_MODE_0_GATE:
case SM501_POWER_MODE_1_GATE:
case SM501_POWER_MODE_0_CLOCK:
case SM501_POWER_MODE_1_CLOCK:
- /* TODO : simulate gate & clock control */
- break;
+ /* TODO : simulate gate & clock control */
+ break;
case SM501_POWER_MODE_CONTROL:
- s->power_mode_control = value & 0x00000003;
- break;
+ s->power_mode_control = value & 0x00000003;
+ break;
default:
- printf("sm501 system config : not implemented register write."
- " addr=%x, val=%x\n", (int)addr, (uint32_t)value);
+ printf("sm501 system config : not implemented register write."
+ " addr=%x, val=%x\n", (int)addr, (uint32_t)value);
abort();
}
}
@@ -843,119 +843,119 @@ static const MemoryRegionOps sm501_system_config_ops = {
static uint32_t sm501_palette_read(void *opaque, hwaddr addr)
{
- SM501State * s = (SM501State *)opaque;
+ SM501State *s = (SM501State *)opaque;
SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
/* TODO : consider BYTE/WORD access */
/* TODO : consider endian */
assert(range_covers_byte(0, 0x400 * 3, addr));
- return *(uint32_t*)&s->dc_palette[addr];
+ return *(uint32_t *)&s->dc_palette[addr];
}
-static void sm501_palette_write(void *opaque,
- hwaddr addr, uint32_t value)
+static void sm501_palette_write(void *opaque, hwaddr addr,
+ uint32_t value)
{
- SM501State * s = (SM501State *)opaque;
+ SM501State *s = (SM501State *)opaque;
SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
- (int)addr, value);
+ (int)addr, value);
/* TODO : consider BYTE/WORD access */
/* TODO : consider endian */
assert(range_covers_byte(0, 0x400 * 3, addr));
- *(uint32_t*)&s->dc_palette[addr] = value;
+ *(uint32_t *)&s->dc_palette[addr] = value;
}
static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
unsigned size)
{
- SM501State * s = (SM501State *)opaque;
+ SM501State *s = (SM501State *)opaque;
uint32_t ret = 0;
SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr);
- switch(addr) {
+ switch (addr) {
case SM501_DC_PANEL_CONTROL:
- ret = s->dc_panel_control;
- break;
+ ret = s->dc_panel_control;
+ break;
case SM501_DC_PANEL_PANNING_CONTROL:
- ret = s->dc_panel_panning_control;
- break;
+ ret = s->dc_panel_panning_control;
+ break;
case SM501_DC_PANEL_FB_ADDR:
- ret = s->dc_panel_fb_addr;
- break;
+ ret = s->dc_panel_fb_addr;
+ break;
case SM501_DC_PANEL_FB_OFFSET:
- ret = s->dc_panel_fb_offset;
- break;
+ ret = s->dc_panel_fb_offset;
+ break;
case SM501_DC_PANEL_FB_WIDTH:
- ret = s->dc_panel_fb_width;
- break;
+ ret = s->dc_panel_fb_width;
+ break;
case SM501_DC_PANEL_FB_HEIGHT:
- ret = s->dc_panel_fb_height;
- break;
+ ret = s->dc_panel_fb_height;
+ break;
case SM501_DC_PANEL_TL_LOC:
- ret = s->dc_panel_tl_location;
- break;
+ ret = s->dc_panel_tl_location;
+ break;
case SM501_DC_PANEL_BR_LOC:
- ret = s->dc_panel_br_location;
- break;
+ ret = s->dc_panel_br_location;
+ break;
case SM501_DC_PANEL_H_TOT:
- ret = s->dc_panel_h_total;
- break;
+ ret = s->dc_panel_h_total;
+ break;
case SM501_DC_PANEL_H_SYNC:
- ret = s->dc_panel_h_sync;
- break;
+ ret = s->dc_panel_h_sync;
+ break;
case SM501_DC_PANEL_V_TOT:
- ret = s->dc_panel_v_total;
- break;
+ ret = s->dc_panel_v_total;
+ break;
case SM501_DC_PANEL_V_SYNC:
- ret = s->dc_panel_v_sync;
- break;
+ ret = s->dc_panel_v_sync;
+ break;
case SM501_DC_CRT_CONTROL:
- ret = s->dc_crt_control;
- break;
+ ret = s->dc_crt_control;
+ break;
case SM501_DC_CRT_FB_ADDR:
- ret = s->dc_crt_fb_addr;
- break;
+ ret = s->dc_crt_fb_addr;
+ break;
case SM501_DC_CRT_FB_OFFSET:
- ret = s->dc_crt_fb_offset;
- break;
+ ret = s->dc_crt_fb_offset;
+ break;
case SM501_DC_CRT_H_TOT:
- ret = s->dc_crt_h_total;
- break;
+ ret = s->dc_crt_h_total;
+ break;
case SM501_DC_CRT_H_SYNC:
- ret = s->dc_crt_h_sync;
- break;
+ ret = s->dc_crt_h_sync;
+ break;
case SM501_DC_CRT_V_TOT:
- ret = s->dc_crt_v_total;
- break;
+ ret = s->dc_crt_v_total;
+ break;
case SM501_DC_CRT_V_SYNC:
- ret = s->dc_crt_v_sync;
- break;
+ ret = s->dc_crt_v_sync;
+ break;
case SM501_DC_CRT_HWC_ADDR:
- ret = s->dc_crt_hwc_addr;
- break;
+ ret = s->dc_crt_hwc_addr;
+ break;
case SM501_DC_CRT_HWC_LOC:
- ret = s->dc_crt_hwc_location;
- break;
+ ret = s->dc_crt_hwc_location;
+ break;
case SM501_DC_CRT_HWC_COLOR_1_2:
- ret = s->dc_crt_hwc_color_1_2;
- break;
+ ret = s->dc_crt_hwc_color_1_2;
+ break;
case SM501_DC_CRT_HWC_COLOR_3:
- ret = s->dc_crt_hwc_color_3;
- break;
+ ret = s->dc_crt_hwc_color_3;
+ break;
- case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4:
+ case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE);
break;
default:
- printf("sm501 disp ctrl : not implemented register read."
- " addr=%x\n", (int)addr);
+ printf("sm501 disp ctrl : not implemented register read."
+ " addr=%x\n", (int)addr);
abort();
}
@@ -965,104 +965,104 @@ static uint64_t sm501_disp_ctrl_read(void *opaque, hwaddr addr,
static void sm501_disp_ctrl_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- SM501State * s = (SM501State *)opaque;
+ SM501State *s = (SM501State *)opaque;
SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
- (unsigned)addr, (unsigned)value);
+ (unsigned)addr, (unsigned)value);
- switch(addr) {
+ switch (addr) {
case SM501_DC_PANEL_CONTROL:
- s->dc_panel_control = value & 0x0FFF73FF;
- break;
+ s->dc_panel_control = value & 0x0FFF73FF;
+ break;
case SM501_DC_PANEL_PANNING_CONTROL:
- s->dc_panel_panning_control = value & 0xFF3FFF3F;
- break;
+ s->dc_panel_panning_control = value & 0xFF3FFF3F;
+ break;
case SM501_DC_PANEL_FB_ADDR:
- s->dc_panel_fb_addr = value & 0x8FFFFFF0;
- break;
+ s->dc_panel_fb_addr = value & 0x8FFFFFF0;
+ break;
case SM501_DC_PANEL_FB_OFFSET:
- s->dc_panel_fb_offset = value & 0x3FF03FF0;
- break;
+ s->dc_panel_fb_offset = value & 0x3FF03FF0;
+ break;
case SM501_DC_PANEL_FB_WIDTH:
- s->dc_panel_fb_width = value & 0x0FFF0FFF;
- break;
+ s->dc_panel_fb_width = value & 0x0FFF0FFF;
+ break;
case SM501_DC_PANEL_FB_HEIGHT:
- s->dc_panel_fb_height = value & 0x0FFF0FFF;
- break;
+ s->dc_panel_fb_height = value & 0x0FFF0FFF;
+ break;
case SM501_DC_PANEL_TL_LOC:
- s->dc_panel_tl_location = value & 0x07FF07FF;
- break;
+ s->dc_panel_tl_location = value & 0x07FF07FF;
+ break;
case SM501_DC_PANEL_BR_LOC:
- s->dc_panel_br_location = value & 0x07FF07FF;
- break;
+ s->dc_panel_br_location = value & 0x07FF07FF;
+ break;
case SM501_DC_PANEL_H_TOT:
- s->dc_panel_h_total = value & 0x0FFF0FFF;
- break;
+ s->dc_panel_h_total = value & 0x0FFF0FFF;
+ break;
case SM501_DC_PANEL_H_SYNC:
- s->dc_panel_h_sync = value & 0x00FF0FFF;
- break;
+ s->dc_panel_h_sync = value & 0x00FF0FFF;
+ break;
case SM501_DC_PANEL_V_TOT:
- s->dc_panel_v_total = value & 0x0FFF0FFF;
- break;
+ s->dc_panel_v_total = value & 0x0FFF0FFF;
+ break;
case SM501_DC_PANEL_V_SYNC:
- s->dc_panel_v_sync = value & 0x003F0FFF;
- break;
+ s->dc_panel_v_sync = value & 0x003F0FFF;
+ break;
case SM501_DC_PANEL_HWC_ADDR:
- s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
- break;
+ s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
+ break;
case SM501_DC_PANEL_HWC_LOC:
- s->dc_panel_hwc_location = value & 0x0FFF0FFF;
- break;
+ s->dc_panel_hwc_location = value & 0x0FFF0FFF;
+ break;
case SM501_DC_PANEL_HWC_COLOR_1_2:
- s->dc_panel_hwc_color_1_2 = value;
- break;
+ s->dc_panel_hwc_color_1_2 = value;
+ break;
case SM501_DC_PANEL_HWC_COLOR_3:
- s->dc_panel_hwc_color_3 = value & 0x0000FFFF;
- break;
+ s->dc_panel_hwc_color_3 = value & 0x0000FFFF;
+ break;
case SM501_DC_CRT_CONTROL:
- s->dc_crt_control = value & 0x0003FFFF;
- break;
+ s->dc_crt_control = value & 0x0003FFFF;
+ break;
case SM501_DC_CRT_FB_ADDR:
- s->dc_crt_fb_addr = value & 0x8FFFFFF0;
- break;
+ s->dc_crt_fb_addr = value & 0x8FFFFFF0;
+ break;
case SM501_DC_CRT_FB_OFFSET:
- s->dc_crt_fb_offset = value & 0x3FF03FF0;
- break;
+ s->dc_crt_fb_offset = value & 0x3FF03FF0;
+ break;
case SM501_DC_CRT_H_TOT:
- s->dc_crt_h_total = value & 0x0FFF0FFF;
- break;
+ s->dc_crt_h_total = value & 0x0FFF0FFF;
+ break;
case SM501_DC_CRT_H_SYNC:
- s->dc_crt_h_sync = value & 0x00FF0FFF;
- break;
+ s->dc_crt_h_sync = value & 0x00FF0FFF;
+ break;
case SM501_DC_CRT_V_TOT:
- s->dc_crt_v_total = value & 0x0FFF0FFF;
- break;
+ s->dc_crt_v_total = value & 0x0FFF0FFF;
+ break;
case SM501_DC_CRT_V_SYNC:
- s->dc_crt_v_sync = value & 0x003F0FFF;
- break;
+ s->dc_crt_v_sync = value & 0x003F0FFF;
+ break;
case SM501_DC_CRT_HWC_ADDR:
- s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
- break;
+ s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
+ break;
case SM501_DC_CRT_HWC_LOC:
- s->dc_crt_hwc_location = value & 0x0FFF0FFF;
- break;
+ s->dc_crt_hwc_location = value & 0x0FFF0FFF;
+ break;
case SM501_DC_CRT_HWC_COLOR_1_2:
- s->dc_crt_hwc_color_1_2 = value;
- break;
+ s->dc_crt_hwc_color_1_2 = value;
+ break;
case SM501_DC_CRT_HWC_COLOR_3:
- s->dc_crt_hwc_color_3 = value & 0x0000FFFF;
- break;
+ s->dc_crt_hwc_color_3 = value & 0x0000FFFF;
+ break;
- case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4:
+ case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400 * 3 - 4:
sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value);
break;
default:
- printf("sm501 disp ctrl : not implemented register write."
- " addr=%x, val=%x\n", (int)addr, (unsigned)value);
+ printf("sm501 disp ctrl : not implemented register write."
+ " addr=%x, val=%x\n", (int)addr, (unsigned)value);
abort();
}
}
@@ -1080,11 +1080,11 @@ static const MemoryRegionOps sm501_disp_ctrl_ops = {
static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
unsigned size)
{
- SM501State * s = (SM501State *)opaque;
+ SM501State *s = (SM501State *)opaque;
uint32_t ret = 0;
SM501_DPRINTF("sm501 2d engine regs : read addr=%x\n", (int)addr);
- switch(addr) {
+ switch (addr) {
case SM501_2D_SOURCE_BASE:
ret = s->twoD_source_base;
break;
@@ -1100,11 +1100,11 @@ static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr,
static void sm501_2d_engine_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- SM501State * s = (SM501State *)opaque;
+ SM501State *s = (SM501State *)opaque;
SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n",
(unsigned)addr, (unsigned)value);
- switch(addr) {
+ switch (addr) {
case SM501_2D_SOURCE:
s->twoD_source = value;
break;
@@ -1168,9 +1168,9 @@ static const MemoryRegionOps sm501_2d_engine_ops = {
/* draw line functions for all console modes */
typedef void draw_line_func(uint8_t *d, const uint8_t *s,
- int width, const uint32_t *pal);
+ int width, const uint32_t *pal);
-typedef void draw_hwc_line_func(SM501State * s, int crt, uint8_t * palette,
+typedef void draw_hwc_line_func(SM501State *s, int crt, uint8_t *palette,
int c_y, uint8_t *d, int width);
#define DEPTH 8
@@ -1197,7 +1197,7 @@ typedef void draw_hwc_line_func(SM501State * s, int crt, uint8_t * palette,
#define DEPTH 32
#include "sm501_template.h"
-static draw_line_func * draw_line8_funcs[] = {
+static draw_line_func *draw_line8_funcs[] = {
draw_line8_8,
draw_line8_15,
draw_line8_16,
@@ -1207,7 +1207,7 @@ static draw_line_func * draw_line8_funcs[] = {
draw_line8_16bgr,
};
-static draw_line_func * draw_line16_funcs[] = {
+static draw_line_func *draw_line16_funcs[] = {
draw_line16_8,
draw_line16_15,
draw_line16_16,
@@ -1217,7 +1217,7 @@ static draw_line_func * draw_line16_funcs[] = {
draw_line16_16bgr,
};
-static draw_line_func * draw_line32_funcs[] = {
+static draw_line_func *draw_line32_funcs[] = {
draw_line32_8,
draw_line32_15,
draw_line32_16,
@@ -1227,7 +1227,7 @@ static draw_line_func * draw_line32_funcs[] = {
draw_line32_16bgr,
};
-static draw_hwc_line_func * draw_hwc_line_funcs[] = {
+static draw_hwc_line_func *draw_hwc_line_funcs[] = {
draw_hwc_line_8,
draw_hwc_line_15,
draw_hwc_line_16,
@@ -1242,7 +1242,7 @@ static inline int get_depth_index(DisplaySurface *surface)
switch (surface_bits_per_pixel(surface)) {
default:
case 8:
- return 0;
+ return 0;
case 15:
return 1;
case 16:
@@ -1256,22 +1256,22 @@ static inline int get_depth_index(DisplaySurface *surface)
}
}
-static void sm501_draw_crt(SM501State * s)
+static void sm501_draw_crt(SM501State *s)
{
DisplaySurface *surface = qemu_console_surface(s->con);
int y;
int width = (s->dc_crt_h_total & 0x00000FFF) + 1;
int height = (s->dc_crt_v_total & 0x00000FFF) + 1;
- uint8_t * src = s->local_mem;
+ uint8_t *src = s->local_mem;
int src_bpp = 0;
int dst_bpp = surface_bytes_per_pixel(surface);
- uint32_t * palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE
- - SM501_DC_PANEL_PALETTE];
+ uint32_t *palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE -
+ SM501_DC_PANEL_PALETTE];
uint8_t hwc_palette[3 * 3];
int ds_depth_index = get_depth_index(surface);
- draw_line_func * draw_line = NULL;
- draw_hwc_line_func * draw_hwc_line = NULL;
+ draw_line_func *draw_line = NULL;
+ draw_hwc_line_func *draw_hwc_line = NULL;
int full_update = 0;
int y_start = -1;
ram_addr_t page_min = ~0l;
@@ -1281,22 +1281,22 @@ static void sm501_draw_crt(SM501State * s)
/* choose draw_line function */
switch (s->dc_crt_control & 3) {
case SM501_DC_CRT_CONTROL_8BPP:
- src_bpp = 1;
- draw_line = draw_line8_funcs[ds_depth_index];
- break;
+ src_bpp = 1;
+ draw_line = draw_line8_funcs[ds_depth_index];
+ break;
case SM501_DC_CRT_CONTROL_16BPP:
- src_bpp = 2;
- draw_line = draw_line16_funcs[ds_depth_index];
- break;
+ src_bpp = 2;
+ draw_line = draw_line16_funcs[ds_depth_index];
+ break;
case SM501_DC_CRT_CONTROL_32BPP:
- src_bpp = 4;
- draw_line = draw_line32_funcs[ds_depth_index];
- break;
+ src_bpp = 4;
+ draw_line = draw_line32_funcs[ds_depth_index];
+ break;
default:
- printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
- s->dc_crt_control);
+ printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
+ s->dc_crt_control);
abort();
- break;
+ break;
}
/* set up to draw hardware cursor */
@@ -1319,61 +1319,65 @@ static void sm501_draw_crt(SM501State * s)
if (s->last_width != width || s->last_height != height) {
qemu_console_resize(s->con, width, height);
surface = qemu_console_surface(s->con);
- s->last_width = width;
- s->last_height = height;
- full_update = 1;
+ s->last_width = width;
+ s->last_height = height;
+ full_update = 1;
}
/* draw each line according to conditions */
memory_region_sync_dirty_bitmap(&s->local_mem_region);
for (y = 0; y < height; y++) {
- int update_hwc = draw_hwc_line ? within_hwc_y_range(s, y, 1) : 0;
- int update = full_update || update_hwc;
+ int update_hwc = draw_hwc_line ? within_hwc_y_range(s, y, 1) : 0;
+ int update = full_update || update_hwc;
ram_addr_t page0 = offset;
ram_addr_t page1 = offset + width * src_bpp - 1;
- /* check dirty flags for each line */
+ /* check dirty flags for each line */
update = memory_region_get_dirty(&s->local_mem_region, page0,
page1 - page0, DIRTY_MEMORY_VGA);
- /* draw line and change status */
- if (update) {
+ /* draw line and change status */
+ if (update) {
uint8_t *d = surface_data(surface);
d += y * width * dst_bpp;
/* draw graphics layer */
draw_line(d, src, width, palette);
- /* draw haredware cursor */
+ /* draw hardware cursor */
if (update_hwc) {
draw_hwc_line(s, 1, hwc_palette, y - get_hwc_y(s, 1), d, width);
}
- if (y_start < 0)
- y_start = y;
- if (page0 < page_min)
- page_min = page0;
- if (page1 > page_max)
- page_max = page1;
- } else {
- if (y_start >= 0) {
- /* flush to display */
+ if (y_start < 0) {
+ y_start = y;
+ }
+ if (page0 < page_min) {
+ page_min = page0;
+ }
+ if (page1 > page_max) {
+ page_max = page1;
+ }
+ } else {
+ if (y_start >= 0) {
+ /* flush to display */
dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
- y_start = -1;
- }
- }
+ y_start = -1;
+ }
+ }
- src += width * src_bpp;
- offset += width * src_bpp;
+ src += width * src_bpp;
+ offset += width * src_bpp;
}
/* complete flush to display */
- if (y_start >= 0)
+ if (y_start >= 0) {
dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
+ }
/* clear dirty flags */
if (page_min != ~0l) {
- memory_region_reset_dirty(&s->local_mem_region,
+ memory_region_reset_dirty(&s->local_mem_region,
page_min, page_max + TARGET_PAGE_SIZE,
DIRTY_MEMORY_VGA);
}
@@ -1381,10 +1385,11 @@ static void sm501_draw_crt(SM501State * s)
static void sm501_update_display(void *opaque)
{
- SM501State * s = (SM501State *)opaque;
+ SM501State *s = (SM501State *)opaque;
- if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE)
- sm501_draw_crt(s);
+ if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE) {
+ sm501_draw_crt(s);
+ }
}
static const GraphicHwOps sm501_ops = {
@@ -1394,19 +1399,18 @@ static const GraphicHwOps sm501_ops = {
void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
uint32_t local_mem_bytes, qemu_irq irq, Chardev *chr)
{
- SM501State * s;
+ SM501State *s;
DeviceState *dev;
MemoryRegion *sm501_system_config = g_new(MemoryRegion, 1);
MemoryRegion *sm501_disp_ctrl = g_new(MemoryRegion, 1);
MemoryRegion *sm501_2d_engine = g_new(MemoryRegion, 1);
/* allocate management data region */
- s = (SM501State *)g_malloc0(sizeof(SM501State));
+ s = g_new0(SM501State, 1);
s->base = base;
- s->local_mem_size_index
- = get_local_mem_size_index(local_mem_bytes);
+ s->local_mem_size_index = get_local_mem_size_index(local_mem_bytes);
SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
- s->local_mem_size_index);
+ s->local_mem_size_index);
s->system_control = 0x00100000;
s->misc_control = 0x00001000; /* assumes SH, active=low */
s->dc_panel_control = 0x00010000;
@@ -1421,8 +1425,8 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base,
memory_region_add_subregion(address_space_mem, base, &s->local_mem_region);
/* map mmio */
- memory_region_init_io(sm501_system_config, NULL, &sm501_system_config_ops, s,
- "sm501-system-config", 0x6c);
+ memory_region_init_io(sm501_system_config, NULL, &sm501_system_config_ops,
+ s, "sm501-system-config", 0x6c);
memory_region_add_subregion(address_space_mem, base + MMIO_BASE_OFFSET,
sm501_system_config);
memory_region_init_io(sm501_disp_ctrl, NULL, &sm501_disp_ctrl_ops, s,
diff --git a/hw/display/sm501_template.h b/hw/display/sm501_template.h
index f33e499..aeeac5d 100644
--- a/hw/display/sm501_template.h
+++ b/hw/display/sm501_template.h
@@ -47,40 +47,40 @@ static void glue(draw_line8_, PIXEL_NAME)(
{
uint8_t v, r, g, b;
do {
- v = ldub_p(s);
- r = (pal[v] >> 16) & 0xff;
- g = (pal[v] >> 8) & 0xff;
- b = (pal[v] >> 0) & 0xff;
- ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
- s ++;
- d += BPP;
- } while (-- width != 0);
+ v = ldub_p(s);
+ r = (pal[v] >> 16) & 0xff;
+ g = (pal[v] >> 8) & 0xff;
+ b = (pal[v] >> 0) & 0xff;
+ *(PIXEL_TYPE *)d = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
+ s++;
+ d += BPP;
+ } while (--width != 0);
}
static void glue(draw_line16_, PIXEL_NAME)(
- uint8_t *d, const uint8_t *s, int width, const uint32_t *pal)
+ uint8_t *d, const uint8_t *s, int width, const uint32_t *pal)
{
uint16_t rgb565;
uint8_t r, g, b;
do {
- rgb565 = lduw_p(s);
- r = ((rgb565 >> 11) & 0x1f) << 3;
- g = ((rgb565 >> 5) & 0x3f) << 2;
- b = ((rgb565 >> 0) & 0x1f) << 3;
- ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
- s += 2;
- d += BPP;
- } while (-- width != 0);
+ rgb565 = lduw_p(s);
+ r = ((rgb565 >> 11) & 0x1f) << 3;
+ g = ((rgb565 >> 5) & 0x3f) << 2;
+ b = ((rgb565 >> 0) & 0x1f) << 3;
+ *(PIXEL_TYPE *)d = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
+ s += 2;
+ d += BPP;
+ } while (--width != 0);
}
static void glue(draw_line32_, PIXEL_NAME)(
- uint8_t *d, const uint8_t *s, int width, const uint32_t *pal)
+ uint8_t *d, const uint8_t *s, int width, const uint32_t *pal)
{
uint8_t r, g, b;
do {
- ldub_p(s);
+ ldub_p(s);
#if defined(TARGET_WORDS_BIGENDIAN)
r = s[1];
g = s[2];
@@ -90,17 +90,17 @@ static void glue(draw_line32_, PIXEL_NAME)(
g = s[1];
r = s[2];
#endif
- ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
- s += 4;
- d += BPP;
- } while (-- width != 0);
+ *(PIXEL_TYPE *)d = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
+ s += 4;
+ d += BPP;
+ } while (--width != 0);
}
/**
* Draw hardware cursor image on the given line.
*/
-static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State * s, int crt,
- uint8_t * palette, int c_y, uint8_t *d, int width)
+static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State *s, int crt,
+ uint8_t *palette, int c_y, uint8_t *d, int width)
{
int x, i;
uint8_t bitset = 0;
@@ -132,7 +132,7 @@ static void glue(draw_hwc_line_, PIXEL_NAME)(SM501State * s, int crt,
uint8_t r = palette[v * 3 + 0];
uint8_t g = palette[v * 3 + 1];
uint8_t b = palette[v * 3 + 2];
- ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
+ *(PIXEL_TYPE *)d = glue(rgb_to_pixel, PIXEL_NAME)(r, g, b);
}
d += BPP;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
` (12 preceding siblings ...)
2017-04-21 15:18 ` [Qemu-devel] [PATCH v7 01/13] sm501: Fixed code style and a few typos in comments BALATON Zoltan
@ 2017-04-22 15:41 ` Aurelien Jarno
2017-04-24 12:09 ` Peter Maydell
14 siblings, 0 replies; 16+ messages in thread
From: Aurelien Jarno @ 2017-04-22 15:41 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-devel, qemu-trivial, Magnus Damm, Peter Maydell,
David Gibson
On 2017-04-21 17:18, BALATON Zoltan wrote:
> v7: Define default values for some variables to avoid an (invalid)
> warning from gcc 6 or 7 as suggested by Aurelien Jarno.
Thanks a lot for this new version, I confirm it now builds fine with GCC
6 or 7.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation
2017-04-21 15:18 [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation BALATON Zoltan
` (13 preceding siblings ...)
2017-04-22 15:41 ` [Qemu-devel] [PATCH v7 00/13] Improvements for SM501 display controller emulation Aurelien Jarno
@ 2017-04-24 12:09 ` Peter Maydell
14 siblings, 0 replies; 16+ messages in thread
From: Peter Maydell @ 2017-04-24 12:09 UTC (permalink / raw)
To: BALATON Zoltan
Cc: QEMU Developers, QEMU Trivial, Magnus Damm, Aurelien Jarno,
David Gibson
On 21 April 2017 at 16:18, BALATON Zoltan <balaton@eik.bme.hu> wrote:
> v7: Define default values for some variables to avoid an (invalid)
> warning from gcc 6 or 7 as suggested by Aurelien Jarno.
>
> BALATON Zoltan (13):
> sm501: Fixed code style and a few typos in comments
> sm501: Use defined constants instead of literal values where available
> sm501: Add missing arbitration control register
> sm501: QOMify
> sm501: Get rid of base address in draw_hwc_line
> sm501: Add emulation of chip connected via PCI
> sm501: Fix device endianness
> sm501: Fix hardware cursor
> sm501: Misc clean ups
> sm501: Add support for panel layer
> sm501: Add some more missing registers
> sm501: Add vmstate descriptor
> ppc: Add SM501 device in ppc softmmu targets default configs
Thanks for working through the code review process on this one.
Since SH4 is only 'odd fixes' and Aurelien has tested the code,
I've applied it directly to git master.
thanks
-- PMM
^ permalink raw reply [flat|nested] 16+ messages in thread