[Qemu-devel] [PATCH v1 0/5] Connect a PCIe host and graphics support to RISC-V

[Qemu-devel] [PATCH v1 0/5] Connect a PCIe host and graphics support to RISC-V

[Alistair Francis]

Alistair Francis (5):
  hw/riscv/virtio: Set the soc device tree node as a simple-bus
  hw/riscv/virt: Increase the number of interrupts
  hw/riscv/virt: Connect the Xilinx PCIe
  hw/riscv/virt: Connect a VGA PCIe device
  riscv64-softmmu.mak: Build Virtio Block support

 default-configs/riscv32-softmmu.mak |  6 +++
 default-configs/riscv64-softmmu.mak |  8 ++++
 hw/riscv/virt.c                     | 73 ++++++++++++++++++++++++++++-
 include/hw/riscv/virt.h             |  6 ++-
 4 files changed, 90 insertions(+), 3 deletions(-)

-- 
2.17.1

[Qemu-devel] [PATCH v1 1/5] hw/riscv/virtio: Set the soc device tree node as a simple-bus

[Alistair Francis]

To allow Linux to ennumerate devices on the /soc/ node set it as a
"simple-bus".

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index bdd75722eb..a95ccb2825 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -120,7 +120,7 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
 
     qemu_fdt_add_subnode(fdt, "/soc");
     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
-    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "riscv-virtio-soc");
+    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 
-- 
2.17.1

[Qemu-devel] [PATCH v1 2/5] hw/riscv/virt: Increase the number of interrupts

[Alistair Francis]

Increase the number of interrupts to match the HiFive Unleashed board.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 91163d6cbf..7cb2742070 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -45,7 +45,7 @@ enum {
     UART0_IRQ = 10,
     VIRTIO_IRQ = 1, /* 1 to 8 */
     VIRTIO_COUNT = 8,
-    VIRTIO_NDEV = 10
+    VIRTIO_NDEV = 0x35
 };
 
 enum {
-- 
2.17.1

[Qemu-devel] [PATCH v1 3/5] hw/riscv/virt: Connect the Xilinx PCIe

[Alistair Francis]

Connect the Xilinx PCIe device based on the device tree included in the
HiFive Unleashed ROM.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 default-configs/riscv32-softmmu.mak |  3 ++
 default-configs/riscv64-softmmu.mak |  3 ++
 hw/riscv/virt.c                     | 65 +++++++++++++++++++++++++++++
 include/hw/riscv/virt.h             |  4 +-
 4 files changed, 74 insertions(+), 1 deletion(-)

diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index 7a003eb5e2..b8cac7a49f 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -4,3 +4,6 @@ CONFIG_SERIAL=y
 CONFIG_VIRTIO_MMIO=y
 CONFIG_VIRTIO=y
 CONFIG_CADENCE=y
+
+CONFIG_PCI=y
+CONFIG_PCI_XILINX=y
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index 7a003eb5e2..b8cac7a49f 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -4,3 +4,6 @@ CONFIG_SERIAL=y
 CONFIG_VIRTIO_MMIO=y
 CONFIG_VIRTIO=y
 CONFIG_CADENCE=y
+
+CONFIG_PCI=y
+CONFIG_PCI_XILINX=y
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index a95ccb2825..7c1ed3aee5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -38,6 +38,8 @@
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
 #include "exec/address-spaces.h"
+#include "hw/pci/pci.h"
+#include "hw/pci-host/xilinx-pcie.h"
 #include "elf.h"
 
 #include <libfdt.h>
@@ -54,6 +56,7 @@ static const struct MemmapEntry {
     [VIRT_UART0] =    { 0x10000000,      0x100 },
     [VIRT_VIRTIO] =   { 0x10001000,     0x1000 },
     [VIRT_DRAM] =     { 0x80000000,        0x0 },
+    [VIRT_PCIE] =     { 0x2000000000, 0x4000000 },
 };
 
 static uint64_t load_kernel(const char *kernel_filename)
@@ -232,6 +235,32 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
         g_free(nodename);
     }
 
+    nodename = g_strdup_printf("/pci@%lx",
+        (long) memmap[VIRT_PCIE].base);
+    qemu_fdt_add_subnode(fdt, nodename);
+    qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 0x3);
+    qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", 0x1);
+    qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2);
+    qemu_fdt_setprop_string(fdt, nodename, "compatible",
+                            "xlnx,axi-pcie-host-1.00.a");
+    qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
+    qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x20, 0x0, 0x0,
+                           memmap[VIRT_PCIE].size);
+    qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
+    qemu_fdt_setprop_cells(fdt, nodename, "ranges", 0x2000000, 0x0,
+                           0x40000000, 0x0, 0x40000000, 0x0, 0x20000000);
+    qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
+    qemu_fdt_setprop_cells(fdt, nodename, "interrupts", PCIE_IRQ);
+    g_free(nodename);
+
+    nodename = g_strdup_printf("/pci@%lx/interrupt-controller",
+            (long) memmap[VIRT_PCIE].base);
+    qemu_fdt_add_subnode(fdt, nodename);
+    qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 0x00);
+    qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", 0x1);
+    qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+    g_free(nodename);
+
     nodename = g_strdup_printf("/test@%lx",
         (long)memmap[VIRT_TEST].base);
     qemu_fdt_add_subnode(fdt, nodename);
@@ -259,6 +288,38 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
     return fdt;
 }
 
+
+static inline DeviceState *
+xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
+                 hwaddr cfg_base, uint64_t cfg_size,
+                 hwaddr mmio_base, uint64_t mmio_size,
+                 qemu_irq irq, bool link_up)
+{
+    DeviceState *dev;
+    MemoryRegion *cfg, *mmio;
+
+    dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST);
+
+    qdev_prop_set_uint32(dev, "bus_nr", bus_nr);
+    qdev_prop_set_uint64(dev, "cfg_base", cfg_base);
+    qdev_prop_set_uint64(dev, "cfg_size", cfg_size);
+    qdev_prop_set_uint64(dev, "mmio_base", mmio_base);
+    qdev_prop_set_uint64(dev, "mmio_size", mmio_size);
+    qdev_prop_set_bit(dev, "link_up", link_up);
+
+    qdev_init_nofail(dev);
+
+    cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+    memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
+
+    mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+    memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);
+
+    qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq);
+
+    return dev;
+}
+
 static void riscv_virt_board_init(MachineState *machine)
 {
     const struct MemmapEntry *memmap = virt_memmap;
@@ -382,6 +443,10 @@ static void riscv_virt_board_init(MachineState *machine)
             qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
     }
 
+    xilinx_pcie_init(system_memory, 0, memmap[VIRT_PCIE].base,
+                     memmap[VIRT_PCIE].size, 0x40000000, 0x20000000,
+                     qdev_get_gpio_in(DEVICE(s->plic), PCIE_IRQ), true);
+
     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
         0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
         serial_hd(0), DEVICE_LITTLE_ENDIAN);
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 7cb2742070..d0129c2ca5 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -38,13 +38,15 @@ enum {
     VIRT_PLIC,
     VIRT_UART0,
     VIRT_VIRTIO,
-    VIRT_DRAM
+    VIRT_DRAM,
+    VIRT_PCIE
 };
 
 enum {
     UART0_IRQ = 10,
     VIRTIO_IRQ = 1, /* 1 to 8 */
     VIRTIO_COUNT = 8,
+    PCIE_IRQ = 0x20,
     VIRTIO_NDEV = 0x35
 };
 
-- 
2.17.1

[Qemu-devel] [PATCH v1 4/5] hw/riscv/virt: Connect a VGA PCIe device

[Alistair Francis]

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 default-configs/riscv32-softmmu.mak |  3 +++
 default-configs/riscv64-softmmu.mak |  3 +++
 hw/riscv/virt.c                     | 12 +++++++++---
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index b8cac7a49f..73a421d3de 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -7,3 +7,6 @@ CONFIG_CADENCE=y
 
 CONFIG_PCI=y
 CONFIG_PCI_XILINX=y
+
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index b8cac7a49f..73a421d3de 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -7,3 +7,6 @@ CONFIG_CADENCE=y
 
 CONFIG_PCI=y
 CONFIG_PCI_XILINX=y
+
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 7c1ed3aee5..11f6f96a47 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -328,6 +328,8 @@ static void riscv_virt_board_init(MachineState *machine)
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+    PCIBus *pci_bus;
+    DeviceState *dev;
     char *plic_hart_config;
     size_t plic_hart_config_len;
     int i;
@@ -443,9 +445,12 @@ static void riscv_virt_board_init(MachineState *machine)
             qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
     }
 
-    xilinx_pcie_init(system_memory, 0, memmap[VIRT_PCIE].base,
-                     memmap[VIRT_PCIE].size, 0x40000000, 0x20000000,
-                     qdev_get_gpio_in(DEVICE(s->plic), PCIE_IRQ), true);
+    dev = xilinx_pcie_init(system_memory, 0, memmap[VIRT_PCIE].base,
+                           memmap[VIRT_PCIE].size, 0x40000000, 0x20000000,
+                           qdev_get_gpio_in(DEVICE(s->plic), PCIE_IRQ), true);
+    pci_bus = &PCI_BRIDGE(&XILINX_PCIE_HOST(dev)->root)->sec_bus;
+
+    pci_vga_init(pci_bus);
 
     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
         0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
@@ -457,6 +462,7 @@ static void riscv_virt_board_machine_init(MachineClass *mc)
     mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
     mc->init = riscv_virt_board_init;
     mc->max_cpus = 8; /* hardcoded limit in BBL */
+    mc->default_display = "std";
 }
 
 DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
-- 
2.17.1

[Qemu-devel] [PATCH v1 5/5] riscv64-softmmu.mak: Build Virtio Block support

[Alistair Francis]

Add build time support for the VirtIO block device. This allows us to
attach a drive using the virtio-blk-device.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 default-configs/riscv64-softmmu.mak | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index 73a421d3de..0be2cce269 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -10,3 +10,5 @@ CONFIG_PCI_XILINX=y
 
 CONFIG_VGA=y
 CONFIG_VGA_PCI=y
+
+CONFIG_VIRTIO_BLK=y
-- 
2.17.1

Re: [Qemu-devel] [PATCH v1 3/5] hw/riscv/virt: Connect the Xilinx PCIe

[Peter Maydell]

On 22 June 2018 at 20:30, Alistair Francis <alistair.francis@wdc.com> wrote:
> Connect the Xilinx PCIe device based on the device tree included in the
> HiFive Unleashed ROM.

Did you consider using the 'gpex' generic PCIe controller here?

thanks
-- PMM

Re: [Qemu-devel] [PATCH v1 3/5] hw/riscv/virt: Connect the Xilinx PCIe

[Michael Clark]

> On 23/06/2018, at 1:07 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> 
> On 22 June 2018 at 20:30, Alistair Francis <alistair.francis@wdc.com> wrote:
>> Connect the Xilinx PCIe device based on the device tree included in the
>> HiFive Unleashed ROM.
> 
> Did you consider using the 'gpex' generic PCIe controller here?

Yes. Alastair and I talked about this yesterday and we agreed in principle to using ‘gpex’ on the virt machine and the Xilinx PCIe on the SiFive U (’sifive_u’) machine, as this reflects one of the IP configurations of SiFive’s Coreplex U series when run on FPGA.

By changing this patch to add Xilinx PCIe to ‘sifive_u’, we can plug IO devices into the U series machine, and instead add gpex to RISC-V virt. i.e. vendor agnostic generic PCIe controller for virt. We would like ‘virt’ to be a potential vendor agnostic hardware target when we have kvm, so using gpex fits with this strategy (speaking from a RISC-V perspective not a SiFive perspective).

Re: [Qemu-devel] [PATCH v1 0/5] Connect a PCIe host and graphics support to RISC-V

[Palmer Dabbelt]

On Fri, 22 Jun 2018 12:28:14 PDT (-0700), alistair.francis@wdc.com wrote:
> Alistair Francis (5):
>   hw/riscv/virtio: Set the soc device tree node as a simple-bus
>   hw/riscv/virt: Increase the number of interrupts
>   hw/riscv/virt: Connect the Xilinx PCIe
>   hw/riscv/virt: Connect a VGA PCIe device
>   riscv64-softmmu.mak: Build Virtio Block support
>
>  default-configs/riscv32-softmmu.mak |  6 +++
>  default-configs/riscv64-softmmu.mak |  8 ++++
>  hw/riscv/virt.c                     | 73 ++++++++++++++++++++++++++++-
>  include/hw/riscv/virt.h             |  6 ++-
>  4 files changed, 90 insertions(+), 3 deletions(-)

Sorry I'm so slow here, I'm still chewing through my patch backlog.  It looks 
like this hasn't made it upstream yet.  I rebased it on top of master but have 
yet to figure out how to make it work, though I think that's on the Linux side.

I haven't yet looked at the code, but I like the functionality so I don't want 
to lose this.  Can you submit a v2 that applies cleanly to master, or do you 
want me to deal with it?

Re: [Qemu-devel] [PATCH v1 0/5] Connect a PCIe host and graphics support toRISC-V

[Alistair]

Hey,

Sorry for the top post. I’m on holidays at the moment and will be back next week.

I have sent a V2 to the list, I don’t think I CCed you as I know your busy. Once the 3.1 merge window opens I’ll send a new version with all the comments I have received.

Alistair

From: Palmer Dabbelt
Sent: Thursday, 2 August 2018 10:44 AM
To: alistair.francis@wdc.com
Cc: qemu-devel@nongnu.org; alistair.francis@wdc.com; alistair23@gmail.com; Michael Clark
Subject: Re: [PATCH v1 0/5] Connect a PCIe host and graphics support toRISC-V

On Fri, 22 Jun 2018 12:28:14 PDT (-0700), alistair.francis@wdc.com wrote:
> Alistair Francis (5):
>   hw/riscv/virtio: Set the soc device tree node as a simple-bus
>   hw/riscv/virt: Increase the number of interrupts
>   hw/riscv/virt: Connect the Xilinx PCIe
>   hw/riscv/virt: Connect a VGA PCIe device
>   riscv64-softmmu.mak: Build Virtio Block support
>
>  default-configs/riscv32-softmmu.mak |  6 +++
>  default-configs/riscv64-softmmu.mak |  8 ++++
>  hw/riscv/virt.c                     | 73 ++++++++++++++++++++++++++++-
>  include/hw/riscv/virt.h             |  6 ++-
>  4 files changed, 90 insertions(+), 3 deletions(-)

Sorry I'm so slow here, I'm still chewing through my patch backlog.  It looks 
like this hasn't made it upstream yet.  I rebased it on top of master but have 
yet to figure out how to make it work, though I think that's on the Linux side.

I haven't yet looked at the code, but I like the functionality so I don't want 
to lose this.  Can you submit a v2 that applies cleanly to master, or do you 
want me to deal with it?