From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, alistair23@gmail.com, mjc@sifive.com
Subject: [Qemu-devel] [PATCH v2 0/6] Connect a PCIe host and graphics support to RISC-V
Date: Mon, 9 Jul 2018 17:27:47 -0700 [thread overview]
Message-ID: <cover.1531182400.git.alistair.francis@wdc.com> (raw)
V2:
- Use the gpex PCIe host for virt
- Add support for SiFive U PCIe
Alistair Francis (6):
hw/riscv/virtio: Set the soc device tree node as a simple-bus
hw/riscv/virt: Increase the number of interrupts
hw/riscv/virt: Connect the gpex PCIe
hw/riscv/virt: Connect a VGA PCIe device
hw/riscv/sifive_u: Connect the Xilinx PCIe
riscv64-softmmu.mak: Build Virtio Block support
default-configs/riscv32-softmmu.mak | 7 ++++
default-configs/riscv64-softmmu.mak | 9 ++++
hw/riscv/sifive_u.c | 64 ++++++++++++++++++++++++++++
hw/riscv/virt.c | 65 ++++++++++++++++++++++++++++-
include/hw/riscv/sifive_u.h | 4 +-
include/hw/riscv/virt.h | 6 ++-
6 files changed, 151 insertions(+), 4 deletions(-)
--
2.17.1
next reply other threads:[~2018-07-10 0:28 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-10 0:27 Alistair Francis [this message]
2018-07-10 0:27 ` [Qemu-devel] [PATCH v2 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus Alistair Francis
2018-07-10 0:28 ` [Qemu-devel] [PATCH v2 2/6] hw/riscv/virt: Increase the number of interrupts Alistair Francis
2018-07-10 0:28 ` [Qemu-devel] [PATCH v2 3/6] hw/riscv/virt: Connect the gpex PCIe Alistair Francis
2018-07-10 0:28 ` [Qemu-devel] [PATCH v2 4/6] hw/riscv/virt: Connect a VGA PCIe device Alistair Francis
2018-07-10 0:28 ` [Qemu-devel] [PATCH v2 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe Alistair Francis
2018-07-10 0:28 ` [Qemu-devel] [PATCH v2 6/6] riscv64-softmmu.mak: Build Virtio Block support Alistair Francis
2018-07-10 1:54 ` Michael Clark
2018-07-11 0:10 ` Alistair Francis
2018-07-11 0:14 ` Alistair Francis
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