From: Alistair Francis <Alistair.Francis@wdc.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"mjc@sifive.com" <mjc@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
"alistair23@gmail.com" <alistair23@gmail.com>,
"stephen@eideticom.com" <stephen@eideticom.com>,
"palmer@sifive.com" <palmer@sifive.com>
Subject: [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V
Date: Thu, 4 Oct 2018 20:06:08 +0000 [thread overview]
Message-ID: <cover.1538683492.git.alistair.francis@wdc.com> (raw)
V5:
- Rebase
- Include pci.mak in the default configs
V4:
- Fix the spike device tree
- Don't use stdvga device
V3:
- Remove Makefile config changes
- Connect a network adapter to the virt device
V2:
- Use the gpex PCIe host for virt
- Add support for SiFive U PCIe
Alistair Francis (5):
hw/riscv/virt: Increase the number of interrupts
hw/riscv/virt: Connect the gpex PCIe
riscv: Enable VGA and PCIE_VGA
hw/riscv/sifive_u: Connect the Xilinx PCIe
hw/riscv/virt: Connect a VirtIO net PCIe device
default-configs/riscv32-softmmu.mak | 10 +++-
default-configs/riscv64-softmmu.mak | 10 +++-
hw/riscv/sifive_u.c | 64 +++++++++++++++++++++++++
hw/riscv/virt.c | 72 +++++++++++++++++++++++++++++
include/hw/riscv/sifive_u.h | 4 +-
include/hw/riscv/virt.h | 6 ++-
6 files changed, 161 insertions(+), 5 deletions(-)
--
2.17.1
next reply other threads:[~2018-10-04 20:06 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-04 20:06 Alistair Francis [this message]
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 1/5] hw/riscv/virt: Increase the number of interrupts Alistair Francis
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 2/5] hw/riscv/virt: Connect the gpex PCIe Alistair Francis
2018-10-25 18:47 ` Peter Maydell
2018-10-30 21:39 ` Alistair Francis
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 3/5] riscv: Enable VGA and PCIE_VGA Alistair Francis
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 4/5] hw/riscv/sifive_u: Connect the Xilinx PCIe Alistair Francis
2018-10-04 20:06 ` [Qemu-devel] [PATCH v5 5/5] hw/riscv/virt: Connect a VirtIO net PCIe device Alistair Francis
2018-10-10 12:26 ` [Qemu-devel] [PATCH v5 0/5] Connect a PCIe host and graphics support to RISC-V Andrea Bolognani
2018-10-10 13:11 ` Stephen Bates
2018-10-10 13:43 ` Andrea Bolognani
2018-10-10 17:24 ` Stephen Bates
2018-10-10 17:32 ` Stephen Bates
2018-10-10 18:01 ` Alistair
2018-10-10 18:47 ` Stephen Bates
2018-10-10 19:53 ` Alistair
2018-10-11 5:45 ` Andrea Bolognani
2018-10-10 19:01 ` Stephen Bates
2018-10-10 19:55 ` Alistair
2018-10-10 17:57 ` Alistair
2018-10-11 5:59 ` Andrea Bolognani
2018-10-11 7:55 ` Richard W.M. Jones
2018-10-11 12:00 ` Peter Maydell
2018-10-11 8:01 ` Richard W.M. Jones
2018-10-11 11:45 ` Richard W.M. Jones
2018-10-11 12:15 ` Andrea Bolognani
2018-10-11 12:25 ` Stephen Bates
2018-10-11 17:40 ` Alistair Francis
2018-10-12 13:46 ` Andrea Bolognani
2018-10-12 16:12 ` Alistair Francis
2018-10-15 14:39 ` Andrea Bolognani
2018-10-15 16:59 ` Alistair Francis
2018-10-16 7:38 ` Andrea Bolognani
2018-10-16 14:11 ` Andrea Bolognani
2018-10-16 14:55 ` Andrea Bolognani
2018-10-16 17:31 ` Stephen Bates
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