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From: Alistair Francis <Alistair.Francis@wdc.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
	"alistair23@gmail.com" <alistair23@gmail.com>
Subject: [Qemu-devel] [PATCH v6 0/5] Connect a PCIe host and graphics support to RISC-V
Date: Tue, 30 Oct 2018 22:17:41 +0000	[thread overview]
Message-ID: <cover.1540937826.git.alistair.francis@wdc.com> (raw)

V6:
 - Fix the interrupt issue for the GPEX device
V5:
 - Rebase
 - Include pci.mak in the default configs
V4:
 - Fix the spike device tree
 - Don't use stdvga device
V3:
 - Remove Makefile config changes
 - Connect a network adapter to the virt device
V2:
 - Use the gpex PCIe host for virt
 - Add support for SiFive U PCIe


Alistair Francis (5):
  hw/riscv/virt: Increase the number of interrupts
  hw/riscv/virt: Connect the gpex PCIe
  riscv: Enable VGA and PCIE_VGA
  hw/riscv/sifive_u: Connect the Xilinx PCIe
  hw/riscv/virt: Connect a VirtIO net PCIe device

 default-configs/riscv32-softmmu.mak |  10 ++-
 default-configs/riscv64-softmmu.mak |  10 ++-
 hw/riscv/sifive_u.c                 |  64 ++++++++++++++
 hw/riscv/virt.c                     | 125 ++++++++++++++++++++++++++++
 include/hw/riscv/sifive_u.h         |   4 +-
 include/hw/riscv/virt.h             |   8 +-
 6 files changed, 216 insertions(+), 5 deletions(-)

-- 
2.19.1

             reply	other threads:[~2018-10-30 22:17 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-30 22:17 Alistair Francis [this message]
2018-10-30 22:17 ` [Qemu-devel] [PATCH v6 1/5] hw/riscv/virt: Increase the number of interrupts Alistair Francis
2018-10-30 22:17 ` [Qemu-devel] [PATCH v6 2/5] hw/riscv/virt: Connect the gpex PCIe Alistair Francis
2018-11-05 13:23   ` Bin Meng
2018-11-05 19:47     ` Alistair Francis
2018-11-06  6:45       ` Bin Meng
2018-11-07 21:46         ` Alistair Francis
2018-10-30 22:18 ` [Qemu-devel] [PATCH v6 3/5] riscv: Enable VGA and PCIE_VGA Alistair Francis
2018-10-30 22:18 ` [Qemu-devel] [PATCH v6 4/5] hw/riscv/sifive_u: Connect the Xilinx PCIe Alistair Francis
2018-10-30 22:18 ` [Qemu-devel] [PATCH v6 5/5] hw/riscv/virt: Connect a VirtIO net PCIe device Alistair Francis
2018-10-31 14:51 ` [Qemu-devel] [PATCH v6 0/5] Connect a PCIe host and graphics support to RISC-V Andrea Bolognani
2018-10-31 20:10   ` Alistair Francis
2018-11-01  8:20     ` Andrea Bolognani
2018-11-07 21:47       ` Alistair Francis
2018-11-13 15:52         ` Andrea Bolognani

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