[Qemu-devel] [PATCH for 4.1 v3 0/6] RISC-V: Allow specifying CPU ISA via command line

[Alistair Francis <Alistair.Francis@wdc.com>]

This patch series adds a generic RISC-V CPU that can be generated at run
time based on the ISA string specified to QEMU via the -cpu argument. This
is supported on the virt and spike boards allowing users to specify the

RISC-V extensions as well as the ISA version.
As part of the conversion we have deprecated the version specifi Spike
machines.

v3:
 - Ensure a minimal length so we don't run off the end of the string.
 - Don't parse the rv32/rv64 in the riscv_generate_cpu_init() loop
v2:
 - Keep the any CPU for linux-user

Alistair Francis (6):
  linux-user/riscv: Add the CPU type as a comment
  target/riscv: Fall back to generating a RISC-V CPU
  target/riscv: Create settable CPU properties
  riscv: virt: Allow specifying a CPU via commandline
  target/riscv: Remove the generic no MMU CPUs
  riscv: Add a generic spike machine

 hw/riscv/spike.c              | 106 +++++++++++++++++++++++-
 hw/riscv/virt.c               |   3 +-
 linux-user/riscv/target_elf.h |   1 +
 target/riscv/cpu.c            | 147 +++++++++++++++++++++++++++++++++-
 target/riscv/cpu.h            |  12 ++-
 5 files changed, 262 insertions(+), 7 deletions(-)

-- 
2.21.0