[PATCH v1 00/15] RISC-V: Update the Hypervisor spec to v0.6

[Alistair Francis <alistair.francis@wdc.com>]

This series updates the experimental QEMU RISC-V Hypervisor spec to the
v0.6 draft implementation.

THis includes support for the new 2-stage lookup instructions and the new
CSRs.

This was tested by running 32-bit and 64-bit Xvisor on QEMU and starting
Linux guests.



Alistair Francis (15):
  target/riscv: Set access as data_load when validating stage-2 PTEs
  target/riscv: Report errors validating 2nd-stage PTEs
  target/riscv: Move the hfence instructions to the rvh decode
  target/riscv: Implement checks for hfence
  target/riscv: Allow setting a two-stage lookup in the virt status
  target/riscv: Allow generating hlv/hlvx/hsv instructions
  target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
  target/riscv: Don't allow guest to write to htinst
  target/riscv: Convert MSTATUS MTL to GVA
  target/riscv: Fix the interrupt cause code
  target/riscv: Update the Hypervisor trap return/entry
  target/riscv: Update the CSRs to the v0.6 Hyp extension
  target/riscv: Only support a single VSXL length
  target/riscv: Only support little endian guests
  target/riscv: Support the v0.6 Hypervisor extension CRSs

 target/riscv/cpu.h                            |   2 +
 target/riscv/cpu_bits.h                       |  19 +-
 target/riscv/cpu_helper.c                     | 114 +++---
 target/riscv/csr.c                            |  61 ++-
 target/riscv/helper.h                         |   8 +
 target/riscv/insn32-64.decode                 |   5 +
 target/riscv/insn32.decode                    |  17 +-
 .../riscv/insn_trans/trans_privileged.inc.c   |  40 --
 target/riscv/insn_trans/trans_rvh.inc.c       | 377 ++++++++++++++++++
 target/riscv/op_helper.c                      | 135 ++++++-
 target/riscv/translate.c                      |  11 +-
 11 files changed, 674 insertions(+), 115 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvh.inc.c

-- 
2.26.2