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Sun, 26 Apr 2020 14:02:37 -0400 (EDT) From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 0/9] RISC-V Add the OpenTitan Machine Date: Sat, 25 Apr 2020 04:28:57 -0700 Message-Id: X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=66.111.4.29; envelope-from=alistair@alistair23.me; helo=out5-smtp.messagingengine.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 14:02:38 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.29 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis OpenTitan is an open source silicon Root of Trust (RoT) project. This series adds initial support for the OpenTitan machine to QEMU. This series add the Ibex CPU to the QEMU RISC-V target. It then adds the OpenTitan machine, the Ibex UART and the Ibex PLIC. The UART has been tested sending data, but not receiving as there is currently no UART receiving support in Tock. With this series QEMU can boot the OpenTitan ROM, Tock OS and a Tock userspace app. The Ibex PLIC is similar to the RISC-V PLIC (and is based on the QEMU implementation) with some differences. The hope is that the Ibex PLIC will converge to follow the RISC-V spec. As that happens I want to update the QEMU Ibex PLIC and hopefully eventually replace the current PLIC as the implementation is a little overlay complex. For more details on OpenTitan, see here: https://docs.opentitan.org/ Alistair Francis (9): riscv/boot: Add a missing header include target/riscv: Don't overwrite the reset vector target/riscv: Add the lowRISC Ibex CPU riscv: Initial commit of OpenTitan machine hw/char: Initial commit of Ibex UART hw/intc: Initial commit of lowRISC Ibex PLIC riscv/opentitan: Connect the PLIC device riscv/opentitan: Connect the UART device target/riscv: Use a smaller guess size for no-MMU PMP MAINTAINERS | 14 + default-configs/riscv32-softmmu.mak | 1 + default-configs/riscv64-softmmu.mak | 11 +- hw/char/Makefile.objs | 1 + hw/char/ibex_uart.c | 487 ++++++++++++++++++++++++++++ hw/intc/Makefile.objs | 1 + hw/intc/ibex_plic.c | 261 +++++++++++++++ hw/riscv/Kconfig | 9 + hw/riscv/Makefile.objs | 1 + hw/riscv/opentitan.c | 204 ++++++++++++ include/hw/char/ibex_uart.h | 110 +++++++ include/hw/intc/ibex_plic.h | 63 ++++ include/hw/riscv/boot.h | 1 + include/hw/riscv/opentitan.h | 79 +++++ target/riscv/cpu.c | 30 +- target/riscv/cpu.h | 1 + target/riscv/pmp.c | 19 +- 17 files changed, 1278 insertions(+), 15 deletions(-) create mode 100644 hw/char/ibex_uart.c create mode 100644 hw/intc/ibex_plic.c create mode 100644 hw/riscv/opentitan.c create mode 100644 include/hw/char/ibex_uart.h create mode 100644 include/hw/intc/ibex_plic.h create mode 100644 include/hw/riscv/opentitan.h -- 2.26.2