* [PATCH v2 1/2] riscv: sifive_e: Manually define the machine
2020-05-20 16:28 [PATCH v2 0/2] Add support for the HiFive1 revB Alistair Francis
@ 2020-05-20 16:28 ` Alistair Francis
2020-05-20 16:28 ` [PATCH v2 2/2] sifive_e: Support the revB machine Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2020-05-20 16:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, philmd, palmer, bmeng.cn, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_e.h | 4 ++++
hw/riscv/sifive_e.c | 41 +++++++++++++++++++++++++++----------
2 files changed, 34 insertions(+), 11 deletions(-)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 25ce7aa9d5..414992119e 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -47,6 +47,10 @@ typedef struct SiFiveEState {
SiFiveESoCState soc;
} SiFiveEState;
+#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
+#define RISCV_E_MACHINE(obj) \
+ OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
+
enum {
SIFIVE_E_DEBUG,
SIFIVE_E_MROM,
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index b53109521e..472a98970b 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -79,7 +79,7 @@ static void riscv_sifive_e_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_e_memmap;
- SiFiveEState *s = g_new0(SiFiveEState, 1);
+ SiFiveEState *s = RISCV_E_MACHINE(machine);
MemoryRegion *sys_mem = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
int i;
@@ -115,6 +115,35 @@ static void riscv_sifive_e_init(MachineState *machine)
}
}
+static void sifive_e_machine_instance_init(Object *obj)
+{
+}
+
+static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "RISC-V Board compatible with SiFive E SDK";
+ mc->init = riscv_sifive_e_init;
+ mc->max_cpus = 1;
+ mc->default_cpu_type = SIFIVE_E_CPU;
+}
+
+static const TypeInfo sifive_e_machine_typeinfo = {
+ .name = MACHINE_TYPE_NAME("sifive_e"),
+ .parent = TYPE_MACHINE,
+ .class_init = sifive_e_machine_class_init,
+ .instance_init = sifive_e_machine_instance_init,
+ .instance_size = sizeof(SiFiveEState),
+};
+
+static void sifive_e_machine_init_register_types(void)
+{
+ type_register_static(&sifive_e_machine_typeinfo);
+}
+
+type_init(sifive_e_machine_init_register_types)
+
static void riscv_sifive_e_soc_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -214,16 +243,6 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
&s->xip_mem);
}
-static void riscv_sifive_e_machine_init(MachineClass *mc)
-{
- mc->desc = "RISC-V Board compatible with SiFive E SDK";
- mc->init = riscv_sifive_e_init;
- mc->max_cpus = 1;
- mc->default_cpu_type = SIFIVE_E_CPU;
-}
-
-DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
-
static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
--
2.26.2
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH v2 2/2] sifive_e: Support the revB machine
2020-05-20 16:28 [PATCH v2 0/2] Add support for the HiFive1 revB Alistair Francis
2020-05-20 16:28 ` [PATCH v2 1/2] riscv: sifive_e: Manually define the machine Alistair Francis
@ 2020-05-20 16:28 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2020-05-20 16:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, philmd, palmer, bmeng.cn, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_e.h | 1 +
hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++----
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 414992119e..0d3cd07fcc 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -45,6 +45,7 @@ typedef struct SiFiveEState {
/*< public >*/
SiFiveESoCState soc;
+ bool revb;
} SiFiveEState;
#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 472a98970b..cb7818341b 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine)
memmap[SIFIVE_E_DTIM].base, main_mem);
/* Mask ROM reset vector */
- uint32_t reset_vec[2] = {
- 0x204002b7, /* 0x1000: lui t0,0x20400 */
- 0x00028067, /* 0x1004: jr t0 */
- };
+ uint32_t reset_vec[2];
+
+ if (s->revb) {
+ reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
+ } else {
+ reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
+ }
+ reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
/* copy in the reset vector in little_endian byte order */
for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
@@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine)
}
}
+static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
+{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ return s->revb;
+}
+
+static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
+{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ s->revb = value;
+}
+
static void sifive_e_machine_instance_init(Object *obj)
{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ s->revb = false;
+ object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
+ sifive_e_machine_set_revb, NULL);
+ object_property_set_description(obj, "revb",
+ "Set on to tell QEMU that it should model "
+ "the revB HiFive1 board",
+ NULL);
}
static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
--
2.26.2
^ permalink raw reply related [flat|nested] 3+ messages in thread