From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com
Subject: [PATCH v1 0/3] A few RISC-V fixes
Date: Tue, 30 Jun 2020 13:12:05 -0700 [thread overview]
Message-ID: <cover.1593547870.git.alistair.francis@wdc.com> (raw)
This series has a few fixes for RISC-V.
Alistair Francis (3):
hw/char: Convert the Ibex UART to use the qdev Clock model
hw/riscv: Allow 64 bit access to SiFive CLINT
target/riscv: Regen floating point rounding mode in dynamic mode
include/hw/char/ibex_uart.h | 2 ++
hw/char/ibex_uart.c | 19 ++++++++++++++++++-
hw/riscv/sifive_clint.c | 2 +-
target/riscv/translate.c | 2 +-
4 files changed, 22 insertions(+), 3 deletions(-)
--
2.27.0
next reply other threads:[~2020-06-30 20:22 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-30 20:12 Alistair Francis [this message]
2020-06-30 20:12 ` [PATCH v1 1/3] hw/char: Convert the Ibex UART to use the qdev Clock model Alistair Francis
2020-07-03 7:42 ` Philippe Mathieu-Daudé
2020-07-07 17:20 ` Alistair Francis
2020-06-30 20:12 ` [PATCH v1 2/3] hw/riscv: Allow 64 bit access to SiFive CLINT Alistair Francis
2020-07-01 0:19 ` LIU Zhiwei
2020-07-02 3:33 ` Alistair Francis
2020-07-03 7:44 ` Philippe Mathieu-Daudé
2020-06-30 20:12 ` [PATCH v1 3/3] target/riscv: Regen floating point rounding mode in dynamic mode Alistair Francis
2020-06-30 21:51 ` Richard Henderson
2020-07-01 0:17 ` LIU Zhiwei
2020-07-03 1:24 ` Bin Meng
2020-07-07 17:23 ` Alistair Francis
2020-07-08 0:36 ` Bin Meng
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