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From: Zong Li <zong.li@sifive.com>
To: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
	sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Zong Li <zong.li@sifive.com>
Subject: [PATCH v3 0/3] Fix some PMP implementation
Date: Tue, 21 Jul 2020 20:40:49 +0800	[thread overview]
Message-ID: <cover.1595335112.git.zong.li@sifive.com> (raw)

This patch set contains the fixes for wrong index of pmpcfg CSR on rv64,
and the pmp range in CSR function table. After 3rd version of this patch
series, we also fix the PMP wrong checking problem.

Changed in v3:
 - Refine the implementation. Suggested by Bin Meng.
 - Add fix for PMP wrong checking

Changed in v2:
 - Move out the shifting operation from loop. Suggested by Bin Meng.

Zong Li (3):
  target/riscv: Fix the range of pmpcfg of CSR funcion table
  target/riscv/pmp.c: Fix the index offset on RV64
  target/riscv: Fix the translation of physical address

 target/riscv/cpu_helper.c | 3 ++-
 target/riscv/csr.c        | 2 +-
 target/riscv/pmp.c        | 8 ++++++++
 3 files changed, 11 insertions(+), 2 deletions(-)

-- 
2.27.0



             reply	other threads:[~2020-07-21 12:43 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-21 12:40 Zong Li [this message]
2020-07-21 12:40 ` [PATCH v3 1/3] target/riscv: Fix the range of pmpcfg of CSR funcion table Zong Li
2020-07-21 12:40 ` [PATCH v3 2/3] target/riscv/pmp.c: Fix the index offset on RV64 Zong Li
2020-07-22  4:57   ` Bin Meng
2020-07-23  3:19     ` Zong Li
2020-07-21 12:40 ` [PATCH v3 3/3] target/riscv: Fix the translation of physical address Zong Li
2020-07-22  9:08   ` Alexander Richardson
2020-07-23  3:20     ` Zong Li

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