From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, richard.henderson@linaro.org,
bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com
Subject: [PATCH v1 0/5] Fix the Hypervisor access functions
Date: Fri, 23 Oct 2020 08:25:59 -0700 [thread overview]
Message-ID: <cover.1603466725.git.alistair.francis@wdc.com> (raw)
Richard pointed out that the Hypervisor access functions don't work
correctly, see:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg751540.html.
This seris fixes them up by adding a new MMU index for the virtualised
state.
Alistair Francis (5):
target/riscv: Add a virtualised MMU Mode
target/riscv: Set the virtualised MMU mode when doing hyp accesses
target/riscv: Remove the HS_TWO_STAGE flag
target/riscv: Remove the hyp load and store functions
target/riscv: Split the Hypervisor execute load helpers
target/riscv/cpu-param.h | 2 +-
target/riscv/cpu.h | 7 +-
target/riscv/cpu_bits.h | 1 -
target/riscv/helper.h | 6 +-
target/riscv/cpu_helper.c | 67 ++++++-------
target/riscv/op_helper.c | 90 ++---------------
target/riscv/insn_trans/trans_rvh.c.inc | 127 +++++++-----------------
7 files changed, 82 insertions(+), 218 deletions(-)
--
2.28.0
next reply other threads:[~2020-10-23 16:14 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 15:25 Alistair Francis [this message]
2020-10-23 15:26 ` [PATCH v1 1/5] target/riscv: Add a virtualised MMU Mode Alistair Francis
2020-10-23 19:13 ` Richard Henderson
2020-10-23 23:29 ` Alistair Francis
2020-10-23 15:26 ` [PATCH v1 2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Alistair Francis
2020-10-23 15:26 ` [PATCH v1 3/5] target/riscv: Remove the HS_TWO_STAGE flag Alistair Francis
2020-10-23 15:26 ` [PATCH v1 4/5] target/riscv: Remove the hyp load and store functions Alistair Francis
2020-10-23 15:26 ` [PATCH v1 5/5] target/riscv: Split the Hypervisor execute load helpers Alistair Francis
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