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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, alistair.francis@wdc.com,
	bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com
Subject: [PATCH v3 0/7]  Fix the Hypervisor access functions
Date: Tue,  3 Nov 2020 11:50:52 -0800	[thread overview]
Message-ID: <cover.1604432950.git.alistair.francis@wdc.com> (raw)

Richard pointed out that the Hypervisor access functions don't work
correctly, see:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg751540.html.
This seris fixes them up by adding a new MMU index for the virtualised
state.

v3:
 - Only set the virtualised MMU mode for HLX ops
v2:
 - Use only 6 MMU modes instead of 8

Alistair Francis (6):
  target/riscv: Add a virtualised MMU Mode
  target/riscv: Set the virtualised MMU mode when doing hyp accesses
  target/riscv: Remove the HS_TWO_STAGE flag
  target/riscv: Remove the hyp load and store functions
  target/riscv: Remove the Hypervisor access check function
  target/riscv: Split the Hypervisor execute load helpers

Yifei Jiang (1):
  target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit

 target/riscv/cpu-param.h                |  10 +-
 target/riscv/cpu.h                      |  43 ++--
 target/riscv/cpu_bits.h                 |  20 +-
 target/riscv/helper.h                   |   5 +-
 target/riscv/cpu.c                      |   8 +-
 target/riscv/cpu_helper.c               |  99 ++++------
 target/riscv/csr.c                      |  18 +-
 target/riscv/op_helper.c                | 135 +------------
 target/riscv/translate.c                |   2 +
 target/riscv/insn_trans/trans_rvh.c.inc | 248 +++++++++++++++---------
 10 files changed, 260 insertions(+), 328 deletions(-)

-- 
2.28.0



             reply	other threads:[~2020-11-03 20:03 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-03 19:50 Alistair Francis [this message]
2020-11-03 19:50 ` [PATCH v3 1/7] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Alistair Francis
2020-11-03 19:52   ` Alistair Francis
2020-11-03 20:19   ` Richard Henderson
2020-11-03 19:50 ` [PATCH v3 2/7] target/riscv: Add a virtualised MMU Mode Alistair Francis
2020-11-03 20:20   ` Richard Henderson
2020-11-04  4:42     ` Alistair Francis
2020-11-03 19:51 ` [PATCH v3 3/7] target/riscv: Set the virtualised MMU mode when doing hyp accesses Alistair Francis
2020-11-03 19:51 ` [PATCH v3 4/7] target/riscv: Remove the HS_TWO_STAGE flag Alistair Francis
2020-11-03 19:51 ` [PATCH v3 5/7] target/riscv: Remove the hyp load and store functions Alistair Francis
2020-11-03 19:51 ` [PATCH v3 6/7] target/riscv: Remove the Hypervisor access check function Alistair Francis
2020-11-03 20:26   ` Richard Henderson
2020-11-03 19:51 ` [PATCH v3 7/7] target/riscv: Split the Hypervisor execute load helpers Alistair Francis
2020-11-03 20:27   ` Richard Henderson

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