From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, richard.henderson@linaro.org,
bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com
Subject: [PATCH v4 0/5] Fix the Hypervisor access functions
Date: Tue, 3 Nov 2020 20:43:20 -0800 [thread overview]
Message-ID: <cover.1604464950.git.alistair.francis@wdc.com> (raw)
Richard pointed out that the Hypervisor access functions don't work
correctly, see:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg751540.html.
This seris fixes them up by adding a new MMU index for the virtualised
state.
v4:
- Consolidate the inline helper to a helper function
- Actually don't have a virtualised MMU index
v3:
- Don't use an external helper
v2:
- Use only 6 MMU modes instead of 8
Alistair Francis (5):
target/riscv: Add a virtualised MMU Mode
target/riscv: Set the virtualised MMU mode when doing hyp accesses
target/riscv: Remove the HS_TWO_STAGE flag
target/riscv: Remove the hyp load and store functions
target/riscv: Split the Hypervisor execute load helpers
target/riscv/cpu-param.h | 11 +-
target/riscv/cpu.h | 19 +++-
target/riscv/cpu_bits.h | 1 -
target/riscv/helper.h | 5 +-
target/riscv/cpu_helper.c | 62 +++++-----
target/riscv/op_helper.c | 124 +-------------------
target/riscv/translate.c | 2 +
target/riscv/insn_trans/trans_rvh.c.inc | 143 +++++++++---------------
8 files changed, 112 insertions(+), 255 deletions(-)
--
2.28.0
next reply other threads:[~2020-11-04 5:02 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-04 4:43 Alistair Francis [this message]
2020-11-04 4:43 ` [PATCH v4 1/5] target/riscv: Add a virtualised MMU Mode Alistair Francis
2020-11-04 16:24 ` Richard Henderson
2020-11-04 4:43 ` [PATCH v4 2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Alistair Francis
2020-11-04 4:43 ` [PATCH v4 3/5] target/riscv: Remove the HS_TWO_STAGE flag Alistair Francis
2020-11-04 4:43 ` [PATCH v4 4/5] target/riscv: Remove the hyp load and store functions Alistair Francis
2020-11-04 16:30 ` Richard Henderson
2020-11-04 4:43 ` [PATCH v4 5/5] target/riscv: Split the Hypervisor execute load helpers Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cover.1604464950.git.alistair.francis@wdc.com \
--to=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=bmeng.cn@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).