From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
alistair23@gmail.com
Subject: [PATCH v1 0/5] RISC-V: Convert the CSR access functions to use
Date: Wed, 17 Mar 2021 13:39:44 -0400 [thread overview]
Message-ID: <cover.1616002766.git.alistair.francis@wdc.com> (raw)
Alistair Francis (5):
target/riscv: Convert the RISC-V exceptions to an enum
target/riscv: Use the RiscVException enum for CSR predicates
target/riscv: Fix 32-bit HS mode access permissions
target/riscv: Use the RiscVException enum for CSR operations
target/riscv: Use RiscVException enum for CSR access
target/riscv/cpu.h | 28 +-
target/riscv/cpu_bits.h | 44 +--
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 4 +-
target/riscv/csr.c | 753 ++++++++++++++++++++++----------------
target/riscv/gdbstub.c | 8 +-
target/riscv/op_helper.c | 18 +-
7 files changed, 499 insertions(+), 358 deletions(-)
--
2.30.1
next reply other threads:[~2021-03-17 17:43 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-17 17:39 Alistair Francis [this message]
2021-03-17 17:39 ` [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-03-18 1:58 ` Bin Meng
2021-03-19 13:19 ` Alistair Francis
2021-03-17 17:39 ` [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates Alistair Francis
2021-03-17 19:44 ` Richard Henderson
2021-03-19 13:17 ` Alistair Francis
2021-03-17 17:39 ` [PATCH v1 3/5] target/riscv: Fix 32-bit HS mode access permissions Alistair Francis
2021-03-17 17:39 ` [PATCH v1 4/5] target/riscv: Use the RiscVException enum for CSR operations Alistair Francis
2021-03-17 17:40 ` [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access Alistair Francis
2021-03-18 13:25 ` Richard Henderson
2021-03-19 13:19 ` Alistair Francis
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