From: Konrad Schwarz <konrad.schwarz@siemens.com>
To: <qemu-devel@nongnu.org>
Cc: Konrad Schwarz <konrad.schwarz@siemens.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
Subject: [PATCH v2 0/5] Improve RISC-V debugging support.
Date: Tue, 4 Jan 2022 16:51:15 +0100 [thread overview]
Message-ID: <cover.1641309725.git.konrad.schwarz@siemens.com> (raw)
In-Reply-To: <00a79b65-288f-f17c-abe4-fcfd3f7971fd@oth-regensburg.de>
Added the files missing in v1 of this patch.
-- >8 --
1) Make the QEMU monitor `info registers' command more informative
2) Implement the QEMU monitor `print $register'
3) Introduce a new command `info gmem' to the QEMU monitor, which displays
a RISC-V hypervisor's guest's 2nd level paging tables similarly to the
existing `info mem' command.
4) Improve QEMU RISC-V target descriptions for GDB. In particular, add
type information for many control and status registers.
5) Extend the virtual `priv' register with hypervisor virtualization status.
Konrad Schwarz (5):
RISC-V: larger and more consistent register set for 'info registers'
RISC-V: monitor's print register functionality
RISC-V: 'info gmem' to show hypervisor guest -> physical address
translations
RISC-V: Typed CSRs in gdbserver
RISC-V: Add `v' (virtualization mode) bit to the `priv' virtual debug
register
gdb-xml/riscv-32bit-virtual.xml | 30 ++-
gdb-xml/riscv-64bit-virtual.xml | 30 ++-
hmp-commands-info.hx | 16 ++
include/monitor/hmp-target.h | 2 +
target/riscv/cpu.c | 327 ++++++++++++++++++++++++++---
target/riscv/csr.c | 2 +
target/riscv/csr32-op-gdbserver.h | 109 ++++++++++
target/riscv/csr64-op-gdbserver.h | 76 +++++++
target/riscv/gdb_csr_type_group.c | 16 ++
target/riscv/gdb_csr_type_group.h | 3 +
target/riscv/gdb_csr_types.c | 333 ++++++++++++++++++++++++++++++
target/riscv/gdb_csr_types.h | 3 +
target/riscv/gdbstub.c | 31 ++-
target/riscv/meson.build | 4 +-
target/riscv/monitor.c | 204 ++++++++++++++----
15 files changed, 1115 insertions(+), 71 deletions(-)
create mode 100644 target/riscv/csr32-op-gdbserver.h
create mode 100644 target/riscv/csr64-op-gdbserver.h
create mode 100644 target/riscv/gdb_csr_type_group.c
create mode 100644 target/riscv/gdb_csr_type_group.h
create mode 100644 target/riscv/gdb_csr_types.c
create mode 100644 target/riscv/gdb_csr_types.h
base-commit: 8627edfb3f1fca24a96a0954148885c3241c10f8
--
Konrad Schwarz
next prev parent reply other threads:[~2022-01-04 16:08 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-02 16:06 [PATCH v1 0/5] Improve RISC-V debugging support Konrad Schwarz
2022-01-02 16:06 ` [PATCH v1 1/5] RISC-V: larger and more consistent register set for 'info registers' Konrad Schwarz
2022-01-02 16:06 ` [PATCH v1 2/5] RISC-V: monitor's print register functionality Konrad Schwarz
2022-01-02 16:06 ` [PATCH v1 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations Konrad Schwarz
2022-01-02 16:06 ` [PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver Konrad Schwarz
2022-01-03 12:54 ` Ralf Ramsauer
2022-01-04 15:51 ` Konrad Schwarz [this message]
2022-01-04 15:51 ` [PATCH v2 1/5] RISC-V: larger and more consistent register set for 'info registers' Konrad Schwarz
2022-01-04 20:57 ` Richard Henderson
2022-01-05 12:38 ` Schwarz, Konrad
2022-01-05 18:21 ` Alex Bennée
2022-01-04 15:51 ` [PATCH v2 2/5] RISC-V: monitor's print register functionality Konrad Schwarz
2022-01-04 15:51 ` [PATCH v2 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations Konrad Schwarz
2022-01-04 22:03 ` Alistair Francis
2022-01-05 13:09 ` Schwarz, Konrad
2022-01-04 15:51 ` [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver Konrad Schwarz
2022-01-04 22:11 ` Alistair Francis
2022-01-05 13:25 ` Schwarz, Konrad
2022-01-04 23:01 ` Richard Henderson
2022-01-05 14:04 ` Schwarz, Konrad
2022-01-05 20:20 ` Richard Henderson
2022-01-05 18:43 ` Alex Bennée
2022-01-05 19:24 ` Schwarz, Konrad
2022-01-05 19:34 ` Alex Bennée
2022-01-04 15:51 ` [PATCH v2 5/5] RISC-V: Add `v' (virtualization mode) bit to the `priv' virtual debug register Konrad Schwarz
2022-01-02 16:06 ` [PATCH v1 " Konrad Schwarz
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