* [PATCH v3 01/20] ppc440_bamboo: Remove unnecessary memsets
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 02/20] ppc4xx: Introduce Ppc4xxSdramBank struct BALATON Zoltan
` (19 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
In ppc4xx_sdram_init() the struct is allocated with g_new0() so no
need to clear its elements. In the bamboo machine init memset can be
replaced with array initialiser which is shorter.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc440_bamboo.c | 6 ++----
hw/ppc/ppc4xx_devs.c | 8 ++------
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index ea945a1c99..5ec82fa8c2 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -169,8 +169,8 @@ static void bamboo_init(MachineState *machine)
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
- hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
- hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
+ hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS] = {0};
+ hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS] = {0};
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
@@ -205,8 +205,6 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
- memset(ram_bases, 0, sizeof(ram_bases));
- memset(ram_sizes, 0, sizeof(ram_sizes));
ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index ce38ae65e6..b4cd10f735 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -363,12 +363,8 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
sdram->irq = irq;
sdram->nbanks = nbanks;
sdram->ram_memories = ram_memories;
- memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
- memcpy(sdram->ram_bases, ram_bases,
- nbanks * sizeof(hwaddr));
- memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
- memcpy(sdram->ram_sizes, ram_sizes,
- nbanks * sizeof(hwaddr));
+ memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr));
+ memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr));
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v3 02/20] ppc4xx: Introduce Ppc4xxSdramBank struct
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 01/20] ppc440_bamboo: Remove unnecessary memsets BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack BALATON Zoltan
` (18 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Instead of storing sdram bank parameters in unrelated arrays put them
in a struct so it's clear they belong to the same bank and simplify
the state struct using this bank type.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/ppc/ppc440_uc.c | 49 +++++++++++++++++-----------------
hw/ppc/ppc4xx_devs.c | 59 ++++++++++++++++++++---------------------
include/hw/ppc/ppc4xx.h | 8 ++++++
3 files changed, 61 insertions(+), 55 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 53e981ddf4..db33334e29 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -16,7 +16,7 @@
#include "qemu/module.h"
#include "hw/irq.h"
#include "exec/memory.h"
-#include "hw/ppc/ppc.h"
+#include "hw/ppc/ppc4xx.h"
#include "hw/qdev-properties.h"
#include "hw/pci/pci.h"
#include "sysemu/block-backend.h"
@@ -485,11 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
typedef struct ppc440_sdram_t {
uint32_t addr;
int nbanks;
- MemoryRegion containers[4]; /* used for clipping */
- MemoryRegion *ram_memories;
- hwaddr ram_bases[4];
- hwaddr ram_sizes[4];
- uint32_t bcr[4];
+ Ppc4xxSdramBank bank[4];
} ppc440_sdram_t;
enum {
@@ -570,23 +566,23 @@ static uint64_t sdram_size(uint32_t bcr)
static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
uint32_t bcr, int enabled)
{
- if (sdram->bcr[i] & 1) {
+ if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
memory_region_del_subregion(get_system_memory(),
- &sdram->containers[i]);
- memory_region_del_subregion(&sdram->containers[i],
- &sdram->ram_memories[i]);
- object_unparent(OBJECT(&sdram->containers[i]));
+ &sdram->bank[i].container);
+ memory_region_del_subregion(&sdram->bank[i].container,
+ &sdram->bank[i].ram);
+ object_unparent(OBJECT(&sdram->bank[i].container));
}
- sdram->bcr[i] = bcr & 0xffe0ffc1;
+ sdram->bank[i].bcr = bcr & 0xffe0ffc1;
if (enabled && (bcr & 1)) {
- memory_region_init(&sdram->containers[i], NULL, "sdram-containers",
+ memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
sdram_size(bcr));
- memory_region_add_subregion(&sdram->containers[i], 0,
- &sdram->ram_memories[i]);
+ memory_region_add_subregion(&sdram->bank[i].container, 0,
+ &sdram->bank[i].ram);
memory_region_add_subregion(get_system_memory(),
sdram_base(bcr),
- &sdram->containers[i]);
+ &sdram->bank[i].container);
}
}
@@ -595,9 +591,9 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->ram_sizes[i] != 0) {
- sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i],
- sdram->ram_sizes[i]), 1);
+ if (sdram->bank[i].size != 0) {
+ sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
} else {
sdram_set_bcr(sdram, i, 0, 0);
}
@@ -614,9 +610,9 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
case SDRAM_R1BAS:
case SDRAM_R2BAS:
case SDRAM_R3BAS:
- if (sdram->ram_sizes[dcrn - SDRAM_R0BAS]) {
- ret = sdram_bcr(sdram->ram_bases[dcrn - SDRAM_R0BAS],
- sdram->ram_sizes[dcrn - SDRAM_R0BAS]);
+ if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
+ ret = sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
+ sdram->bank[dcrn - SDRAM_R0BAS].size);
}
break;
case SDRAM_CONF1HB:
@@ -701,12 +697,15 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
int do_init)
{
ppc440_sdram_t *sdram;
+ int i;
sdram = g_malloc0(sizeof(*sdram));
sdram->nbanks = nbanks;
- sdram->ram_memories = ram_memories;
- memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr));
- memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr));
+ for (i = 0; i < nbanks; i++) {
+ sdram->bank[i].ram = ram_memories[i];
+ sdram->bank[i].base = ram_bases[i];
+ sdram->bank[i].size = ram_sizes[i];
+ }
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index b4cd10f735..1226ec4aa9 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -42,10 +42,7 @@ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
struct ppc4xx_sdram_t {
uint32_t addr;
int nbanks;
- MemoryRegion containers[4]; /* used for clipping */
- MemoryRegion *ram_memories;
- hwaddr ram_bases[4];
- hwaddr ram_sizes[4];
+ Ppc4xxSdramBank bank[4];
uint32_t besr0;
uint32_t besr1;
uint32_t bear;
@@ -53,7 +50,6 @@ struct ppc4xx_sdram_t {
uint32_t status;
uint32_t rtr;
uint32_t pmit;
- uint32_t bcr[4];
uint32_t tr;
uint32_t ecccfg;
uint32_t eccesr;
@@ -131,26 +127,26 @@ static target_ulong sdram_size(uint32_t bcr)
static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
uint32_t bcr, int enabled)
{
- if (sdram->bcr[i] & 0x00000001) {
+ if (sdram->bank[i].bcr & 0x00000001) {
/* Unmap RAM */
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]),
- sdram_size(sdram->bcr[i]));
+ trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
+ sdram_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
- &sdram->containers[i]);
- memory_region_del_subregion(&sdram->containers[i],
- &sdram->ram_memories[i]);
- object_unparent(OBJECT(&sdram->containers[i]));
+ &sdram->bank[i].container);
+ memory_region_del_subregion(&sdram->bank[i].container,
+ &sdram->bank[i].ram);
+ object_unparent(OBJECT(&sdram->bank[i].container));
}
- sdram->bcr[i] = bcr & 0xFFDEE001;
+ sdram->bank[i].bcr = bcr & 0xFFDEE001;
if (enabled && (bcr & 0x00000001)) {
trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
- memory_region_init(&sdram->containers[i], NULL, "sdram-containers",
+ memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
sdram_size(bcr));
- memory_region_add_subregion(&sdram->containers[i], 0,
- &sdram->ram_memories[i]);
+ memory_region_add_subregion(&sdram->bank[i].container, 0,
+ &sdram->bank[i].ram);
memory_region_add_subregion(get_system_memory(),
sdram_base(bcr),
- &sdram->containers[i]);
+ &sdram->bank[i].container);
}
}
@@ -159,9 +155,9 @@ static void sdram_map_bcr(ppc4xx_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->ram_sizes[i] != 0) {
- sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i],
- sdram->ram_sizes[i]), 1);
+ if (sdram->bank[i].size != 0) {
+ sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
} else {
sdram_set_bcr(sdram, i, 0x00000000, 0);
}
@@ -173,10 +169,10 @@ static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]),
- sdram_size(sdram->bcr[i]));
+ trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
+ sdram_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
- &sdram->ram_memories[i]);
+ &sdram->bank[i].ram);
}
}
@@ -214,16 +210,16 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
ret = sdram->pmit;
break;
case 0x40: /* SDRAM_B0CR */
- ret = sdram->bcr[0];
+ ret = sdram->bank[0].bcr;
break;
case 0x44: /* SDRAM_B1CR */
- ret = sdram->bcr[1];
+ ret = sdram->bank[1].bcr;
break;
case 0x48: /* SDRAM_B2CR */
- ret = sdram->bcr[2];
+ ret = sdram->bank[2].bcr;
break;
case 0x4C: /* SDRAM_B3CR */
- ret = sdram->bcr[3];
+ ret = sdram->bank[3].bcr;
break;
case 0x80: /* SDRAM_TR */
ret = -1; /* ? */
@@ -358,13 +354,16 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
int do_init)
{
ppc4xx_sdram_t *sdram;
+ int i;
sdram = g_new0(ppc4xx_sdram_t, 1);
sdram->irq = irq;
sdram->nbanks = nbanks;
- sdram->ram_memories = ram_memories;
- memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr));
- memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr));
+ for (i = 0; i < nbanks; i++) {
+ sdram->bank[i].ram = ram_memories[i];
+ sdram->bank[i].base = ram_bases[i];
+ sdram->bank[i].size = ram_sizes[i];
+ }
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index a1781afa8e..2af0d60577 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -29,6 +29,14 @@
#include "exec/memory.h"
#include "hw/sysbus.h"
+typedef struct {
+ MemoryRegion ram;
+ MemoryRegion container; /* used for clipping */
+ hwaddr base;
+ hwaddr size;
+ uint32_t bcr;
+} Ppc4xxSdramBank;
+
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
MemoryRegion ram_memories[],
hwaddr ram_bases[], hwaddr ram_sizes[],
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 01/20] ppc440_bamboo: Remove unnecessary memsets BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 02/20] ppc4xx: Introduce Ppc4xxSdramBank struct BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-14 6:57 ` Cédric Le Goater
2022-09-13 19:52 ` [PATCH v3 04/20] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks() BALATON Zoltan
` (17 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
The do_init parameter of ppc4xx_sdram_init() is used to map memory
regions that is normally done by the firmware by programming the SDRAM
controller. This is needed when booting a kernel directly from -kernel
without a firmware. Do this from board code accesing normal SDRAM
controller registers the same way as firmware would do, so we can get
rid of this hack.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
v2: Fix ref405ep boot with -kernel and U-Boot
hw/ppc/ppc405.h | 1 -
hw/ppc/ppc405_boards.c | 12 ++++++++++--
hw/ppc/ppc405_uc.c | 4 +---
hw/ppc/ppc440_bamboo.c | 8 +++++++-
hw/ppc/ppc440_uc.c | 2 --
hw/ppc/ppc4xx_devs.c | 11 +----------
include/hw/ppc/ppc4xx.h | 8 ++++++--
7 files changed, 25 insertions(+), 21 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 1e558c7831..756865621b 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -169,7 +169,6 @@ struct Ppc405SoCState {
/* Public */
MemoryRegion ram_banks[2];
hwaddr ram_bases[2], ram_sizes[2];
- bool do_dram_init;
MemoryRegion *dram_mr;
hwaddr ram_size;
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 083f12b23e..bf02a71c6d 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -274,6 +274,7 @@ static void ppc405_init(MachineState *machine)
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
MemoryRegion *sysmem = get_system_memory();
+ CPUPPCState *env;
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
@@ -288,12 +289,19 @@ static void ppc405_init(MachineState *machine)
machine->ram_size, &error_fatal);
object_property_set_link(OBJECT(&ppc405->soc), "dram",
OBJECT(machine->ram), &error_abort);
- object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
- kernel_filename != NULL, &error_abort);
object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
&error_abort);
qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
+ /* Enable SDRAM memory regions */
+ /* FIXME This shouldn't be needed with firmware but we lack SPD data */
+ env = &ppc405->soc.cpu.env;
+ if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
+ ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
+ error_report("Could not enable memory regions");
+ exit(1);
+ }
+
/* allocate and load BIOS */
if (machine->firmware) {
MemoryRegion *bios = g_new(MemoryRegion, 1);
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 2ca42fdef6..1e02347e57 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1081,8 +1081,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
s->ram_bases[0], s->ram_sizes[0]);
ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->ram_banks, s->ram_bases, s->ram_sizes,
- s->do_dram_init);
+ s->ram_banks, s->ram_bases, s->ram_sizes);
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
@@ -1160,7 +1159,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
- DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 5ec82fa8c2..e3412c4fcd 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -211,7 +211,13 @@ static void bamboo_init(MachineState *machine)
ppc4xx_sdram_init(env,
qdev_get_gpio_in(uicdev, 14),
PPC440EP_SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes, 1);
+ ram_bases, ram_sizes);
+ /* Enable SDRAM memory regions, this should be done by the firmware */
+ if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
+ ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
+ error_report("couldn't enable memory regions");
+ exit(1);
+ }
/* PCI */
dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index db33334e29..6ab0ad7985 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -489,8 +489,6 @@ typedef struct ppc440_sdram_t {
} ppc440_sdram_t;
enum {
- SDRAM0_CFGADDR = 0x10,
- SDRAM0_CFGDATA,
SDRAM_R0BAS = 0x40,
SDRAM_R1BAS,
SDRAM_R2BAS,
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 1226ec4aa9..936d6f77fe 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -56,11 +56,6 @@ struct ppc4xx_sdram_t {
qemu_irq irq;
};
-enum {
- SDRAM0_CFGADDR = 0x010,
- SDRAM0_CFGDATA = 0x011,
-};
-
/*
* XXX: TOFIX: some patches have made this code become inconsistent:
* there are type inconsistencies, mixing hwaddr, target_ulong
@@ -350,8 +345,7 @@ static void sdram_reset(void *opaque)
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion *ram_memories,
hwaddr *ram_bases,
- hwaddr *ram_sizes,
- int do_init)
+ hwaddr *ram_sizes)
{
ppc4xx_sdram_t *sdram;
int i;
@@ -369,9 +363,6 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
sdram, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
sdram, &dcr_read_sdram, &dcr_write_sdram);
- if (do_init) {
- sdram_map_bcr(sdram);
- }
}
/*
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 2af0d60577..a5e6c185af 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -37,6 +37,11 @@ typedef struct {
uint32_t bcr;
} Ppc4xxSdramBank;
+enum {
+ SDRAM0_CFGADDR = 0x010,
+ SDRAM0_CFGDATA = 0x011,
+};
+
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
MemoryRegion ram_memories[],
hwaddr ram_bases[], hwaddr ram_sizes[],
@@ -45,8 +50,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
MemoryRegion ram_memories[],
hwaddr *ram_bases,
- hwaddr *ram_sizes,
- int do_init);
+ hwaddr *ram_sizes);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack
2022-09-13 19:52 ` [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack BALATON Zoltan
@ 2022-09-14 6:57 ` Cédric Le Goater
2022-09-14 11:44 ` BALATON Zoltan
0 siblings, 1 reply; 41+ messages in thread
From: Cédric Le Goater @ 2022-09-14 6:57 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 9/13/22 21:52, BALATON Zoltan wrote:
> The do_init parameter of ppc4xx_sdram_init() is used to map memory
> regions that is normally done by the firmware by programming the SDRAM
> controller. This is needed when booting a kernel directly from -kernel
> without a firmware. Do this from board code accesing normal SDRAM
accessing
> controller registers the same way as firmware would do, so we can get
> rid of this hack.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> v2: Fix ref405ep boot with -kernel and U-Boot
>
> hw/ppc/ppc405.h | 1 -
> hw/ppc/ppc405_boards.c | 12 ++++++++++--
> hw/ppc/ppc405_uc.c | 4 +---
> hw/ppc/ppc440_bamboo.c | 8 +++++++-
> hw/ppc/ppc440_uc.c | 2 --
> hw/ppc/ppc4xx_devs.c | 11 +----------
> include/hw/ppc/ppc4xx.h | 8 ++++++--
> 7 files changed, 25 insertions(+), 21 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 1e558c7831..756865621b 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -169,7 +169,6 @@ struct Ppc405SoCState {
> /* Public */
> MemoryRegion ram_banks[2];
> hwaddr ram_bases[2], ram_sizes[2];
> - bool do_dram_init;
>
> MemoryRegion *dram_mr;
> hwaddr ram_size;
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index 083f12b23e..bf02a71c6d 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -274,6 +274,7 @@ static void ppc405_init(MachineState *machine)
> MachineClass *mc = MACHINE_GET_CLASS(machine);
> const char *kernel_filename = machine->kernel_filename;
> MemoryRegion *sysmem = get_system_memory();
> + CPUPPCState *env;
>
> if (machine->ram_size != mc->default_ram_size) {
> char *sz = size_to_str(mc->default_ram_size);
> @@ -288,12 +289,19 @@ static void ppc405_init(MachineState *machine)
> machine->ram_size, &error_fatal);
> object_property_set_link(OBJECT(&ppc405->soc), "dram",
> OBJECT(machine->ram), &error_abort);
> - object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
> - kernel_filename != NULL, &error_abort);
> object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
> &error_abort);
> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
>
> + /* Enable SDRAM memory regions */
> + /* FIXME This shouldn't be needed with firmware but we lack SPD data */
what do you mean ?
> + env = &ppc405->soc.cpu.env;
> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
I am not in favor of these ppc_drc_write calls and this is still a hack.
The "dram-init" property is a cleaner solution. It takes care of doing the
pre-mapping of RAM banks in the realize routine of the sdram model (when
available).
C.
> + error_report("Could not enable memory regions");
> + exit(1);
> + }
> +
> /* allocate and load BIOS */
> if (machine->firmware) {
> MemoryRegion *bios = g_new(MemoryRegion, 1);
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 2ca42fdef6..1e02347e57 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1081,8 +1081,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> s->ram_bases[0], s->ram_sizes[0]);
>
> ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
> - s->ram_banks, s->ram_bases, s->ram_sizes,
> - s->do_dram_init);
> + s->ram_banks, s->ram_bases, s->ram_sizes);
>
> /* External bus controller */
> if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
> @@ -1160,7 +1159,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> static Property ppc405_soc_properties[] = {
> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
> MemoryRegion *),
> - DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
> DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
> DEFINE_PROP_END_OF_LIST(),
> };
> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
> index 5ec82fa8c2..e3412c4fcd 100644
> --- a/hw/ppc/ppc440_bamboo.c
> +++ b/hw/ppc/ppc440_bamboo.c
> @@ -211,7 +211,13 @@ static void bamboo_init(MachineState *machine)
> ppc4xx_sdram_init(env,
> qdev_get_gpio_in(uicdev, 14),
> PPC440EP_SDRAM_NR_BANKS, ram_memories,
> - ram_bases, ram_sizes, 1);
> + ram_bases, ram_sizes);
> + /* Enable SDRAM memory regions, this should be done by the firmware */
> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
> + error_report("couldn't enable memory regions");
> + exit(1);
> + }
>
> /* PCI */
> dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
> index db33334e29..6ab0ad7985 100644
> --- a/hw/ppc/ppc440_uc.c
> +++ b/hw/ppc/ppc440_uc.c
> @@ -489,8 +489,6 @@ typedef struct ppc440_sdram_t {
> } ppc440_sdram_t;
>
> enum {
> - SDRAM0_CFGADDR = 0x10,
> - SDRAM0_CFGDATA,
> SDRAM_R0BAS = 0x40,
> SDRAM_R1BAS,
> SDRAM_R2BAS,
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index 1226ec4aa9..936d6f77fe 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -56,11 +56,6 @@ struct ppc4xx_sdram_t {
> qemu_irq irq;
> };
>
> -enum {
> - SDRAM0_CFGADDR = 0x010,
> - SDRAM0_CFGDATA = 0x011,
> -};
> -
> /*
> * XXX: TOFIX: some patches have made this code become inconsistent:
> * there are type inconsistencies, mixing hwaddr, target_ulong
> @@ -350,8 +345,7 @@ static void sdram_reset(void *opaque)
> void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
> MemoryRegion *ram_memories,
> hwaddr *ram_bases,
> - hwaddr *ram_sizes,
> - int do_init)
> + hwaddr *ram_sizes)
> {
> ppc4xx_sdram_t *sdram;
> int i;
> @@ -369,9 +363,6 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
> sdram, &dcr_read_sdram, &dcr_write_sdram);
> ppc_dcr_register(env, SDRAM0_CFGDATA,
> sdram, &dcr_read_sdram, &dcr_write_sdram);
> - if (do_init) {
> - sdram_map_bcr(sdram);
> - }
> }
>
> /*
> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
> index 2af0d60577..a5e6c185af 100644
> --- a/include/hw/ppc/ppc4xx.h
> +++ b/include/hw/ppc/ppc4xx.h
> @@ -37,6 +37,11 @@ typedef struct {
> uint32_t bcr;
> } Ppc4xxSdramBank;
>
> +enum {
> + SDRAM0_CFGADDR = 0x010,
> + SDRAM0_CFGDATA = 0x011,
> +};
> +
> void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
> MemoryRegion ram_memories[],
> hwaddr ram_bases[], hwaddr ram_sizes[],
> @@ -45,8 +50,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
> void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
> MemoryRegion ram_memories[],
> hwaddr *ram_bases,
> - hwaddr *ram_sizes,
> - int do_init);
> + hwaddr *ram_sizes);
>
> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack
2022-09-14 6:57 ` Cédric Le Goater
@ 2022-09-14 11:44 ` BALATON Zoltan
2022-09-14 13:50 ` Cédric Le Goater
0 siblings, 1 reply; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-14 11:44 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 8768 bytes --]
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
> On 9/13/22 21:52, BALATON Zoltan wrote:
>> The do_init parameter of ppc4xx_sdram_init() is used to map memory
>> regions that is normally done by the firmware by programming the SDRAM
>> controller. This is needed when booting a kernel directly from -kernel
>> without a firmware. Do this from board code accesing normal SDRAM
>
> accessing
Fixed, also two ofhers in another patch you haven't noticed.
>> controller registers the same way as firmware would do, so we can get
>> rid of this hack.
>>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> v2: Fix ref405ep boot with -kernel and U-Boot
>>
>> hw/ppc/ppc405.h | 1 -
>> hw/ppc/ppc405_boards.c | 12 ++++++++++--
>> hw/ppc/ppc405_uc.c | 4 +---
>> hw/ppc/ppc440_bamboo.c | 8 +++++++-
>> hw/ppc/ppc440_uc.c | 2 --
>> hw/ppc/ppc4xx_devs.c | 11 +----------
>> include/hw/ppc/ppc4xx.h | 8 ++++++--
>> 7 files changed, 25 insertions(+), 21 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>> index 1e558c7831..756865621b 100644
>> --- a/hw/ppc/ppc405.h
>> +++ b/hw/ppc/ppc405.h
>> @@ -169,7 +169,6 @@ struct Ppc405SoCState {
>> /* Public */
>> MemoryRegion ram_banks[2];
>> hwaddr ram_bases[2], ram_sizes[2];
>> - bool do_dram_init;
>> MemoryRegion *dram_mr;
>> hwaddr ram_size;
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index 083f12b23e..bf02a71c6d 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -274,6 +274,7 @@ static void ppc405_init(MachineState *machine)
>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>> const char *kernel_filename = machine->kernel_filename;
>> MemoryRegion *sysmem = get_system_memory();
>> + CPUPPCState *env;
>> if (machine->ram_size != mc->default_ram_size) {
>> char *sz = size_to_str(mc->default_ram_size);
>> @@ -288,12 +289,19 @@ static void ppc405_init(MachineState *machine)
>> machine->ram_size, &error_fatal);
>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>> OBJECT(machine->ram), &error_abort);
>> - object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>> - kernel_filename != NULL, &error_abort);
>> object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
>> &error_abort);
>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
>> + /* Enable SDRAM memory regions */
>> + /* FIXME This shouldn't be needed with firmware but we lack SPD data
>> */
>
> what do you mean ?
U-Boot detects the available RAM by reading the SPD info of the RAM
modules but that probably also needs i2c emulation. See sam460ex.
>> + env = &ppc405->soc.cpu.env;
>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>
>
> I am not in favor of these ppc_drc_write calls and this is still a hack.
It's not. Normally this is done by firmware to enable memory controller
but the board code has to do it if not using firmware (e.g. booting with
-kernel) the same way it provides bootinfo or device tree mods the
firmware would normally do or in this case maybe the emulation is
incomplete so the part of firmware that configures the SDRAM controller
does not run.
> The "dram-init" property is a cleaner solution. It takes care of doing the
> pre-mapping of RAM banks in the realize routine of the sdram model (when
> available).
I disagree, the hardware does not have such feature, it proviesd DCRs as
the way to configure it. Adding a special property for it deviates from
hardware and clutters qtree. Doing it like this patch is cleaner IMO.
Regards,
BALATON Zoltan
>
> C.
>
>> + error_report("Could not enable memory regions");
>> + exit(1);
>> + }
>> +
>> /* allocate and load BIOS */
>> if (machine->firmware) {
>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>> index 2ca42fdef6..1e02347e57 100644
>> --- a/hw/ppc/ppc405_uc.c
>> +++ b/hw/ppc/ppc405_uc.c
>> @@ -1081,8 +1081,7 @@ static void ppc405_soc_realize(DeviceState *dev,
>> Error **errp)
>> s->ram_bases[0], s->ram_sizes[0]);
>> ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
>> - s->ram_banks, s->ram_bases, s->ram_sizes,
>> - s->do_dram_init);
>> + s->ram_banks, s->ram_bases, s->ram_sizes);
>> /* External bus controller */
>> if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
>> @@ -1160,7 +1159,6 @@ static void ppc405_soc_realize(DeviceState *dev,
>> Error **errp)
>> static Property ppc405_soc_properties[] = {
>> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
>> MemoryRegion *),
>> - DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
>> DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
>> DEFINE_PROP_END_OF_LIST(),
>> };
>> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
>> index 5ec82fa8c2..e3412c4fcd 100644
>> --- a/hw/ppc/ppc440_bamboo.c
>> +++ b/hw/ppc/ppc440_bamboo.c
>> @@ -211,7 +211,13 @@ static void bamboo_init(MachineState *machine)
>> ppc4xx_sdram_init(env,
>> qdev_get_gpio_in(uicdev, 14),
>> PPC440EP_SDRAM_NR_BANKS, ram_memories,
>> - ram_bases, ram_sizes, 1);
>> + ram_bases, ram_sizes);
>> + /* Enable SDRAM memory regions, this should be done by the firmware */
>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>> + error_report("couldn't enable memory regions");
>> + exit(1);
>> + }
>> /* PCI */
>> dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
>> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
>> index db33334e29..6ab0ad7985 100644
>> --- a/hw/ppc/ppc440_uc.c
>> +++ b/hw/ppc/ppc440_uc.c
>> @@ -489,8 +489,6 @@ typedef struct ppc440_sdram_t {
>> } ppc440_sdram_t;
>> enum {
>> - SDRAM0_CFGADDR = 0x10,
>> - SDRAM0_CFGDATA,
>> SDRAM_R0BAS = 0x40,
>> SDRAM_R1BAS,
>> SDRAM_R2BAS,
>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>> index 1226ec4aa9..936d6f77fe 100644
>> --- a/hw/ppc/ppc4xx_devs.c
>> +++ b/hw/ppc/ppc4xx_devs.c
>> @@ -56,11 +56,6 @@ struct ppc4xx_sdram_t {
>> qemu_irq irq;
>> };
>> -enum {
>> - SDRAM0_CFGADDR = 0x010,
>> - SDRAM0_CFGDATA = 0x011,
>> -};
>> -
>> /*
>> * XXX: TOFIX: some patches have made this code become inconsistent:
>> * there are type inconsistencies, mixing hwaddr, target_ulong
>> @@ -350,8 +345,7 @@ static void sdram_reset(void *opaque)
>> void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
>> MemoryRegion *ram_memories,
>> hwaddr *ram_bases,
>> - hwaddr *ram_sizes,
>> - int do_init)
>> + hwaddr *ram_sizes)
>> {
>> ppc4xx_sdram_t *sdram;
>> int i;
>> @@ -369,9 +363,6 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq,
>> int nbanks,
>> sdram, &dcr_read_sdram, &dcr_write_sdram);
>> ppc_dcr_register(env, SDRAM0_CFGDATA,
>> sdram, &dcr_read_sdram, &dcr_write_sdram);
>> - if (do_init) {
>> - sdram_map_bcr(sdram);
>> - }
>> }
>> /*
>> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
>> index 2af0d60577..a5e6c185af 100644
>> --- a/include/hw/ppc/ppc4xx.h
>> +++ b/include/hw/ppc/ppc4xx.h
>> @@ -37,6 +37,11 @@ typedef struct {
>> uint32_t bcr;
>> } Ppc4xxSdramBank;
>> +enum {
>> + SDRAM0_CFGADDR = 0x010,
>> + SDRAM0_CFGDATA = 0x011,
>> +};
>> +
>> void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
>> MemoryRegion ram_memories[],
>> hwaddr ram_bases[], hwaddr ram_sizes[],
>> @@ -45,8 +50,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
>> void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
>> MemoryRegion ram_memories[],
>> hwaddr *ram_bases,
>> - hwaddr *ram_sizes,
>> - int do_init);
>> + hwaddr *ram_sizes);
>> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>>
>
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack
2022-09-14 11:44 ` BALATON Zoltan
@ 2022-09-14 13:50 ` Cédric Le Goater
2022-09-14 18:25 ` BALATON Zoltan
0 siblings, 1 reply; 41+ messages in thread
From: Cédric Le Goater @ 2022-09-14 13:50 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
On 9/14/22 13:44, BALATON Zoltan wrote:
> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>> On 9/13/22 21:52, BALATON Zoltan wrote:
>>> The do_init parameter of ppc4xx_sdram_init() is used to map memory
>>> regions that is normally done by the firmware by programming the SDRAM
>>> controller. This is needed when booting a kernel directly from -kernel
>>> without a firmware. Do this from board code accesing normal SDRAM
>>
>> accessing
>
> Fixed, also two ofhers in another patch you haven't noticed.
>
>>> controller registers the same way as firmware would do, so we can get
>>> rid of this hack.
>>>
>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>> ---
>>> v2: Fix ref405ep boot with -kernel and U-Boot
>>>
>>> hw/ppc/ppc405.h | 1 -
>>> hw/ppc/ppc405_boards.c | 12 ++++++++++--
>>> hw/ppc/ppc405_uc.c | 4 +---
>>> hw/ppc/ppc440_bamboo.c | 8 +++++++-
>>> hw/ppc/ppc440_uc.c | 2 --
>>> hw/ppc/ppc4xx_devs.c | 11 +----------
>>> include/hw/ppc/ppc4xx.h | 8 ++++++--
>>> 7 files changed, 25 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>> index 1e558c7831..756865621b 100644
>>> --- a/hw/ppc/ppc405.h
>>> +++ b/hw/ppc/ppc405.h
>>> @@ -169,7 +169,6 @@ struct Ppc405SoCState {
>>> /* Public */
>>> MemoryRegion ram_banks[2];
>>> hwaddr ram_bases[2], ram_sizes[2];
>>> - bool do_dram_init;
>>> MemoryRegion *dram_mr;
>>> hwaddr ram_size;
>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>> index 083f12b23e..bf02a71c6d 100644
>>> --- a/hw/ppc/ppc405_boards.c
>>> +++ b/hw/ppc/ppc405_boards.c
>>> @@ -274,6 +274,7 @@ static void ppc405_init(MachineState *machine)
>>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>>> const char *kernel_filename = machine->kernel_filename;
>>> MemoryRegion *sysmem = get_system_memory();
>>> + CPUPPCState *env;
>>> if (machine->ram_size != mc->default_ram_size) {
>>> char *sz = size_to_str(mc->default_ram_size);
>>> @@ -288,12 +289,19 @@ static void ppc405_init(MachineState *machine)
>>> machine->ram_size, &error_fatal);
>>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>>> OBJECT(machine->ram), &error_abort);
>>> - object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>>> - kernel_filename != NULL, &error_abort);
>>> object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
>>> &error_abort);
>>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
>>> + /* Enable SDRAM memory regions */
>>> + /* FIXME This shouldn't be needed with firmware but we lack SPD data */
>>
>> what do you mean ?
>
> U-Boot detects the available RAM by reading the SPD info of the RAM modules but that probably also needs i2c emulation. See sam460ex.
>
>>> + env = &ppc405->soc.cpu.env;
>>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>>
>>
>> I am not in favor of these ppc_drc_write calls and this is still a hack.
>
> It's not. Normally this is done by firmware to enable memory controller but the board code has to do it if not using firmware (e.g. booting with -kernel) the same way it provides bootinfo or device tree mods the firmware would normally do or in this case maybe the emulation is incomplete so the part of firmware that configures the SDRAM controller does not run.
Exactly, and what the above proposal does is mimicking execution of CPU
instructions before the CPU is even fully initiated. Reset has not been
called at that stage.
>
>> The "dram-init" property is a cleaner solution. It takes care of doing the
>> pre-mapping of RAM banks in the realize routine of the sdram model (when
>> available).
>
> I disagree, the hardware does not have such feature, it proviesd DCRs as the way to configure it. Adding a special property for it deviates from hardware and clutters qtree.
In this machine, running QEMU with -kernel deviates from HW. That's
the whole purpose of this option. It assumes that the SDRAM device
is pre-initialized (and much more should be done) by the QEMU machine
and the simplest way to acheive this goal is to inform the SDRAM model
to take care of the pre-initialization.
Another way would be to change the default reset values of the SDRAM
registers (in the realize method using some property) and perform
some actions (mapping the banks) in the reset handler of the SDRAM
device model. That would be a deferred initialization but a property
is still needed to change the default behavior of the SDRAM model.
Anyhow, this should be isolated under the SDRAM device model and
not in the machine init by using the CPU state. That's clearly ugly.
Thanks,
C.
> Doing it like this patch is cleaner IMO.
>
> Regards,
> BALATON Zoltan
>
>>
>> C.
>>
>>> + error_report("Could not enable memory regions");
>>> + exit(1);
>>> + }
>>> +
>>> /* allocate and load BIOS */
>>> if (machine->firmware) {
>>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>>> index 2ca42fdef6..1e02347e57 100644
>>> --- a/hw/ppc/ppc405_uc.c
>>> +++ b/hw/ppc/ppc405_uc.c
>>> @@ -1081,8 +1081,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>>> s->ram_bases[0], s->ram_sizes[0]);
>>> ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
>>> - s->ram_banks, s->ram_bases, s->ram_sizes,
>>> - s->do_dram_init);
>>> + s->ram_banks, s->ram_bases, s->ram_sizes);
>>> /* External bus controller */
>>> if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
>>> @@ -1160,7 +1159,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>>> static Property ppc405_soc_properties[] = {
>>> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
>>> MemoryRegion *),
>>> - DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
>>> DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
>>> DEFINE_PROP_END_OF_LIST(),
>>> };
>>> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
>>> index 5ec82fa8c2..e3412c4fcd 100644
>>> --- a/hw/ppc/ppc440_bamboo.c
>>> +++ b/hw/ppc/ppc440_bamboo.c
>>> @@ -211,7 +211,13 @@ static void bamboo_init(MachineState *machine)
>>> ppc4xx_sdram_init(env,
>>> qdev_get_gpio_in(uicdev, 14),
>>> PPC440EP_SDRAM_NR_BANKS, ram_memories,
>>> - ram_bases, ram_sizes, 1);
>>> + ram_bases, ram_sizes);
>>> + /* Enable SDRAM memory regions, this should be done by the firmware */
>>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>>> + error_report("couldn't enable memory regions");
>>> + exit(1);
>>> + }
>>> /* PCI */
>>> dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
>>> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
>>> index db33334e29..6ab0ad7985 100644
>>> --- a/hw/ppc/ppc440_uc.c
>>> +++ b/hw/ppc/ppc440_uc.c
>>> @@ -489,8 +489,6 @@ typedef struct ppc440_sdram_t {
>>> } ppc440_sdram_t;
>>> enum {
>>> - SDRAM0_CFGADDR = 0x10,
>>> - SDRAM0_CFGDATA,
>>> SDRAM_R0BAS = 0x40,
>>> SDRAM_R1BAS,
>>> SDRAM_R2BAS,
>>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>>> index 1226ec4aa9..936d6f77fe 100644
>>> --- a/hw/ppc/ppc4xx_devs.c
>>> +++ b/hw/ppc/ppc4xx_devs.c
>>> @@ -56,11 +56,6 @@ struct ppc4xx_sdram_t {
>>> qemu_irq irq;
>>> };
>>> -enum {
>>> - SDRAM0_CFGADDR = 0x010,
>>> - SDRAM0_CFGDATA = 0x011,
>>> -};
>>> -
>>> /*
>>> * XXX: TOFIX: some patches have made this code become inconsistent:
>>> * there are type inconsistencies, mixing hwaddr, target_ulong
>>> @@ -350,8 +345,7 @@ static void sdram_reset(void *opaque)
>>> void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
>>> MemoryRegion *ram_memories,
>>> hwaddr *ram_bases,
>>> - hwaddr *ram_sizes,
>>> - int do_init)
>>> + hwaddr *ram_sizes)
>>> {
>>> ppc4xx_sdram_t *sdram;
>>> int i;
>>> @@ -369,9 +363,6 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
>>> sdram, &dcr_read_sdram, &dcr_write_sdram);
>>> ppc_dcr_register(env, SDRAM0_CFGDATA,
>>> sdram, &dcr_read_sdram, &dcr_write_sdram);
>>> - if (do_init) {
>>> - sdram_map_bcr(sdram);
>>> - }
>>> }
>>> /*
>>> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
>>> index 2af0d60577..a5e6c185af 100644
>>> --- a/include/hw/ppc/ppc4xx.h
>>> +++ b/include/hw/ppc/ppc4xx.h
>>> @@ -37,6 +37,11 @@ typedef struct {
>>> uint32_t bcr;
>>> } Ppc4xxSdramBank;
>>> +enum {
>>> + SDRAM0_CFGADDR = 0x010,
>>> + SDRAM0_CFGDATA = 0x011,
>>> +};
>>> +
>>> void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
>>> MemoryRegion ram_memories[],
>>> hwaddr ram_bases[], hwaddr ram_sizes[],
>>> @@ -45,8 +50,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
>>> void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
>>> MemoryRegion ram_memories[],
>>> hwaddr *ram_bases,
>>> - hwaddr *ram_sizes,
>>> - int do_init);
>>> + hwaddr *ram_sizes);
>>> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>>>
>>
>>
>>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack
2022-09-14 13:50 ` Cédric Le Goater
@ 2022-09-14 18:25 ` BALATON Zoltan
2022-09-14 18:32 ` BALATON Zoltan
2022-09-18 7:34 ` Cédric Le Goater
0 siblings, 2 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-14 18:25 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 13070 bytes --]
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
> On 9/14/22 13:44, BALATON Zoltan wrote:
>> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>>> On 9/13/22 21:52, BALATON Zoltan wrote:
>>>> The do_init parameter of ppc4xx_sdram_init() is used to map memory
>>>> regions that is normally done by the firmware by programming the SDRAM
>>>> controller. This is needed when booting a kernel directly from -kernel
>>>> without a firmware. Do this from board code accesing normal SDRAM
>>>
>>> accessing
>>
>> Fixed, also two ofhers in another patch you haven't noticed.
>>
>>>> controller registers the same way as firmware would do, so we can get
>>>> rid of this hack.
>>>>
>>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>>> ---
>>>> v2: Fix ref405ep boot with -kernel and U-Boot
>>>>
>>>> hw/ppc/ppc405.h | 1 -
>>>> hw/ppc/ppc405_boards.c | 12 ++++++++++--
>>>> hw/ppc/ppc405_uc.c | 4 +---
>>>> hw/ppc/ppc440_bamboo.c | 8 +++++++-
>>>> hw/ppc/ppc440_uc.c | 2 --
>>>> hw/ppc/ppc4xx_devs.c | 11 +----------
>>>> include/hw/ppc/ppc4xx.h | 8 ++++++--
>>>> 7 files changed, 25 insertions(+), 21 deletions(-)
>>>>
>>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>>> index 1e558c7831..756865621b 100644
>>>> --- a/hw/ppc/ppc405.h
>>>> +++ b/hw/ppc/ppc405.h
>>>> @@ -169,7 +169,6 @@ struct Ppc405SoCState {
>>>> /* Public */
>>>> MemoryRegion ram_banks[2];
>>>> hwaddr ram_bases[2], ram_sizes[2];
>>>> - bool do_dram_init;
>>>> MemoryRegion *dram_mr;
>>>> hwaddr ram_size;
>>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>>> index 083f12b23e..bf02a71c6d 100644
>>>> --- a/hw/ppc/ppc405_boards.c
>>>> +++ b/hw/ppc/ppc405_boards.c
>>>> @@ -274,6 +274,7 @@ static void ppc405_init(MachineState *machine)
>>>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>>>> const char *kernel_filename = machine->kernel_filename;
>>>> MemoryRegion *sysmem = get_system_memory();
>>>> + CPUPPCState *env;
>>>> if (machine->ram_size != mc->default_ram_size) {
>>>> char *sz = size_to_str(mc->default_ram_size);
>>>> @@ -288,12 +289,19 @@ static void ppc405_init(MachineState *machine)
>>>> machine->ram_size, &error_fatal);
>>>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>>>> OBJECT(machine->ram), &error_abort);
>>>> - object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>>>> - kernel_filename != NULL, &error_abort);
>>>> object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
>>>> &error_abort);
>>>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
>>>> + /* Enable SDRAM memory regions */
>>>> + /* FIXME This shouldn't be needed with firmware but we lack SPD data
>>>> */
>>>
>>> what do you mean ?
>>
>> U-Boot detects the available RAM by reading the SPD info of the RAM modules
>> but that probably also needs i2c emulation. See sam460ex.
>>
>>>> + env = &ppc405->soc.cpu.env;
>>>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>>>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>>>
>>>
>>> I am not in favor of these ppc_drc_write calls and this is still a hack.
>>
>> It's not. Normally this is done by firmware to enable memory controller but
>> the board code has to do it if not using firmware (e.g. booting with
>> -kernel) the same way it provides bootinfo or device tree mods the firmware
>> would normally do or in this case maybe the emulation is incomplete so the
>> part of firmware that configures the SDRAM controller does not run.
>
> Exactly, and what the above proposal does is mimicking execution of CPU
> instructions before the CPU is even fully initiated. Reset has not been
> called at that stage.
I don't get this. We're not calling any CPU instructions, ppc_dcr_write
just calls the write callback the device has registered for the dcr so it
just does the same as the hack did at the end just doing it the same way
the firmware should do.
>>> The "dram-init" property is a cleaner solution. It takes care of doing the
>>> pre-mapping of RAM banks in the realize routine of the sdram model (when
>>> available).
>>
>> I disagree, the hardware does not have such feature, it proviesd DCRs as
>> the way to configure it. Adding a special property for it deviates from
>> hardware and clutters qtree.
>
>
> In this machine, running QEMU with -kernel deviates from HW. That's
In all machines booting with -kernel likely deviates and all machines
probably have additinal code in this case to do some things normally done
by the firmware. Look at pegasos2_machine_reset() for example. All that is
not needed when we boot with firmware as then the firmware will do all
that and provide the device tree, etc. bur we need to do these when
booting without firmware. In thes case QEMU also emulates the firmware
and has to do thinigs like enabling the memory controller.
> the whole purpose of this option. It assumes that the SDRAM device
> is pre-initialized (and much more should be done) by the QEMU machine
> and the simplest way to acheive this goal is to inform the SDRAM model
> to take care of the pre-initialization.
In my opinion the SDRAM controller model should model the hardware and if
the board uses it differently then it should take care of that and not
change the model.
> Another way would be to change the default reset values of the SDRAM
> registers (in the realize method using some property) and perform
> some actions (mapping the banks) in the reset handler of the SDRAM
> device model. That would be a deferred initialization but a property
> is still needed to change the default behavior of the SDRAM model.
>
> Anyhow, this should be isolated under the SDRAM device model and
> not in the machine init by using the CPU state. That's clearly ugly.
Why? You already have the ppc405_set_bootinfo and all it's stuff in the
ppc405 board which is also only needed without firmware. If you're opposed
to the few lines enabling the memory controller being in ppc405_init I
could put it in a function either in ppc405_boards.c or if you think this
should be in ppc4xx_sdrem.c then we can export that function via
include/hw/ppc/ppc4xx.h and call that from boards but I don't want to add
hacks and a property for this in the device model becuase I'm not
convinced it belongs there. If the hardware would have such an option then
modeling that in is valid but if it's done by the firmare on the real
hardware then either use the firmware or do it in board code which is
then emulating the firmware too.
Regards,
BALATON Zoltan
>
> Thanks,
>
> C.
>
>
>
>
>
>> Doing it like this patch is cleaner IMO.
>>
>> Regards,
>> BALATON Zoltan
>>
>>>
>>> C.
>>>
>>>> + error_report("Could not enable memory regions");
>>>> + exit(1);
>>>> + }
>>>> +
>>>> /* allocate and load BIOS */
>>>> if (machine->firmware) {
>>>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>>>> index 2ca42fdef6..1e02347e57 100644
>>>> --- a/hw/ppc/ppc405_uc.c
>>>> +++ b/hw/ppc/ppc405_uc.c
>>>> @@ -1081,8 +1081,7 @@ static void ppc405_soc_realize(DeviceState *dev,
>>>> Error **errp)
>>>> s->ram_bases[0], s->ram_sizes[0]);
>>>> ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
>>>> - s->ram_banks, s->ram_bases, s->ram_sizes,
>>>> - s->do_dram_init);
>>>> + s->ram_banks, s->ram_bases, s->ram_sizes);
>>>> /* External bus controller */
>>>> if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp))
>>>> {
>>>> @@ -1160,7 +1159,6 @@ static void ppc405_soc_realize(DeviceState *dev,
>>>> Error **errp)
>>>> static Property ppc405_soc_properties[] = {
>>>> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr,
>>>> TYPE_MEMORY_REGION,
>>>> MemoryRegion *),
>>>> - DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
>>>> DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
>>>> DEFINE_PROP_END_OF_LIST(),
>>>> };
>>>> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
>>>> index 5ec82fa8c2..e3412c4fcd 100644
>>>> --- a/hw/ppc/ppc440_bamboo.c
>>>> +++ b/hw/ppc/ppc440_bamboo.c
>>>> @@ -211,7 +211,13 @@ static void bamboo_init(MachineState *machine)
>>>> ppc4xx_sdram_init(env,
>>>> qdev_get_gpio_in(uicdev, 14),
>>>> PPC440EP_SDRAM_NR_BANKS, ram_memories,
>>>> - ram_bases, ram_sizes, 1);
>>>> + ram_bases, ram_sizes);
>>>> + /* Enable SDRAM memory regions, this should be done by the firmware
>>>> */
>>>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>>>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>>>> + error_report("couldn't enable memory regions");
>>>> + exit(1);
>>>> + }
>>>> /* PCI */
>>>> dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
>>>> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
>>>> index db33334e29..6ab0ad7985 100644
>>>> --- a/hw/ppc/ppc440_uc.c
>>>> +++ b/hw/ppc/ppc440_uc.c
>>>> @@ -489,8 +489,6 @@ typedef struct ppc440_sdram_t {
>>>> } ppc440_sdram_t;
>>>> enum {
>>>> - SDRAM0_CFGADDR = 0x10,
>>>> - SDRAM0_CFGDATA,
>>>> SDRAM_R0BAS = 0x40,
>>>> SDRAM_R1BAS,
>>>> SDRAM_R2BAS,
>>>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>>>> index 1226ec4aa9..936d6f77fe 100644
>>>> --- a/hw/ppc/ppc4xx_devs.c
>>>> +++ b/hw/ppc/ppc4xx_devs.c
>>>> @@ -56,11 +56,6 @@ struct ppc4xx_sdram_t {
>>>> qemu_irq irq;
>>>> };
>>>> -enum {
>>>> - SDRAM0_CFGADDR = 0x010,
>>>> - SDRAM0_CFGDATA = 0x011,
>>>> -};
>>>> -
>>>> /*
>>>> * XXX: TOFIX: some patches have made this code become inconsistent:
>>>> * there are type inconsistencies, mixing hwaddr, target_ulong
>>>> @@ -350,8 +345,7 @@ static void sdram_reset(void *opaque)
>>>> void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
>>>> MemoryRegion *ram_memories,
>>>> hwaddr *ram_bases,
>>>> - hwaddr *ram_sizes,
>>>> - int do_init)
>>>> + hwaddr *ram_sizes)
>>>> {
>>>> ppc4xx_sdram_t *sdram;
>>>> int i;
>>>> @@ -369,9 +363,6 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq
>>>> irq, int nbanks,
>>>> sdram, &dcr_read_sdram, &dcr_write_sdram);
>>>> ppc_dcr_register(env, SDRAM0_CFGDATA,
>>>> sdram, &dcr_read_sdram, &dcr_write_sdram);
>>>> - if (do_init) {
>>>> - sdram_map_bcr(sdram);
>>>> - }
>>>> }
>>>> /*
>>>> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
>>>> index 2af0d60577..a5e6c185af 100644
>>>> --- a/include/hw/ppc/ppc4xx.h
>>>> +++ b/include/hw/ppc/ppc4xx.h
>>>> @@ -37,6 +37,11 @@ typedef struct {
>>>> uint32_t bcr;
>>>> } Ppc4xxSdramBank;
>>>> +enum {
>>>> + SDRAM0_CFGADDR = 0x010,
>>>> + SDRAM0_CFGDATA = 0x011,
>>>> +};
>>>> +
>>>> void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
>>>> MemoryRegion ram_memories[],
>>>> hwaddr ram_bases[], hwaddr ram_sizes[],
>>>> @@ -45,8 +50,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int
>>>> nr_banks,
>>>> void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
>>>> MemoryRegion ram_memories[],
>>>> hwaddr *ram_bases,
>>>> - hwaddr *ram_sizes,
>>>> - int do_init);
>>>> + hwaddr *ram_sizes);
>>>> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>>>>
>>>
>>>
>>>
>
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack
2022-09-14 18:25 ` BALATON Zoltan
@ 2022-09-14 18:32 ` BALATON Zoltan
2022-09-18 7:34 ` Cédric Le Goater
2022-09-18 7:34 ` Cédric Le Goater
1 sibling, 1 reply; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-14 18:32 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 14181 bytes --]
On Wed, 14 Sep 2022, BALATON Zoltan wrote:
> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>> On 9/14/22 13:44, BALATON Zoltan wrote:
>>> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>>>> On 9/13/22 21:52, BALATON Zoltan wrote:
>>>>> The do_init parameter of ppc4xx_sdram_init() is used to map memory
>>>>> regions that is normally done by the firmware by programming the SDRAM
>>>>> controller. This is needed when booting a kernel directly from -kernel
>>>>> without a firmware. Do this from board code accesing normal SDRAM
>>>>
>>>> accessing
>>>
>>> Fixed, also two ofhers in another patch you haven't noticed.
>>>
>>>>> controller registers the same way as firmware would do, so we can get
>>>>> rid of this hack.
>>>>>
>>>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>>>> ---
>>>>> v2: Fix ref405ep boot with -kernel and U-Boot
>>>>>
>>>>> hw/ppc/ppc405.h | 1 -
>>>>> hw/ppc/ppc405_boards.c | 12 ++++++++++--
>>>>> hw/ppc/ppc405_uc.c | 4 +---
>>>>> hw/ppc/ppc440_bamboo.c | 8 +++++++-
>>>>> hw/ppc/ppc440_uc.c | 2 --
>>>>> hw/ppc/ppc4xx_devs.c | 11 +----------
>>>>> include/hw/ppc/ppc4xx.h | 8 ++++++--
>>>>> 7 files changed, 25 insertions(+), 21 deletions(-)
>>>>>
>>>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>>>> index 1e558c7831..756865621b 100644
>>>>> --- a/hw/ppc/ppc405.h
>>>>> +++ b/hw/ppc/ppc405.h
>>>>> @@ -169,7 +169,6 @@ struct Ppc405SoCState {
>>>>> /* Public */
>>>>> MemoryRegion ram_banks[2];
>>>>> hwaddr ram_bases[2], ram_sizes[2];
>>>>> - bool do_dram_init;
>>>>> MemoryRegion *dram_mr;
>>>>> hwaddr ram_size;
>>>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>>>> index 083f12b23e..bf02a71c6d 100644
>>>>> --- a/hw/ppc/ppc405_boards.c
>>>>> +++ b/hw/ppc/ppc405_boards.c
>>>>> @@ -274,6 +274,7 @@ static void ppc405_init(MachineState *machine)
>>>>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>>>>> const char *kernel_filename = machine->kernel_filename;
>>>>> MemoryRegion *sysmem = get_system_memory();
>>>>> + CPUPPCState *env;
>>>>> if (machine->ram_size != mc->default_ram_size) {
>>>>> char *sz = size_to_str(mc->default_ram_size);
>>>>> @@ -288,12 +289,19 @@ static void ppc405_init(MachineState *machine)
>>>>> machine->ram_size, &error_fatal);
>>>>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>>>>> OBJECT(machine->ram), &error_abort);
>>>>> - object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>>>>> - kernel_filename != NULL, &error_abort);
>>>>> object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk",
>>>>> 33333333,
>>>>> &error_abort);
>>>>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
>>>>> + /* Enable SDRAM memory regions */
>>>>> + /* FIXME This shouldn't be needed with firmware but we lack SPD
>>>>> data */
>>>>
>>>> what do you mean ?
>>>
>>> U-Boot detects the available RAM by reading the SPD info of the RAM
>>> modules but that probably also needs i2c emulation. See sam460ex.
>>>
>>>>> + env = &ppc405->soc.cpu.env;
>>>>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>>>>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>>>>
>>>>
>>>> I am not in favor of these ppc_drc_write calls and this is still a hack.
>>>
>>> It's not. Normally this is done by firmware to enable memory controller
>>> but the board code has to do it if not using firmware (e.g. booting with
>>> -kernel) the same way it provides bootinfo or device tree mods the
>>> firmware would normally do or in this case maybe the emulation is
>>> incomplete so the part of firmware that configures the SDRAM controller
>>> does not run.
>>
>> Exactly, and what the above proposal does is mimicking execution of CPU
>> instructions before the CPU is even fully initiated. Reset has not been
>> called at that stage.
>
> I don't get this. We're not calling any CPU instructions, ppc_dcr_write just
> calls the write callback the device has registered for the dcr so it just
> does the same as the hack did at the end just doing it the same way the
> firmware should do.
>
>>>> The "dram-init" property is a cleaner solution. It takes care of doing
>>>> the
>>>> pre-mapping of RAM banks in the realize routine of the sdram model (when
>>>> available).
>>>
>>> I disagree, the hardware does not have such feature, it proviesd DCRs as
>>> the way to configure it. Adding a special property for it deviates from
>>> hardware and clutters qtree.
>>
>>
>> In this machine, running QEMU with -kernel deviates from HW. That's
>
> In all machines booting with -kernel likely deviates and all machines
> probably have additinal code in this case to do some things normally done by
> the firmware. Look at pegasos2_machine_reset() for example. All that is not
> needed when we boot with firmware as then the firmware will do all that and
> provide the device tree, etc. bur we need to do these when booting without
> firmware. In thes case QEMU also emulates the firmware and has to do thinigs
> like enabling the memory controller.
>
>> the whole purpose of this option. It assumes that the SDRAM device
>> is pre-initialized (and much more should be done) by the QEMU machine
>> and the simplest way to acheive this goal is to inform the SDRAM model
>> to take care of the pre-initialization.
>
> In my opinion the SDRAM controller model should model the hardware and if the
> board uses it differently then it should take care of that and not change the
> model.
>
>> Another way would be to change the default reset values of the SDRAM
>> registers (in the realize method using some property) and perform
>> some actions (mapping the banks) in the reset handler of the SDRAM
>> device model. That would be a deferred initialization but a property
>> is still needed to change the default behavior of the SDRAM model.
>>
>> Anyhow, this should be isolated under the SDRAM device model and
>> not in the machine init by using the CPU state. That's clearly ugly.
Additionally, if you don't like the FIXME comment, it's there because this
would really belong at the beginning of boot_from_kernel() function before
that calls ppc405_set_bootinfo which is called when booting without
firmware but I left it where it was in init for now because you menfioned
that firmware boot was also broken when I had it at the end of
boot_from_kernel so I suspect the board is not providing the SPD data so
the firmware cannot detect the RAM and this why it's not enabling the
SDRAM itself (or maybe that part is even compiled out because of that) but
then it's a limitation of the board emulation and not the SDRAM controller
so it should be handled in the board code.
Regards,
BALATON Zoltan
> Why? You already have the ppc405_set_bootinfo and all it's stuff in the
> ppc405 board which is also only needed without firmware. If you're opposed to
> the few lines enabling the memory controller being in ppc405_init I could put
> it in a function either in ppc405_boards.c or if you think this should be in
> ppc4xx_sdrem.c then we can export that function via include/hw/ppc/ppc4xx.h
> and call that from boards but I don't want to add hacks and a property for
> this in the device model becuase I'm not convinced it belongs there. If the
> hardware would have such an option then modeling that in is valid but if it's
> done by the firmare on the real hardware then either use the firmware or do
> it in board code which is then emulating the firmware too.
>
> Regards,
> BALATON Zoltan
>
>>
>> Thanks,
>>
>> C.
>>
>>
>>
>>
>>
>>> Doing it like this patch is cleaner IMO.
>>>
>>> Regards,
>>> BALATON Zoltan
>>>
>>>>
>>>> C.
>>>>
>>>>> + error_report("Could not enable memory regions");
>>>>> + exit(1);
>>>>> + }
>>>>> +
>>>>> /* allocate and load BIOS */
>>>>> if (machine->firmware) {
>>>>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>>>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>>>>> index 2ca42fdef6..1e02347e57 100644
>>>>> --- a/hw/ppc/ppc405_uc.c
>>>>> +++ b/hw/ppc/ppc405_uc.c
>>>>> @@ -1081,8 +1081,7 @@ static void ppc405_soc_realize(DeviceState *dev,
>>>>> Error **errp)
>>>>> s->ram_bases[0], s->ram_sizes[0]);
>>>>> ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
>>>>> - s->ram_banks, s->ram_bases, s->ram_sizes,
>>>>> - s->do_dram_init);
>>>>> + s->ram_banks, s->ram_bases, s->ram_sizes);
>>>>> /* External bus controller */
>>>>> if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu,
>>>>> errp)) {
>>>>> @@ -1160,7 +1159,6 @@ static void ppc405_soc_realize(DeviceState *dev,
>>>>> Error **errp)
>>>>> static Property ppc405_soc_properties[] = {
>>>>> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr,
>>>>> TYPE_MEMORY_REGION,
>>>>> MemoryRegion *),
>>>>> - DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
>>>>> DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
>>>>> DEFINE_PROP_END_OF_LIST(),
>>>>> };
>>>>> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
>>>>> index 5ec82fa8c2..e3412c4fcd 100644
>>>>> --- a/hw/ppc/ppc440_bamboo.c
>>>>> +++ b/hw/ppc/ppc440_bamboo.c
>>>>> @@ -211,7 +211,13 @@ static void bamboo_init(MachineState *machine)
>>>>> ppc4xx_sdram_init(env,
>>>>> qdev_get_gpio_in(uicdev, 14),
>>>>> PPC440EP_SDRAM_NR_BANKS, ram_memories,
>>>>> - ram_bases, ram_sizes, 1);
>>>>> + ram_bases, ram_sizes);
>>>>> + /* Enable SDRAM memory regions, this should be done by the firmware
>>>>> */
>>>>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>>>>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>>>>> + error_report("couldn't enable memory regions");
>>>>> + exit(1);
>>>>> + }
>>>>> /* PCI */
>>>>> dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
>>>>> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
>>>>> index db33334e29..6ab0ad7985 100644
>>>>> --- a/hw/ppc/ppc440_uc.c
>>>>> +++ b/hw/ppc/ppc440_uc.c
>>>>> @@ -489,8 +489,6 @@ typedef struct ppc440_sdram_t {
>>>>> } ppc440_sdram_t;
>>>>> enum {
>>>>> - SDRAM0_CFGADDR = 0x10,
>>>>> - SDRAM0_CFGDATA,
>>>>> SDRAM_R0BAS = 0x40,
>>>>> SDRAM_R1BAS,
>>>>> SDRAM_R2BAS,
>>>>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>>>>> index 1226ec4aa9..936d6f77fe 100644
>>>>> --- a/hw/ppc/ppc4xx_devs.c
>>>>> +++ b/hw/ppc/ppc4xx_devs.c
>>>>> @@ -56,11 +56,6 @@ struct ppc4xx_sdram_t {
>>>>> qemu_irq irq;
>>>>> };
>>>>> -enum {
>>>>> - SDRAM0_CFGADDR = 0x010,
>>>>> - SDRAM0_CFGDATA = 0x011,
>>>>> -};
>>>>> -
>>>>> /*
>>>>> * XXX: TOFIX: some patches have made this code become inconsistent:
>>>>> * there are type inconsistencies, mixing hwaddr, target_ulong
>>>>> @@ -350,8 +345,7 @@ static void sdram_reset(void *opaque)
>>>>> void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
>>>>> MemoryRegion *ram_memories,
>>>>> hwaddr *ram_bases,
>>>>> - hwaddr *ram_sizes,
>>>>> - int do_init)
>>>>> + hwaddr *ram_sizes)
>>>>> {
>>>>> ppc4xx_sdram_t *sdram;
>>>>> int i;
>>>>> @@ -369,9 +363,6 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq
>>>>> irq, int nbanks,
>>>>> sdram, &dcr_read_sdram, &dcr_write_sdram);
>>>>> ppc_dcr_register(env, SDRAM0_CFGDATA,
>>>>> sdram, &dcr_read_sdram, &dcr_write_sdram);
>>>>> - if (do_init) {
>>>>> - sdram_map_bcr(sdram);
>>>>> - }
>>>>> }
>>>>> /*
>>>>> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
>>>>> index 2af0d60577..a5e6c185af 100644
>>>>> --- a/include/hw/ppc/ppc4xx.h
>>>>> +++ b/include/hw/ppc/ppc4xx.h
>>>>> @@ -37,6 +37,11 @@ typedef struct {
>>>>> uint32_t bcr;
>>>>> } Ppc4xxSdramBank;
>>>>> +enum {
>>>>> + SDRAM0_CFGADDR = 0x010,
>>>>> + SDRAM0_CFGDATA = 0x011,
>>>>> +};
>>>>> +
>>>>> void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
>>>>> MemoryRegion ram_memories[],
>>>>> hwaddr ram_bases[], hwaddr ram_sizes[],
>>>>> @@ -45,8 +50,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int
>>>>> nr_banks,
>>>>> void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
>>>>> MemoryRegion ram_memories[],
>>>>> hwaddr *ram_bases,
>>>>> - hwaddr *ram_sizes,
>>>>> - int do_init);
>>>>> + hwaddr *ram_sizes);
>>>>> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>>>>>
>>>>
>>>>
>>>>
>>
>>
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack
2022-09-14 18:32 ` BALATON Zoltan
@ 2022-09-18 7:34 ` Cédric Le Goater
2022-09-18 10:27 ` BALATON Zoltan
0 siblings, 1 reply; 41+ messages in thread
From: Cédric Le Goater @ 2022-09-18 7:34 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
On 9/14/22 20:32, BALATON Zoltan wrote:
> On Wed, 14 Sep 2022, BALATON Zoltan wrote:
>> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>>> On 9/14/22 13:44, BALATON Zoltan wrote:
>>>> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>>>>> On 9/13/22 21:52, BALATON Zoltan wrote:
>>>>>> The do_init parameter of ppc4xx_sdram_init() is used to map memory
>>>>>> regions that is normally done by the firmware by programming the SDRAM
>>>>>> controller. This is needed when booting a kernel directly from -kernel
>>>>>> without a firmware. Do this from board code accesing normal SDRAM
>>>>>
>>>>> accessing
>>>>
>>>> Fixed, also two ofhers in another patch you haven't noticed.
>>>>
>>>>>> controller registers the same way as firmware would do, so we can get
>>>>>> rid of this hack.
>>>>>>
>>>>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>>>>> ---
>>>>>> v2: Fix ref405ep boot with -kernel and U-Boot
>>>>>>
>>>>>> hw/ppc/ppc405.h | 1 -
>>>>>> hw/ppc/ppc405_boards.c | 12 ++++++++++--
>>>>>> hw/ppc/ppc405_uc.c | 4 +---
>>>>>> hw/ppc/ppc440_bamboo.c | 8 +++++++-
>>>>>> hw/ppc/ppc440_uc.c | 2 --
>>>>>> hw/ppc/ppc4xx_devs.c | 11 +----------
>>>>>> include/hw/ppc/ppc4xx.h | 8 ++++++--
>>>>>> 7 files changed, 25 insertions(+), 21 deletions(-)
>>>>>>
>>>>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>>>>> index 1e558c7831..756865621b 100644
>>>>>> --- a/hw/ppc/ppc405.h
>>>>>> +++ b/hw/ppc/ppc405.h
>>>>>> @@ -169,7 +169,6 @@ struct Ppc405SoCState {
>>>>>> /* Public */
>>>>>> MemoryRegion ram_banks[2];
>>>>>> hwaddr ram_bases[2], ram_sizes[2];
>>>>>> - bool do_dram_init;
>>>>>> MemoryRegion *dram_mr;
>>>>>> hwaddr ram_size;
>>>>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>>>>> index 083f12b23e..bf02a71c6d 100644
>>>>>> --- a/hw/ppc/ppc405_boards.c
>>>>>> +++ b/hw/ppc/ppc405_boards.c
>>>>>> @@ -274,6 +274,7 @@ static void ppc405_init(MachineState *machine)
>>>>>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>>>>>> const char *kernel_filename = machine->kernel_filename;
>>>>>> MemoryRegion *sysmem = get_system_memory();
>>>>>> + CPUPPCState *env;
>>>>>> if (machine->ram_size != mc->default_ram_size) {
>>>>>> char *sz = size_to_str(mc->default_ram_size);
>>>>>> @@ -288,12 +289,19 @@ static void ppc405_init(MachineState *machine)
>>>>>> machine->ram_size, &error_fatal);
>>>>>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>>>>>> OBJECT(machine->ram), &error_abort);
>>>>>> - object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>>>>>> - kernel_filename != NULL, &error_abort);
>>>>>> object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
>>>>>> &error_abort);
>>>>>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
>>>>>> + /* Enable SDRAM memory regions */
>>>>>> + /* FIXME This shouldn't be needed with firmware but we lack SPD data */
>>>>>
>>>>> what do you mean ?
>>>>
>>>> U-Boot detects the available RAM by reading the SPD info of the RAM modules but that probably also needs i2c emulation. See sam460ex.
>>>>
>>>>>> + env = &ppc405->soc.cpu.env;
>>>>>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>>>>>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>>>>>
>>>>>
>>>>> I am not in favor of these ppc_drc_write calls and this is still a hack.
>>>>
>>>> It's not. Normally this is done by firmware to enable memory controller but the board code has to do it if not using firmware (e.g. booting with -kernel) the same way it provides bootinfo or device tree mods the firmware would normally do or in this case maybe the emulation is incomplete so the part of firmware that configures the SDRAM controller does not run.
>>>
>>> Exactly, and what the above proposal does is mimicking execution of CPU
>>> instructions before the CPU is even fully initiated. Reset has not been
>>> called at that stage.
>>
>> I don't get this. We're not calling any CPU instructions, ppc_dcr_write just calls the write callback the device has registered for the dcr so it just does the same as the hack did at the end just doing it the same way the firmware should do.
>>
>>>>> The "dram-init" property is a cleaner solution. It takes care of doing the
>>>>> pre-mapping of RAM banks in the realize routine of the sdram model (when
>>>>> available).
>>>>
>>>> I disagree, the hardware does not have such feature, it proviesd DCRs as the way to configure it. Adding a special property for it deviates from hardware and clutters qtree.
>>>
>>>
>>> In this machine, running QEMU with -kernel deviates from HW. That's
>>
>> In all machines booting with -kernel likely deviates and all machines probably have additinal code in this case to do some things normally done by the firmware. Look at pegasos2_machine_reset() for example. All that is not needed when we boot with firmware as then the firmware will do all that and provide the device tree, etc. bur we need to do these when booting without firmware. In thes case QEMU also emulates the firmware and has to do thinigs like enabling the memory controller.
>>
>>> the whole purpose of this option. It assumes that the SDRAM device
>>> is pre-initialized (and much more should be done) by the QEMU machine
>>> and the simplest way to acheive this goal is to inform the SDRAM model
>>> to take care of the pre-initialization.
>>
>> In my opinion the SDRAM controller model should model the hardware and if the board uses it differently then it should take care of that and not change the model.
>>
>>> Another way would be to change the default reset values of the SDRAM
>>> registers (in the realize method using some property) and perform
>>> some actions (mapping the banks) in the reset handler of the SDRAM
>>> device model. That would be a deferred initialization but a property
>>> is still needed to change the default behavior of the SDRAM model.
>>>
>>> Anyhow, this should be isolated under the SDRAM device model and
>>> not in the machine init by using the CPU state. That's clearly ugly.
>
> Additionally, if you don't like the FIXME comment,
I didn't understand it. That's different.
> it's there because this would really belong at the beginning of boot_from_kernel() function before that calls ppc405_set_bootinfo which is called when booting without firmware but I left it where it was in init for now because you menfioned that firmware boot was also broken
hmm ? but It's not anymore. v2 broke it I think.
> when I had it at the end of boot_from_kernel so I suspect the board is not providing the SPD data so the firmware cannot detect the RAM and this why it's not enabling the SDRAM itself (or maybe that part is even compiled out because of that) but then it's a limitation of the board emulation and not the SDRAM controller so it should be handled in the board code.
Here is the U-boot tree that can be used :
https://gitlab.com/huth/u-boot/-/tree/taihu
and the SDRAM init hacks :
https://gitlab.com/huth/u-boot/-/commit/296e0479a972fa57390f0f3a912650168dabe851
May be there is a way to fix the model to remove the U-boot hack.
Thomas added a uboot.bin in the tree which is used by :
tests/avocado/ppc_405.py
Thanks,
C.
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack
2022-09-18 7:34 ` Cédric Le Goater
@ 2022-09-18 10:27 ` BALATON Zoltan
2022-09-18 10:35 ` BALATON Zoltan
0 siblings, 1 reply; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-18 10:27 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 10124 bytes --]
On Sun, 18 Sep 2022, Cédric Le Goater wrote:
> On 9/14/22 20:32, BALATON Zoltan wrote:
>> On Wed, 14 Sep 2022, BALATON Zoltan wrote:
>>> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>>>> On 9/14/22 13:44, BALATON Zoltan wrote:
>>>>> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>>>>>> On 9/13/22 21:52, BALATON Zoltan wrote:
>>>>>>> The do_init parameter of ppc4xx_sdram_init() is used to map memory
>>>>>>> regions that is normally done by the firmware by programming the SDRAM
>>>>>>> controller. This is needed when booting a kernel directly from -kernel
>>>>>>> without a firmware. Do this from board code accesing normal SDRAM
>>>>>>
>>>>>> accessing
>>>>>
>>>>> Fixed, also two ofhers in another patch you haven't noticed.
>>>>>
>>>>>>> controller registers the same way as firmware would do, so we can get
>>>>>>> rid of this hack.
>>>>>>>
>>>>>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>>>>>> ---
>>>>>>> v2: Fix ref405ep boot with -kernel and U-Boot
>>>>>>>
>>>>>>> hw/ppc/ppc405.h | 1 -
>>>>>>> hw/ppc/ppc405_boards.c | 12 ++++++++++--
>>>>>>> hw/ppc/ppc405_uc.c | 4 +---
>>>>>>> hw/ppc/ppc440_bamboo.c | 8 +++++++-
>>>>>>> hw/ppc/ppc440_uc.c | 2 --
>>>>>>> hw/ppc/ppc4xx_devs.c | 11 +----------
>>>>>>> include/hw/ppc/ppc4xx.h | 8 ++++++--
>>>>>>> 7 files changed, 25 insertions(+), 21 deletions(-)
>>>>>>>
>>>>>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>>>>>> index 1e558c7831..756865621b 100644
>>>>>>> --- a/hw/ppc/ppc405.h
>>>>>>> +++ b/hw/ppc/ppc405.h
>>>>>>> @@ -169,7 +169,6 @@ struct Ppc405SoCState {
>>>>>>> /* Public */
>>>>>>> MemoryRegion ram_banks[2];
>>>>>>> hwaddr ram_bases[2], ram_sizes[2];
>>>>>>> - bool do_dram_init;
>>>>>>> MemoryRegion *dram_mr;
>>>>>>> hwaddr ram_size;
>>>>>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>>>>>> index 083f12b23e..bf02a71c6d 100644
>>>>>>> --- a/hw/ppc/ppc405_boards.c
>>>>>>> +++ b/hw/ppc/ppc405_boards.c
>>>>>>> @@ -274,6 +274,7 @@ static void ppc405_init(MachineState *machine)
>>>>>>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>>>>>>> const char *kernel_filename = machine->kernel_filename;
>>>>>>> MemoryRegion *sysmem = get_system_memory();
>>>>>>> + CPUPPCState *env;
>>>>>>> if (machine->ram_size != mc->default_ram_size) {
>>>>>>> char *sz = size_to_str(mc->default_ram_size);
>>>>>>> @@ -288,12 +289,19 @@ static void ppc405_init(MachineState *machine)
>>>>>>> machine->ram_size, &error_fatal);
>>>>>>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>>>>>>> OBJECT(machine->ram), &error_abort);
>>>>>>> - object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>>>>>>> - kernel_filename != NULL, &error_abort);
>>>>>>> object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk",
>>>>>>> 33333333,
>>>>>>> &error_abort);
>>>>>>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
>>>>>>> + /* Enable SDRAM memory regions */
>>>>>>> + /* FIXME This shouldn't be needed with firmware but we lack SPD
>>>>>>> data */
>>>>>>
>>>>>> what do you mean ?
>>>>>
>>>>> U-Boot detects the available RAM by reading the SPD info of the RAM
>>>>> modules but that probably also needs i2c emulation. See sam460ex.
>>>>>
>>>>>>> + env = &ppc405->soc.cpu.env;
>>>>>>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>>>>>>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>>>>>>
>>>>>>
>>>>>> I am not in favor of these ppc_drc_write calls and this is still a
>>>>>> hack.
>>>>>
>>>>> It's not. Normally this is done by firmware to enable memory controller
>>>>> but the board code has to do it if not using firmware (e.g. booting with
>>>>> -kernel) the same way it provides bootinfo or device tree mods the
>>>>> firmware would normally do or in this case maybe the emulation is
>>>>> incomplete so the part of firmware that configures the SDRAM controller
>>>>> does not run.
>>>>
>>>> Exactly, and what the above proposal does is mimicking execution of CPU
>>>> instructions before the CPU is even fully initiated. Reset has not been
>>>> called at that stage.
>>>
>>> I don't get this. We're not calling any CPU instructions, ppc_dcr_write
>>> just calls the write callback the device has registered for the dcr so it
>>> just does the same as the hack did at the end just doing it the same way
>>> the firmware should do.
>>>
>>>>>> The "dram-init" property is a cleaner solution. It takes care of doing
>>>>>> the
>>>>>> pre-mapping of RAM banks in the realize routine of the sdram model
>>>>>> (when
>>>>>> available).
>>>>>
>>>>> I disagree, the hardware does not have such feature, it proviesd DCRs as
>>>>> the way to configure it. Adding a special property for it deviates from
>>>>> hardware and clutters qtree.
>>>>
>>>>
>>>> In this machine, running QEMU with -kernel deviates from HW. That's
>>>
>>> In all machines booting with -kernel likely deviates and all machines
>>> probably have additinal code in this case to do some things normally done
>>> by the firmware. Look at pegasos2_machine_reset() for example. All that is
>>> not needed when we boot with firmware as then the firmware will do all
>>> that and provide the device tree, etc. bur we need to do these when
>>> booting without firmware. In thes case QEMU also emulates the firmware and
>>> has to do thinigs like enabling the memory controller.
>>>
>>>> the whole purpose of this option. It assumes that the SDRAM device
>>>> is pre-initialized (and much more should be done) by the QEMU machine
>>>> and the simplest way to acheive this goal is to inform the SDRAM model
>>>> to take care of the pre-initialization.
>>>
>>> In my opinion the SDRAM controller model should model the hardware and if
>>> the board uses it differently then it should take care of that and not
>>> change the model.
>>>
>>>> Another way would be to change the default reset values of the SDRAM
>>>> registers (in the realize method using some property) and perform
>>>> some actions (mapping the banks) in the reset handler of the SDRAM
>>>> device model. That would be a deferred initialization but a property
>>>> is still needed to change the default behavior of the SDRAM model.
>>>>
>>>> Anyhow, this should be isolated under the SDRAM device model and
>>>> not in the machine init by using the CPU state. That's clearly ugly.
>>
>> Additionally, if you don't like the FIXME comment,
>
> I didn't understand it. That's different.
>
>> it's there because this would really belong at the beginning of
>> boot_from_kernel() function before that calls ppc405_set_bootinfo which is
>> called when booting without firmware but I left it where it was in init for
>> now because you menfioned that firmware boot was also broken
>
> hmm ? but It's not anymore. v2 broke it I think.
First I've put enabling SDRAM controller in boot_from_kernel at the end
before qemu_register_reset but this is wrong as the bootinfo is written in
RAM so it should be enabled before. So this should be done at the
beginning of boot_from_kernel but you said my first version not only broke
-kernel but also booting with firmware so that told me firmware also does
not enable the SDRAM conroller itself (as now seen below it's disabled) so
I moved enabling back to where it was in init. Ideally it should be done
by the firmware if using that or QEMU at the beginning of boot_from_kernel
when emulating firmwere but that does not work yet so that's why we have
the FIXME comment to remind for this.
>> when I had it at the end of boot_from_kernel so I suspect the board is not
>> providing the SPD data so the firmware cannot detect the RAM and this why
>> it's not enabling the SDRAM itself (or maybe that part is even compiled out
>> because of that) but then it's a limitation of the board emulation and not
>> the SDRAM controller so it should be handled in the board code.
>
> Here is the U-boot tree that can be used :
>
> https://gitlab.com/huth/u-boot/-/tree/taihu
>
> and the SDRAM init hacks :
> https://gitlab.com/huth/u-boot/-/commit/296e0479a972fa57390f0f3a912650168dabe851
>
> May be there is a way to fix the model to remove the U-boot hack.
I don't know how that works for 405. For 440 used by Sam460ex u-boot reads
the SPD EEPROMs to detect memmory size and configures the SDRAM DDR2
controller according to that but that needs i2c and SPD data as in
sam460ex.c. The code you pointed to seems to try a fixed table of valid
RAM sizes in mb0cf[] that is either taken from CONFIG_SYS_SDRAM_TABLE
value or use default of 128, 64, 32, 16, 4 MB. Maybe the model can be
changed to allow this check to succeed so it does not have to be disabled
but I don't know what it really tries to do here. The SoC manual may also
have some docs on the register which you could check if you have it. This
controller should be the same as in some 440 with DDR SDRAM. I think there
are three different memory controllers in these SoCs: SDRAM, DDR and DDR2.
The 460EX has DDR2, the 440 in bamboo has DDR and I think this is
backwards compatible with SDRAM in 405 but the 440 DDR controller has some
more regs for ECC. Therefore in QEMU we mostly only model DDR2 and DDR and
use DDR instead of SDRAM in 405 as its common regs are likely the same but
I don't have docs to prove it, I've only seen docs on 440 DDR so it's just
what I've found while doing this series. Anyway you should keep this in
mind when changing the DDR model and also check bamboo firmware which I
don't have.
Regards,
BALATON Zoltan
>
> Thomas added a uboot.bin in the tree which is used by :
>
> tests/avocado/ppc_405.py
>
> Thanks,
>
> C.
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack
2022-09-18 10:27 ` BALATON Zoltan
@ 2022-09-18 10:35 ` BALATON Zoltan
0 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-18 10:35 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 10808 bytes --]
On Sun, 18 Sep 2022, BALATON Zoltan wrote:
> On Sun, 18 Sep 2022, Cédric Le Goater wrote:
>> On 9/14/22 20:32, BALATON Zoltan wrote:
>>> On Wed, 14 Sep 2022, BALATON Zoltan wrote:
>>>> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>>>>> On 9/14/22 13:44, BALATON Zoltan wrote:
>>>>>> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>>>>>>> On 9/13/22 21:52, BALATON Zoltan wrote:
>>>>>>>> The do_init parameter of ppc4xx_sdram_init() is used to map memory
>>>>>>>> regions that is normally done by the firmware by programming the
>>>>>>>> SDRAM
>>>>>>>> controller. This is needed when booting a kernel directly from
>>>>>>>> -kernel
>>>>>>>> without a firmware. Do this from board code accesing normal SDRAM
>>>>>>>
>>>>>>> accessing
>>>>>>
>>>>>> Fixed, also two ofhers in another patch you haven't noticed.
>>>>>>
>>>>>>>> controller registers the same way as firmware would do, so we can get
>>>>>>>> rid of this hack.
>>>>>>>>
>>>>>>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>>>>>>> ---
>>>>>>>> v2: Fix ref405ep boot with -kernel and U-Boot
>>>>>>>>
>>>>>>>> hw/ppc/ppc405.h | 1 -
>>>>>>>> hw/ppc/ppc405_boards.c | 12 ++++++++++--
>>>>>>>> hw/ppc/ppc405_uc.c | 4 +---
>>>>>>>> hw/ppc/ppc440_bamboo.c | 8 +++++++-
>>>>>>>> hw/ppc/ppc440_uc.c | 2 --
>>>>>>>> hw/ppc/ppc4xx_devs.c | 11 +----------
>>>>>>>> include/hw/ppc/ppc4xx.h | 8 ++++++--
>>>>>>>> 7 files changed, 25 insertions(+), 21 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>>>>>>> index 1e558c7831..756865621b 100644
>>>>>>>> --- a/hw/ppc/ppc405.h
>>>>>>>> +++ b/hw/ppc/ppc405.h
>>>>>>>> @@ -169,7 +169,6 @@ struct Ppc405SoCState {
>>>>>>>> /* Public */
>>>>>>>> MemoryRegion ram_banks[2];
>>>>>>>> hwaddr ram_bases[2], ram_sizes[2];
>>>>>>>> - bool do_dram_init;
>>>>>>>> MemoryRegion *dram_mr;
>>>>>>>> hwaddr ram_size;
>>>>>>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>>>>>>> index 083f12b23e..bf02a71c6d 100644
>>>>>>>> --- a/hw/ppc/ppc405_boards.c
>>>>>>>> +++ b/hw/ppc/ppc405_boards.c
>>>>>>>> @@ -274,6 +274,7 @@ static void ppc405_init(MachineState *machine)
>>>>>>>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>>>>>>>> const char *kernel_filename = machine->kernel_filename;
>>>>>>>> MemoryRegion *sysmem = get_system_memory();
>>>>>>>> + CPUPPCState *env;
>>>>>>>> if (machine->ram_size != mc->default_ram_size) {
>>>>>>>> char *sz = size_to_str(mc->default_ram_size);
>>>>>>>> @@ -288,12 +289,19 @@ static void ppc405_init(MachineState *machine)
>>>>>>>> machine->ram_size, &error_fatal);
>>>>>>>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>>>>>>>> OBJECT(machine->ram), &error_abort);
>>>>>>>> - object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>>>>>>>> - kernel_filename != NULL, &error_abort);
>>>>>>>> object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk",
>>>>>>>> 33333333,
>>>>>>>> &error_abort);
>>>>>>>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
>>>>>>>> + /* Enable SDRAM memory regions */
>>>>>>>> + /* FIXME This shouldn't be needed with firmware but we lack SPD
>>>>>>>> data */
>>>>>>>
>>>>>>> what do you mean ?
>>>>>>
>>>>>> U-Boot detects the available RAM by reading the SPD info of the RAM
>>>>>> modules but that probably also needs i2c emulation. See sam460ex.
>>>>>>
>>>>>>>> + env = &ppc405->soc.cpu.env;
>>>>>>>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>>>>>>>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>>>>>>>
>>>>>>>
>>>>>>> I am not in favor of these ppc_drc_write calls and this is still a
>>>>>>> hack.
>>>>>>
>>>>>> It's not. Normally this is done by firmware to enable memory controller
>>>>>> but the board code has to do it if not using firmware (e.g. booting
>>>>>> with -kernel) the same way it provides bootinfo or device tree mods the
>>>>>> firmware would normally do or in this case maybe the emulation is
>>>>>> incomplete so the part of firmware that configures the SDRAM controller
>>>>>> does not run.
>>>>>
>>>>> Exactly, and what the above proposal does is mimicking execution of CPU
>>>>> instructions before the CPU is even fully initiated. Reset has not been
>>>>> called at that stage.
>>>>
>>>> I don't get this. We're not calling any CPU instructions, ppc_dcr_write
>>>> just calls the write callback the device has registered for the dcr so it
>>>> just does the same as the hack did at the end just doing it the same way
>>>> the firmware should do.
>>>>
>>>>>>> The "dram-init" property is a cleaner solution. It takes care of doing
>>>>>>> the
>>>>>>> pre-mapping of RAM banks in the realize routine of the sdram model
>>>>>>> (when
>>>>>>> available).
>>>>>>
>>>>>> I disagree, the hardware does not have such feature, it proviesd DCRs
>>>>>> as the way to configure it. Adding a special property for it deviates
>>>>>> from hardware and clutters qtree.
>>>>>
>>>>>
>>>>> In this machine, running QEMU with -kernel deviates from HW. That's
>>>>
>>>> In all machines booting with -kernel likely deviates and all machines
>>>> probably have additinal code in this case to do some things normally done
>>>> by the firmware. Look at pegasos2_machine_reset() for example. All that
>>>> is not needed when we boot with firmware as then the firmware will do all
>>>> that and provide the device tree, etc. bur we need to do these when
>>>> booting without firmware. In thes case QEMU also emulates the firmware
>>>> and has to do thinigs like enabling the memory controller.
>>>>
>>>>> the whole purpose of this option. It assumes that the SDRAM device
>>>>> is pre-initialized (and much more should be done) by the QEMU machine
>>>>> and the simplest way to acheive this goal is to inform the SDRAM model
>>>>> to take care of the pre-initialization.
>>>>
>>>> In my opinion the SDRAM controller model should model the hardware and if
>>>> the board uses it differently then it should take care of that and not
>>>> change the model.
>>>>
>>>>> Another way would be to change the default reset values of the SDRAM
>>>>> registers (in the realize method using some property) and perform
>>>>> some actions (mapping the banks) in the reset handler of the SDRAM
>>>>> device model. That would be a deferred initialization but a property
>>>>> is still needed to change the default behavior of the SDRAM model.
>>>>>
>>>>> Anyhow, this should be isolated under the SDRAM device model and
>>>>> not in the machine init by using the CPU state. That's clearly ugly.
>>>
>>> Additionally, if you don't like the FIXME comment,
>>
>> I didn't understand it. That's different.
>>
>>> it's there because this would really belong at the beginning of
>>> boot_from_kernel() function before that calls ppc405_set_bootinfo which is
>>> called when booting without firmware but I left it where it was in init
>>> for now because you menfioned that firmware boot was also broken
>>
>> hmm ? but It's not anymore. v2 broke it I think.
>
> First I've put enabling SDRAM controller in boot_from_kernel at the end
> before qemu_register_reset but this is wrong as the bootinfo is written in
> RAM so it should be enabled before. So this should be done at the beginning
> of boot_from_kernel but you said my first version not only broke -kernel but
> also booting with firmware so that told me firmware also does not enable the
> SDRAM conroller itself (as now seen below it's disabled) so I moved enabling
On second look, enabling the memory controller in line 195 is not
#ifdef-ed out so maybe it would work with enable only at the beginning of
boot_from_kernel, I'll try to test with the firmware. For removing the
hack the register values would need to be checked but that's something I
don't want to do. You could look at that later as a follow up.
Regards,
BALATON Zoltan
> back to where it was in init. Ideally it should be done by the firmware if
> using that or QEMU at the beginning of boot_from_kernel when emulating
> firmwere but that does not work yet so that's why we have the FIXME comment
> to remind for this.
>
>>> when I had it at the end of boot_from_kernel so I suspect the board is not
>>> providing the SPD data so the firmware cannot detect the RAM and this why
>>> it's not enabling the SDRAM itself (or maybe that part is even compiled
>>> out because of that) but then it's a limitation of the board emulation and
>>> not the SDRAM controller so it should be handled in the board code.
>>
>> Here is the U-boot tree that can be used :
>>
>> https://gitlab.com/huth/u-boot/-/tree/taihu
>>
>> and the SDRAM init hacks :
>> https://gitlab.com/huth/u-boot/-/commit/296e0479a972fa57390f0f3a912650168dabe851
>>
>> May be there is a way to fix the model to remove the U-boot hack.
>
> I don't know how that works for 405. For 440 used by Sam460ex u-boot reads
> the SPD EEPROMs to detect memmory size and configures the SDRAM DDR2
> controller according to that but that needs i2c and SPD data as in
> sam460ex.c. The code you pointed to seems to try a fixed table of valid RAM
> sizes in mb0cf[] that is either taken from CONFIG_SYS_SDRAM_TABLE value or
> use default of 128, 64, 32, 16, 4 MB. Maybe the model can be changed to allow
> this check to succeed so it does not have to be disabled but I don't know
> what it really tries to do here. The SoC manual may also have some docs on
> the register which you could check if you have it. This controller should be
> the same as in some 440 with DDR SDRAM. I think there are three different
> memory controllers in these SoCs: SDRAM, DDR and DDR2. The 460EX has DDR2,
> the 440 in bamboo has DDR and I think this is backwards compatible with SDRAM
> in 405 but the 440 DDR controller has some more regs for ECC. Therefore in
> QEMU we mostly only model DDR2 and DDR and use DDR instead of SDRAM in 405 as
> its common regs are likely the same but I don't have docs to prove it, I've
> only seen docs on 440 DDR so it's just what I've found while doing this
> series. Anyway you should keep this in mind when changing the DDR model and
> also check bamboo firmware which I don't have.
>
> Regards,
> BALATON Zoltan
>
>>
>> Thomas added a uboot.bin in the tree which is used by :
>>
>> tests/avocado/ppc_405.py
>>
>> Thanks,
>>
>> C.
>>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack
2022-09-14 18:25 ` BALATON Zoltan
2022-09-14 18:32 ` BALATON Zoltan
@ 2022-09-18 7:34 ` Cédric Le Goater
2022-09-18 21:35 ` BALATON Zoltan
1 sibling, 1 reply; 41+ messages in thread
From: Cédric Le Goater @ 2022-09-18 7:34 UTC (permalink / raw)
To: BALATON Zoltan
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
On 9/14/22 20:25, BALATON Zoltan wrote:
> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>> On 9/14/22 13:44, BALATON Zoltan wrote:
>>> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>>>> On 9/13/22 21:52, BALATON Zoltan wrote:
>>>>> The do_init parameter of ppc4xx_sdram_init() is used to map memory
>>>>> regions that is normally done by the firmware by programming the SDRAM
>>>>> controller. This is needed when booting a kernel directly from -kernel
>>>>> without a firmware. Do this from board code accesing normal SDRAM
>>>>
>>>> accessing
>>>
>>> Fixed, also two ofhers in another patch you haven't noticed.
>>>
>>>>> controller registers the same way as firmware would do, so we can get
>>>>> rid of this hack.
>>>>>
>>>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>>>> ---
>>>>> v2: Fix ref405ep boot with -kernel and U-Boot
>>>>>
>>>>> hw/ppc/ppc405.h | 1 -
>>>>> hw/ppc/ppc405_boards.c | 12 ++++++++++--
>>>>> hw/ppc/ppc405_uc.c | 4 +---
>>>>> hw/ppc/ppc440_bamboo.c | 8 +++++++-
>>>>> hw/ppc/ppc440_uc.c | 2 --
>>>>> hw/ppc/ppc4xx_devs.c | 11 +----------
>>>>> include/hw/ppc/ppc4xx.h | 8 ++++++--
>>>>> 7 files changed, 25 insertions(+), 21 deletions(-)
>>>>>
>>>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>>>> index 1e558c7831..756865621b 100644
>>>>> --- a/hw/ppc/ppc405.h
>>>>> +++ b/hw/ppc/ppc405.h
>>>>> @@ -169,7 +169,6 @@ struct Ppc405SoCState {
>>>>> /* Public */
>>>>> MemoryRegion ram_banks[2];
>>>>> hwaddr ram_bases[2], ram_sizes[2];
>>>>> - bool do_dram_init;
>>>>> MemoryRegion *dram_mr;
>>>>> hwaddr ram_size;
>>>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>>>> index 083f12b23e..bf02a71c6d 100644
>>>>> --- a/hw/ppc/ppc405_boards.c
>>>>> +++ b/hw/ppc/ppc405_boards.c
>>>>> @@ -274,6 +274,7 @@ static void ppc405_init(MachineState *machine)
>>>>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>>>>> const char *kernel_filename = machine->kernel_filename;
>>>>> MemoryRegion *sysmem = get_system_memory();
>>>>> + CPUPPCState *env;
>>>>> if (machine->ram_size != mc->default_ram_size) {
>>>>> char *sz = size_to_str(mc->default_ram_size);
>>>>> @@ -288,12 +289,19 @@ static void ppc405_init(MachineState *machine)
>>>>> machine->ram_size, &error_fatal);
>>>>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>>>>> OBJECT(machine->ram), &error_abort);
>>>>> - object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>>>>> - kernel_filename != NULL, &error_abort);
>>>>> object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
>>>>> &error_abort);
>>>>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
>>>>> + /* Enable SDRAM memory regions */
>>>>> + /* FIXME This shouldn't be needed with firmware but we lack SPD data */
>>>>
>>>> what do you mean ?
>>>
>>> U-Boot detects the available RAM by reading the SPD info of the RAM modules but that probably also needs i2c emulation. See sam460ex.
>>>
>>>>> + env = &ppc405->soc.cpu.env;
>>>>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>>>>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>>>>
>>>>
>>>> I am not in favor of these ppc_drc_write calls and this is still a hack.
>>>
>>> It's not. Normally this is done by firmware to enable memory controller but the board code has to do it if not using firmware (e.g. booting with -kernel) the same way it provides bootinfo or device tree mods the firmware would normally do or in this case maybe the emulation is incomplete so the part of firmware that configures the SDRAM controller does not run.
>>
>> Exactly, and what the above proposal does is mimicking execution of CPU
>> instructions before the CPU is even fully initiated. Reset has not been
>> called at that stage.
>
> I don't get this. We're not calling any CPU instructions, ppc_dcr_write just calls the write callback the device has registered for the dcr so it just does the same as the hack did at the end just doing it the same way the firmware should do.
>
>>>> The "dram-init" property is a cleaner solution. It takes care of doing the
>>>> pre-mapping of RAM banks in the realize routine of the sdram model (when
>>>> available).
>>>
>>> I disagree, the hardware does not have such feature, it proviesd DCRs as the way to configure it. Adding a special property for it deviates from hardware and clutters qtree.
>>
>>
>> In this machine, running QEMU with -kernel deviates from HW. That's
>
> In all machines booting with -kernel likely deviates and all machines probably have additinal code in this case to do some things normally done by the firmware. Look at pegasos2_machine_reset() for example. All that is not needed when we boot with firmware as then the firmware will do all that and provide the device tree, etc. bur we need to do these when booting without firmware. In thes case QEMU also emulates the firmware and has to do thinigs like enabling the memory controller.
>
>> the whole purpose of this option. It assumes that the SDRAM device
>> is pre-initialized (and much more should be done) by the QEMU machine
>> and the simplest way to acheive this goal is to inform the SDRAM model
>> to take care of the pre-initialization.
>
> In my opinion the SDRAM controller model should model the hardware and if the board uses it differently then it should take care of that and not change the model.
>
>> Another way would be to change the default reset values of the SDRAM
>> registers (in the realize method using some property) and perform
>> some actions (mapping the banks) in the reset handler of the SDRAM
>> device model. That would be a deferred initialization but a property
>> is still needed to change the default behavior of the SDRAM model.
>>
>> Anyhow, this should be isolated under the SDRAM device model and
>> not in the machine init by using the CPU state. That's clearly ugly.
>
> Why? You already have the ppc405_set_bootinfo and all it's stuff in the ppc405 board which is also only needed without firmware.
True. ppc405_set_bootinfo() is mimicking u-boot and updating RAM to pretend
that FW already ran. It is done from under boot_from_kernel() only.
FYI, The U-boot support was quite a mess :
https://lists.ozlabs.org/pipermail/linuxppc-dev/2009-July/074487.html
> If you're opposed to the few lines enabling the memory controller being in ppc405_init
Well, that's what the init property is doing already. I do understand you
need to move the code to cleanup the SDRAM model, but there are cleaner
ways to do so.
Alternative would be to remove the SDRAM pre-init for now, change the
model and re-add it at the end when all is cleanly modified. The -kernel
support would be temporarily broken but that's fine.
On that topic, you should probably consider changing the patchset to
propose first, a new SDRAM model (without using it in the boards) and
then do the model "switch" at the end. That might be easier to review.
> I could put it in a function either in ppc405_boards.c or if you think this should be in ppc4xx_sdrem.c
> then we can export that function via include/hw/ppc/ppc4xx.h and call that from boards
Yes. That would be better.
Please call from under boot_from_kernel(), something like
sdram_map_bcr(&ppc405->soc.sdram);
> but I don't want to add hacks and a property for this in the device model becuase I'm not convinced it belongs there.
That's how the default state of a model is changed and possibly taken
into account at reset. A bit like HW strapping would work.
Typically, in that case, you could use properties to change the BCR
reg values and do the mapping accordingly at reset.
> If the hardware would have such an option then modeling that in is valid
QEMU has all kinds of extensions which makes it much more useful than HW
in some places. The frontier is not that well draw.
Thanks,
C.
> but if it's done by the firmare on the real hardware then either use the firmware or do it in board code which is then emulating the firmware too.
>
> Regards,
> BALATON Zoltan
>
>>
>> Thanks,
>>
>> C.
>>
>>
>>
>>
>>
>>> Doing it like this patch is cleaner IMO.
>>>
>>> Regards,
>>> BALATON Zoltan
>>>
>>>>
>>>> C.
>>>>
>>>>> + error_report("Could not enable memory regions");
>>>>> + exit(1);
>>>>> + }
>>>>> +
>>>>> /* allocate and load BIOS */
>>>>> if (machine->firmware) {
>>>>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>>>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>>>>> index 2ca42fdef6..1e02347e57 100644
>>>>> --- a/hw/ppc/ppc405_uc.c
>>>>> +++ b/hw/ppc/ppc405_uc.c
>>>>> @@ -1081,8 +1081,7 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>>>>> s->ram_bases[0], s->ram_sizes[0]);
>>>>> ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
>>>>> - s->ram_banks, s->ram_bases, s->ram_sizes,
>>>>> - s->do_dram_init);
>>>>> + s->ram_banks, s->ram_bases, s->ram_sizes);
>>>>> /* External bus controller */
>>>>> if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
>>>>> @@ -1160,7 +1159,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>>>>> static Property ppc405_soc_properties[] = {
>>>>> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
>>>>> MemoryRegion *),
>>>>> - DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
>>>>> DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
>>>>> DEFINE_PROP_END_OF_LIST(),
>>>>> };
>>>>> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
>>>>> index 5ec82fa8c2..e3412c4fcd 100644
>>>>> --- a/hw/ppc/ppc440_bamboo.c
>>>>> +++ b/hw/ppc/ppc440_bamboo.c
>>>>> @@ -211,7 +211,13 @@ static void bamboo_init(MachineState *machine)
>>>>> ppc4xx_sdram_init(env,
>>>>> qdev_get_gpio_in(uicdev, 14),
>>>>> PPC440EP_SDRAM_NR_BANKS, ram_memories,
>>>>> - ram_bases, ram_sizes, 1);
>>>>> + ram_bases, ram_sizes);
>>>>> + /* Enable SDRAM memory regions, this should be done by the firmware */
>>>>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>>>>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>>>>> + error_report("couldn't enable memory regions");
>>>>> + exit(1);
>>>>> + }
>>>>> /* PCI */
>>>>> dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
>>>>> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
>>>>> index db33334e29..6ab0ad7985 100644
>>>>> --- a/hw/ppc/ppc440_uc.c
>>>>> +++ b/hw/ppc/ppc440_uc.c
>>>>> @@ -489,8 +489,6 @@ typedef struct ppc440_sdram_t {
>>>>> } ppc440_sdram_t;
>>>>> enum {
>>>>> - SDRAM0_CFGADDR = 0x10,
>>>>> - SDRAM0_CFGDATA,
>>>>> SDRAM_R0BAS = 0x40,
>>>>> SDRAM_R1BAS,
>>>>> SDRAM_R2BAS,
>>>>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>>>>> index 1226ec4aa9..936d6f77fe 100644
>>>>> --- a/hw/ppc/ppc4xx_devs.c
>>>>> +++ b/hw/ppc/ppc4xx_devs.c
>>>>> @@ -56,11 +56,6 @@ struct ppc4xx_sdram_t {
>>>>> qemu_irq irq;
>>>>> };
>>>>> -enum {
>>>>> - SDRAM0_CFGADDR = 0x010,
>>>>> - SDRAM0_CFGDATA = 0x011,
>>>>> -};
>>>>> -
>>>>> /*
>>>>> * XXX: TOFIX: some patches have made this code become inconsistent:
>>>>> * there are type inconsistencies, mixing hwaddr, target_ulong
>>>>> @@ -350,8 +345,7 @@ static void sdram_reset(void *opaque)
>>>>> void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
>>>>> MemoryRegion *ram_memories,
>>>>> hwaddr *ram_bases,
>>>>> - hwaddr *ram_sizes,
>>>>> - int do_init)
>>>>> + hwaddr *ram_sizes)
>>>>> {
>>>>> ppc4xx_sdram_t *sdram;
>>>>> int i;
>>>>> @@ -369,9 +363,6 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
>>>>> sdram, &dcr_read_sdram, &dcr_write_sdram);
>>>>> ppc_dcr_register(env, SDRAM0_CFGDATA,
>>>>> sdram, &dcr_read_sdram, &dcr_write_sdram);
>>>>> - if (do_init) {
>>>>> - sdram_map_bcr(sdram);
>>>>> - }
>>>>> }
>>>>> /*
>>>>> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
>>>>> index 2af0d60577..a5e6c185af 100644
>>>>> --- a/include/hw/ppc/ppc4xx.h
>>>>> +++ b/include/hw/ppc/ppc4xx.h
>>>>> @@ -37,6 +37,11 @@ typedef struct {
>>>>> uint32_t bcr;
>>>>> } Ppc4xxSdramBank;
>>>>> +enum {
>>>>> + SDRAM0_CFGADDR = 0x010,
>>>>> + SDRAM0_CFGDATA = 0x011,
>>>>> +};
>>>>> +
>>>>> void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
>>>>> MemoryRegion ram_memories[],
>>>>> hwaddr ram_bases[], hwaddr ram_sizes[],
>>>>> @@ -45,8 +50,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
>>>>> void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
>>>>> MemoryRegion ram_memories[],
>>>>> hwaddr *ram_bases,
>>>>> - hwaddr *ram_sizes,
>>>>> - int do_init);
>>>>> + hwaddr *ram_sizes);
>>>>> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>>>>>
>>>>
>>>>
>>>>
>>
>>
>>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack
2022-09-18 7:34 ` Cédric Le Goater
@ 2022-09-18 21:35 ` BALATON Zoltan
0 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-18 21:35 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 16323 bytes --]
On Sun, 18 Sep 2022, Cédric Le Goater wrote:
> On 9/14/22 20:25, BALATON Zoltan wrote:
>> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>>> On 9/14/22 13:44, BALATON Zoltan wrote:
>>>> On Wed, 14 Sep 2022, Cédric Le Goater wrote:
>>>>> On 9/13/22 21:52, BALATON Zoltan wrote:
>>>>>> The do_init parameter of ppc4xx_sdram_init() is used to map memory
>>>>>> regions that is normally done by the firmware by programming the SDRAM
>>>>>> controller. This is needed when booting a kernel directly from -kernel
>>>>>> without a firmware. Do this from board code accesing normal SDRAM
>>>>>
>>>>> accessing
>>>>
>>>> Fixed, also two ofhers in another patch you haven't noticed.
>>>>
>>>>>> controller registers the same way as firmware would do, so we can get
>>>>>> rid of this hack.
>>>>>>
>>>>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>>>>> ---
>>>>>> v2: Fix ref405ep boot with -kernel and U-Boot
>>>>>>
>>>>>> hw/ppc/ppc405.h | 1 -
>>>>>> hw/ppc/ppc405_boards.c | 12 ++++++++++--
>>>>>> hw/ppc/ppc405_uc.c | 4 +---
>>>>>> hw/ppc/ppc440_bamboo.c | 8 +++++++-
>>>>>> hw/ppc/ppc440_uc.c | 2 --
>>>>>> hw/ppc/ppc4xx_devs.c | 11 +----------
>>>>>> include/hw/ppc/ppc4xx.h | 8 ++++++--
>>>>>> 7 files changed, 25 insertions(+), 21 deletions(-)
>>>>>>
>>>>>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>>>>>> index 1e558c7831..756865621b 100644
>>>>>> --- a/hw/ppc/ppc405.h
>>>>>> +++ b/hw/ppc/ppc405.h
>>>>>> @@ -169,7 +169,6 @@ struct Ppc405SoCState {
>>>>>> /* Public */
>>>>>> MemoryRegion ram_banks[2];
>>>>>> hwaddr ram_bases[2], ram_sizes[2];
>>>>>> - bool do_dram_init;
>>>>>> MemoryRegion *dram_mr;
>>>>>> hwaddr ram_size;
>>>>>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>>>>>> index 083f12b23e..bf02a71c6d 100644
>>>>>> --- a/hw/ppc/ppc405_boards.c
>>>>>> +++ b/hw/ppc/ppc405_boards.c
>>>>>> @@ -274,6 +274,7 @@ static void ppc405_init(MachineState *machine)
>>>>>> MachineClass *mc = MACHINE_GET_CLASS(machine);
>>>>>> const char *kernel_filename = machine->kernel_filename;
>>>>>> MemoryRegion *sysmem = get_system_memory();
>>>>>> + CPUPPCState *env;
>>>>>> if (machine->ram_size != mc->default_ram_size) {
>>>>>> char *sz = size_to_str(mc->default_ram_size);
>>>>>> @@ -288,12 +289,19 @@ static void ppc405_init(MachineState *machine)
>>>>>> machine->ram_size, &error_fatal);
>>>>>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>>>>>> OBJECT(machine->ram), &error_abort);
>>>>>> - object_property_set_bool(OBJECT(&ppc405->soc), "dram-init",
>>>>>> - kernel_filename != NULL, &error_abort);
>>>>>> object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk",
>>>>>> 33333333,
>>>>>> &error_abort);
>>>>>> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
>>>>>> + /* Enable SDRAM memory regions */
>>>>>> + /* FIXME This shouldn't be needed with firmware but we lack SPD
>>>>>> data */
>>>>>
>>>>> what do you mean ?
>>>>
>>>> U-Boot detects the available RAM by reading the SPD info of the RAM
>>>> modules but that probably also needs i2c emulation. See sam460ex.
>>>>
>>>>>> + env = &ppc405->soc.cpu.env;
>>>>>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>>>>>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>>>>>
>>>>>
>>>>> I am not in favor of these ppc_drc_write calls and this is still a hack.
>>>>
>>>> It's not. Normally this is done by firmware to enable memory controller
>>>> but the board code has to do it if not using firmware (e.g. booting with
>>>> -kernel) the same way it provides bootinfo or device tree mods the
>>>> firmware would normally do or in this case maybe the emulation is
>>>> incomplete so the part of firmware that configures the SDRAM controller
>>>> does not run.
>>>
>>> Exactly, and what the above proposal does is mimicking execution of CPU
>>> instructions before the CPU is even fully initiated. Reset has not been
>>> called at that stage.
>>
>> I don't get this. We're not calling any CPU instructions, ppc_dcr_write
>> just calls the write callback the device has registered for the dcr so it
>> just does the same as the hack did at the end just doing it the same way
>> the firmware should do.
>>
>>>>> The "dram-init" property is a cleaner solution. It takes care of doing
>>>>> the
>>>>> pre-mapping of RAM banks in the realize routine of the sdram model (when
>>>>> available).
>>>>
>>>> I disagree, the hardware does not have such feature, it proviesd DCRs as
>>>> the way to configure it. Adding a special property for it deviates from
>>>> hardware and clutters qtree.
>>>
>>>
>>> In this machine, running QEMU with -kernel deviates from HW. That's
>>
>> In all machines booting with -kernel likely deviates and all machines
>> probably have additinal code in this case to do some things normally done
>> by the firmware. Look at pegasos2_machine_reset() for example. All that is
>> not needed when we boot with firmware as then the firmware will do all that
>> and provide the device tree, etc. bur we need to do these when booting
>> without firmware. In thes case QEMU also emulates the firmware and has to
>> do thinigs like enabling the memory controller.
>>
>>> the whole purpose of this option. It assumes that the SDRAM device
>>> is pre-initialized (and much more should be done) by the QEMU machine
>>> and the simplest way to acheive this goal is to inform the SDRAM model
>>> to take care of the pre-initialization.
>>
>> In my opinion the SDRAM controller model should model the hardware and if
>> the board uses it differently then it should take care of that and not
>> change the model.
>>
>>> Another way would be to change the default reset values of the SDRAM
>>> registers (in the realize method using some property) and perform
>>> some actions (mapping the banks) in the reset handler of the SDRAM
>>> device model. That would be a deferred initialization but a property
>>> is still needed to change the default behavior of the SDRAM model.
>>>
>>> Anyhow, this should be isolated under the SDRAM device model and
>>> not in the machine init by using the CPU state. That's clearly ugly.
>>
>> Why? You already have the ppc405_set_bootinfo and all it's stuff in the
>> ppc405 board which is also only needed without firmware.
>
> True. ppc405_set_bootinfo() is mimicking u-boot and updating RAM to pretend
> that FW already ran. It is done from under boot_from_kernel() only.
>
> FYI, The U-boot support was quite a mess :
>
> https://lists.ozlabs.org/pipermail/linuxppc-dev/2009-July/074487.html
>
>> If you're opposed to the few lines enabling the memory controller being in
>> ppc405_init
>
> Well, that's what the init property is doing already. I do understand you
> need to move the code to cleanup the SDRAM model, but there are cleaner
> ways to do so.
>
> Alternative would be to remove the SDRAM pre-init for now, change the
> model and re-add it at the end when all is cleanly modified. The -kernel
> support would be temporarily broken but that's fine.
Doing the init in any other way than through dcr write is bad becuause
then the register values and mapped regions can get out of sync so I don't
like to add any other hack to go around this. The code to enable and
disable the contrller is there at one place and everything should go
through that.
> On that topic, you should probably consider changing the patchset to
> propose first, a new SDRAM model (without using it in the boards) and
> then do the model "switch" at the end. That might be easier to review.
Besides that ir would require me to redo everthing from scratch it would
also be hard to bisect as you ended up with one patch changing everything
and no way to test the individual steps so I don't think this is a good
idea.
>> I could put it in a function either in ppc405_boards.c or if you think this
>> should be in ppc4xx_sdrem.c then we can export that function via
>> include/hw/ppc/ppc4xx.h and call that from boards
>
> Yes. That would be better.
I went with this then in v5...
> Please call from under boot_from_kernel(), something like
>
> sdram_map_bcr(&ppc405->soc.sdram);
...but not quite like this becuase of the above and also because this
function will be gone by the end of the series.
>> but I don't want to add hacks and a property for this in the device model
>> becuase I'm not convinced it belongs there.
>
> That's how the default state of a model is changed and possibly taken
> into account at reset. A bit like HW strapping would work.
>
> Typically, in that case, you could use properties to change the BCR
> reg values and do the mapping accordingly at reset.
I'm not a fan of qdev properties that turn a sysbus_create_simple() into 5
lines of unreadable code and also mess up -device help and info qtree
output. (At least these devices are not used creatable so -device help is
not a problem here.)
>> If the hardware would have such an option then modeling that in is valid
>
> QEMU has all kinds of extensions which makes it much more useful than HW
> in some places. The frontier is not that well draw.
Sure but in this case I think it would not make it more useful and we
could just model the device better without such an addition.
Regards,
BALATON Zoltan
> Thanks,
>
> C.
>
>
>> but if it's done by the firmare on the real hardware then either use the
>> firmware or do it in board code which is then emulating the firmware too.
>>
>> Regards,
>> BALATON Zoltan
>>
>>>
>>> Thanks,
>>>
>>> C.
>>>
>>>
>>>
>>>
>>>
>>>> Doing it like this patch is cleaner IMO.
>>>>
>>>> Regards,
>>>> BALATON Zoltan
>>>>
>>>>>
>>>>> C.
>>>>>
>>>>>> + error_report("Could not enable memory regions");
>>>>>> + exit(1);
>>>>>> + }
>>>>>> +
>>>>>> /* allocate and load BIOS */
>>>>>> if (machine->firmware) {
>>>>>> MemoryRegion *bios = g_new(MemoryRegion, 1);
>>>>>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>>>>>> index 2ca42fdef6..1e02347e57 100644
>>>>>> --- a/hw/ppc/ppc405_uc.c
>>>>>> +++ b/hw/ppc/ppc405_uc.c
>>>>>> @@ -1081,8 +1081,7 @@ static void ppc405_soc_realize(DeviceState *dev,
>>>>>> Error **errp)
>>>>>> s->ram_bases[0], s->ram_sizes[0]);
>>>>>> ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17),
>>>>>> 1,
>>>>>> - s->ram_banks, s->ram_bases, s->ram_sizes,
>>>>>> - s->do_dram_init);
>>>>>> + s->ram_banks, s->ram_bases, s->ram_sizes);
>>>>>> /* External bus controller */
>>>>>> if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu,
>>>>>> errp)) {
>>>>>> @@ -1160,7 +1159,6 @@ static void ppc405_soc_realize(DeviceState *dev,
>>>>>> Error **errp)
>>>>>> static Property ppc405_soc_properties[] = {
>>>>>> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr,
>>>>>> TYPE_MEMORY_REGION,
>>>>>> MemoryRegion *),
>>>>>> - DEFINE_PROP_BOOL("dram-init", Ppc405SoCState, do_dram_init, 0),
>>>>>> DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
>>>>>> DEFINE_PROP_END_OF_LIST(),
>>>>>> };
>>>>>> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
>>>>>> index 5ec82fa8c2..e3412c4fcd 100644
>>>>>> --- a/hw/ppc/ppc440_bamboo.c
>>>>>> +++ b/hw/ppc/ppc440_bamboo.c
>>>>>> @@ -211,7 +211,13 @@ static void bamboo_init(MachineState *machine)
>>>>>> ppc4xx_sdram_init(env,
>>>>>> qdev_get_gpio_in(uicdev, 14),
>>>>>> PPC440EP_SDRAM_NR_BANKS, ram_memories,
>>>>>> - ram_bases, ram_sizes, 1);
>>>>>> + ram_bases, ram_sizes);
>>>>>> + /* Enable SDRAM memory regions, this should be done by the
>>>>>> firmware */
>>>>>> + if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>>>>>> + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>>>>>> + error_report("couldn't enable memory regions");
>>>>>> + exit(1);
>>>>>> + }
>>>>>> /* PCI */
>>>>>> dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
>>>>>> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
>>>>>> index db33334e29..6ab0ad7985 100644
>>>>>> --- a/hw/ppc/ppc440_uc.c
>>>>>> +++ b/hw/ppc/ppc440_uc.c
>>>>>> @@ -489,8 +489,6 @@ typedef struct ppc440_sdram_t {
>>>>>> } ppc440_sdram_t;
>>>>>> enum {
>>>>>> - SDRAM0_CFGADDR = 0x10,
>>>>>> - SDRAM0_CFGDATA,
>>>>>> SDRAM_R0BAS = 0x40,
>>>>>> SDRAM_R1BAS,
>>>>>> SDRAM_R2BAS,
>>>>>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>>>>>> index 1226ec4aa9..936d6f77fe 100644
>>>>>> --- a/hw/ppc/ppc4xx_devs.c
>>>>>> +++ b/hw/ppc/ppc4xx_devs.c
>>>>>> @@ -56,11 +56,6 @@ struct ppc4xx_sdram_t {
>>>>>> qemu_irq irq;
>>>>>> };
>>>>>> -enum {
>>>>>> - SDRAM0_CFGADDR = 0x010,
>>>>>> - SDRAM0_CFGDATA = 0x011,
>>>>>> -};
>>>>>> -
>>>>>> /*
>>>>>> * XXX: TOFIX: some patches have made this code become inconsistent:
>>>>>> * there are type inconsistencies, mixing hwaddr, target_ulong
>>>>>> @@ -350,8 +345,7 @@ static void sdram_reset(void *opaque)
>>>>>> void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
>>>>>> MemoryRegion *ram_memories,
>>>>>> hwaddr *ram_bases,
>>>>>> - hwaddr *ram_sizes,
>>>>>> - int do_init)
>>>>>> + hwaddr *ram_sizes)
>>>>>> {
>>>>>> ppc4xx_sdram_t *sdram;
>>>>>> int i;
>>>>>> @@ -369,9 +363,6 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq
>>>>>> irq, int nbanks,
>>>>>> sdram, &dcr_read_sdram, &dcr_write_sdram);
>>>>>> ppc_dcr_register(env, SDRAM0_CFGDATA,
>>>>>> sdram, &dcr_read_sdram, &dcr_write_sdram);
>>>>>> - if (do_init) {
>>>>>> - sdram_map_bcr(sdram);
>>>>>> - }
>>>>>> }
>>>>>> /*
>>>>>> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
>>>>>> index 2af0d60577..a5e6c185af 100644
>>>>>> --- a/include/hw/ppc/ppc4xx.h
>>>>>> +++ b/include/hw/ppc/ppc4xx.h
>>>>>> @@ -37,6 +37,11 @@ typedef struct {
>>>>>> uint32_t bcr;
>>>>>> } Ppc4xxSdramBank;
>>>>>> +enum {
>>>>>> + SDRAM0_CFGADDR = 0x010,
>>>>>> + SDRAM0_CFGDATA = 0x011,
>>>>>> +};
>>>>>> +
>>>>>> void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
>>>>>> MemoryRegion ram_memories[],
>>>>>> hwaddr ram_bases[], hwaddr ram_sizes[],
>>>>>> @@ -45,8 +50,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int
>>>>>> nr_banks,
>>>>>> void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
>>>>>> MemoryRegion ram_memories[],
>>>>>> hwaddr *ram_bases,
>>>>>> - hwaddr *ram_sizes,
>>>>>> - int do_init);
>>>>>> + hwaddr *ram_sizes);
>>>>>> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>>>>>>
>>>>>
>>>>>
>>>>>
>>>
>>>
>>>
>
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v3 04/20] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (2 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 03/20] ppc4xx_sdram: Get rid of the init RAM hack BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-14 6:58 ` Cédric Le Goater
2022-09-13 19:52 ` [PATCH v3 05/20] ppc440_bamboo: Add missing 4 MiB valid memory size BALATON Zoltan
` (16 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead
of the separate arrays and adjust ppc4xx_sdram_init() and
ppc440_sdram_init() accordingly as well as machines using these.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
v2: Use pointer for ram_banks in the prototype of the init funcs as
an array of struct seems to confuse gcc 12.2.1 and provoke a warning
hw/ppc/ppc405.h | 4 +---
hw/ppc/ppc405_uc.c | 10 +++++-----
hw/ppc/ppc440.h | 5 ++---
hw/ppc/ppc440_bamboo.c | 15 ++++++---------
hw/ppc/ppc440_uc.c | 9 ++++-----
hw/ppc/ppc4xx_devs.c | 21 +++++++++------------
hw/ppc/sam460ex.c | 15 +++++----------
include/hw/ppc/ppc4xx.h | 9 +++------
8 files changed, 35 insertions(+), 53 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 756865621b..ca0972b88b 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -167,9 +167,7 @@ struct Ppc405SoCState {
DeviceState parent_obj;
/* Public */
- MemoryRegion ram_banks[2];
- hwaddr ram_bases[2], ram_sizes[2];
-
+ Ppc4xxSdramBank ram_banks[2];
MemoryRegion *dram_mr;
hwaddr ram_size;
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 1e02347e57..bcbf35bc14 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1074,14 +1074,14 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
- s->ram_bases[0] = 0;
- s->ram_sizes[0] = s->ram_size;
- memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
+ s->ram_banks[0].base = 0;
+ s->ram_banks[0].size = s->ram_size;
+ memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s),
"ppc405.sdram0", s->dram_mr,
- s->ram_bases[0], s->ram_sizes[0]);
+ s->ram_banks[0].base, s->ram_banks[0].size);
ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->ram_banks, s->ram_bases, s->ram_sizes);
+ s->ram_banks);
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index 7cef936125..e6c905b7d6 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -11,14 +11,13 @@
#ifndef PPC440_H
#define PPC440_H
-#include "hw/ppc/ppc.h"
+#include "hw/ppc/ppc4xx.h"
void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram_memories,
- hwaddr *ram_bases, hwaddr *ram_sizes,
+ Ppc4xxSdramBank *ram_banks,
int do_init);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index e3412c4fcd..2aac8a3fe9 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -168,9 +168,8 @@ static void bamboo_init(MachineState *machine)
unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
- MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
- hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS] = {0};
- hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS] = {0};
+ Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank,
+ PPC440EP_SDRAM_NR_BANKS);
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
@@ -205,13 +204,11 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
- ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
+ ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks,
+ ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
- ppc4xx_sdram_init(env,
- qdev_get_gpio_in(uicdev, 14),
- PPC440EP_SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes);
+ ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
+ PPC440EP_SDRAM_NR_BANKS, ram_banks);
/* Enable SDRAM memory regions, this should be done by the firmware */
if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 6ab0ad7985..5db59d1190 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -690,8 +690,7 @@ static void sdram_reset(void *opaque)
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram_memories,
- hwaddr *ram_bases, hwaddr *ram_sizes,
+ Ppc4xxSdramBank *ram_banks,
int do_init)
{
ppc440_sdram_t *sdram;
@@ -700,9 +699,9 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
sdram = g_malloc0(sizeof(*sdram));
sdram->nbanks = nbanks;
for (i = 0; i < nbanks; i++) {
- sdram->bank[i].ram = ram_memories[i];
- sdram->bank[i].base = ram_bases[i];
- sdram->bank[i].size = ram_sizes[i];
+ sdram->bank[i].ram = ram_banks[i].ram;
+ sdram->bank[i].base = ram_banks[i].base;
+ sdram->bank[i].size = ram_banks[i].size;
}
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 936d6f77fe..7bdcbd6fac 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -343,9 +343,7 @@ static void sdram_reset(void *opaque)
}
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- MemoryRegion *ram_memories,
- hwaddr *ram_bases,
- hwaddr *ram_sizes)
+ Ppc4xxSdramBank *ram_banks)
{
ppc4xx_sdram_t *sdram;
int i;
@@ -354,9 +352,9 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
sdram->irq = irq;
sdram->nbanks = nbanks;
for (i = 0; i < nbanks; i++) {
- sdram->bank[i].ram = ram_memories[i];
- sdram->bank[i].base = ram_bases[i];
- sdram->bank[i].size = ram_sizes[i];
+ sdram->bank[i].ram = ram_banks[i].ram;
+ sdram->bank[i].base = ram_banks[i].base;
+ sdram->bank[i].size = ram_banks[i].size;
}
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
@@ -376,8 +374,7 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
* sizes varies by SoC.
*/
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
- MemoryRegion ram_memories[],
- hwaddr ram_bases[], hwaddr ram_sizes[],
+ Ppc4xxSdramBank ram_banks[],
const ram_addr_t sdram_bank_sizes[])
{
ram_addr_t size_left = memory_region_size(ram);
@@ -392,13 +389,13 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
if (bank_size <= size_left) {
char name[32];
- ram_bases[i] = base;
- ram_sizes[i] = bank_size;
+ ram_banks[i].base = base;
+ ram_banks[i].size = bank_size;
base += bank_size;
size_left -= bank_size;
snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
- memory_region_init_alias(&ram_memories[i], NULL, name, ram,
- ram_bases[i], ram_sizes[i]);
+ memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram,
+ ram_banks[i].base, ram_banks[i].size);
break;
}
}
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 850bb3b817..f4c2a693fb 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -73,7 +73,6 @@
#define OPB_FREQ 115000000
#define EBC_FREQ 115000000
#define UART_FREQ 11059200
-#define SDRAM_NR_BANKS 4
/* The SoC could also handle 4 GiB but firmware does not work with that. */
/* Maybe it overflows a signed 32 bit number somewhere? */
@@ -274,9 +273,7 @@ static void sam460ex_init(MachineState *machine)
{
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
- MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS);
- hwaddr ram_bases[SDRAM_NR_BANKS] = {0};
- hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
+ Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank, 1);
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
DeviceState *uic[4];
int i;
@@ -345,20 +342,18 @@ static void sam460ex_init(MachineState *machine)
/* SDRAM controller */
/* put all RAM on first bank because board has one slot
* and firmware only checks that */
- ppc4xx_sdram_banks(machine->ram, 1, ram_memories, ram_bases, ram_sizes,
- ppc460ex_sdram_bank_sizes);
+ ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes);
/* FIXME: does 460EX have ECC interrupts? */
- ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
- ram_bases, ram_sizes, 1);
+ ppc440_sdram_init(env, 1, ram_banks, 1);
/* IIC controllers and devices */
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
qdev_get_gpio_in(uic[0], 2));
i2c = PPC4xx_I2C(dev)->bus;
/* SPD EEPROM on RAM module */
- spd_data = spd_data_generate(ram_sizes[0] < 128 * MiB ? DDR : DDR2,
- ram_sizes[0]);
+ spd_data = spd_data_generate(ram_banks->size < 128 * MiB ? DDR : DDR2,
+ ram_banks->size);
spd_data[20] = 4; /* SO-DIMM module */
smbus_eeprom_init_one(i2c, 0x50, spd_data);
/* RTC */
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index a5e6c185af..5013b8bf3a 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -43,14 +43,11 @@ enum {
};
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
- MemoryRegion ram_memories[],
- hwaddr ram_bases[], hwaddr ram_sizes[],
+ Ppc4xxSdramBank ram_banks[],
const ram_addr_t sdram_bank_sizes[]);
-void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
- MemoryRegion ram_memories[],
- hwaddr *ram_bases,
- hwaddr *ram_sizes);
+void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
+ Ppc4xxSdramBank *ram_banks);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v3 04/20] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()
2022-09-13 19:52 ` [PATCH v3 04/20] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks() BALATON Zoltan
@ 2022-09-14 6:58 ` Cédric Le Goater
0 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-09-14 6:58 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 9/13/22 21:52, BALATON Zoltan wrote:
> Change ppc4xx_sdram_banks() to take one Ppc4xxSdramBank array instead
> of the separate arrays and adjust ppc4xx_sdram_init() and
> ppc440_sdram_init() accordingly as well as machines using these.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> v2: Use pointer for ram_banks in the prototype of the init funcs as
> an array of struct seems to confuse gcc 12.2.1 and provoke a warning
>
> hw/ppc/ppc405.h | 4 +---
> hw/ppc/ppc405_uc.c | 10 +++++-----
> hw/ppc/ppc440.h | 5 ++---
> hw/ppc/ppc440_bamboo.c | 15 ++++++---------
> hw/ppc/ppc440_uc.c | 9 ++++-----
> hw/ppc/ppc4xx_devs.c | 21 +++++++++------------
> hw/ppc/sam460ex.c | 15 +++++----------
> include/hw/ppc/ppc4xx.h | 9 +++------
> 8 files changed, 35 insertions(+), 53 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index 756865621b..ca0972b88b 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -167,9 +167,7 @@ struct Ppc405SoCState {
> DeviceState parent_obj;
>
> /* Public */
> - MemoryRegion ram_banks[2];
> - hwaddr ram_bases[2], ram_sizes[2];
> -
> + Ppc4xxSdramBank ram_banks[2];
> MemoryRegion *dram_mr;
> hwaddr ram_size;
>
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 1e02347e57..bcbf35bc14 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1074,14 +1074,14 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>
> /* SDRAM controller */
> /* XXX 405EP has no ECC interrupt */
> - s->ram_bases[0] = 0;
> - s->ram_sizes[0] = s->ram_size;
> - memory_region_init_alias(&s->ram_banks[0], OBJECT(s),
> + s->ram_banks[0].base = 0;
> + s->ram_banks[0].size = s->ram_size;
> + memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s),
> "ppc405.sdram0", s->dram_mr,
> - s->ram_bases[0], s->ram_sizes[0]);
> + s->ram_banks[0].base, s->ram_banks[0].size);
>
> ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
> - s->ram_banks, s->ram_bases, s->ram_sizes);
> + s->ram_banks);
>
> /* External bus controller */
> if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
> diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
> index 7cef936125..e6c905b7d6 100644
> --- a/hw/ppc/ppc440.h
> +++ b/hw/ppc/ppc440.h
> @@ -11,14 +11,13 @@
> #ifndef PPC440_H
> #define PPC440_H
>
> -#include "hw/ppc/ppc.h"
> +#include "hw/ppc/ppc4xx.h"
>
> void ppc4xx_l2sram_init(CPUPPCState *env);
> void ppc4xx_cpr_init(CPUPPCState *env);
> void ppc4xx_sdr_init(CPUPPCState *env);
> void ppc440_sdram_init(CPUPPCState *env, int nbanks,
> - MemoryRegion *ram_memories,
> - hwaddr *ram_bases, hwaddr *ram_sizes,
> + Ppc4xxSdramBank *ram_banks,
> int do_init);
> void ppc4xx_ahb_init(CPUPPCState *env);
> void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
> index e3412c4fcd..2aac8a3fe9 100644
> --- a/hw/ppc/ppc440_bamboo.c
> +++ b/hw/ppc/ppc440_bamboo.c
> @@ -168,9 +168,8 @@ static void bamboo_init(MachineState *machine)
> unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
> MemoryRegion *address_space_mem = get_system_memory();
> MemoryRegion *isa = g_new(MemoryRegion, 1);
> - MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
> - hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS] = {0};
> - hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS] = {0};
> + Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank,
> + PPC440EP_SDRAM_NR_BANKS);
> PCIBus *pcibus;
> PowerPCCPU *cpu;
> CPUPPCState *env;
> @@ -205,13 +204,11 @@ static void bamboo_init(MachineState *machine)
> qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
>
> /* SDRAM controller */
> - ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
> - ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
> + ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks,
> + ppc440ep_sdram_bank_sizes);
> /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
> - ppc4xx_sdram_init(env,
> - qdev_get_gpio_in(uicdev, 14),
> - PPC440EP_SDRAM_NR_BANKS, ram_memories,
> - ram_bases, ram_sizes);
> + ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
> + PPC440EP_SDRAM_NR_BANKS, ram_banks);
> /* Enable SDRAM memory regions, this should be done by the firmware */
> if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
> ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
> index 6ab0ad7985..5db59d1190 100644
> --- a/hw/ppc/ppc440_uc.c
> +++ b/hw/ppc/ppc440_uc.c
> @@ -690,8 +690,7 @@ static void sdram_reset(void *opaque)
> }
>
> void ppc440_sdram_init(CPUPPCState *env, int nbanks,
> - MemoryRegion *ram_memories,
> - hwaddr *ram_bases, hwaddr *ram_sizes,
> + Ppc4xxSdramBank *ram_banks,
> int do_init)
> {
> ppc440_sdram_t *sdram;
> @@ -700,9 +699,9 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
> sdram = g_malloc0(sizeof(*sdram));
> sdram->nbanks = nbanks;
> for (i = 0; i < nbanks; i++) {
> - sdram->bank[i].ram = ram_memories[i];
> - sdram->bank[i].base = ram_bases[i];
> - sdram->bank[i].size = ram_sizes[i];
> + sdram->bank[i].ram = ram_banks[i].ram;
> + sdram->bank[i].base = ram_banks[i].base;
> + sdram->bank[i].size = ram_banks[i].size;
> }
> qemu_register_reset(&sdram_reset, sdram);
> ppc_dcr_register(env, SDRAM0_CFGADDR,
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index 936d6f77fe..7bdcbd6fac 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -343,9 +343,7 @@ static void sdram_reset(void *opaque)
> }
>
> void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
> - MemoryRegion *ram_memories,
> - hwaddr *ram_bases,
> - hwaddr *ram_sizes)
> + Ppc4xxSdramBank *ram_banks)
> {
> ppc4xx_sdram_t *sdram;
> int i;
> @@ -354,9 +352,9 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
> sdram->irq = irq;
> sdram->nbanks = nbanks;
> for (i = 0; i < nbanks; i++) {
> - sdram->bank[i].ram = ram_memories[i];
> - sdram->bank[i].base = ram_bases[i];
> - sdram->bank[i].size = ram_sizes[i];
> + sdram->bank[i].ram = ram_banks[i].ram;
> + sdram->bank[i].base = ram_banks[i].base;
> + sdram->bank[i].size = ram_banks[i].size;
> }
> qemu_register_reset(&sdram_reset, sdram);
> ppc_dcr_register(env, SDRAM0_CFGADDR,
> @@ -376,8 +374,7 @@ void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
> * sizes varies by SoC.
> */
> void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
> - MemoryRegion ram_memories[],
> - hwaddr ram_bases[], hwaddr ram_sizes[],
> + Ppc4xxSdramBank ram_banks[],
> const ram_addr_t sdram_bank_sizes[])
> {
> ram_addr_t size_left = memory_region_size(ram);
> @@ -392,13 +389,13 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
> if (bank_size <= size_left) {
> char name[32];
>
> - ram_bases[i] = base;
> - ram_sizes[i] = bank_size;
> + ram_banks[i].base = base;
> + ram_banks[i].size = bank_size;
> base += bank_size;
> size_left -= bank_size;
> snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
> - memory_region_init_alias(&ram_memories[i], NULL, name, ram,
> - ram_bases[i], ram_sizes[i]);
> + memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram,
> + ram_banks[i].base, ram_banks[i].size);
> break;
> }
> }
> diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
> index 850bb3b817..f4c2a693fb 100644
> --- a/hw/ppc/sam460ex.c
> +++ b/hw/ppc/sam460ex.c
> @@ -73,7 +73,6 @@
> #define OPB_FREQ 115000000
> #define EBC_FREQ 115000000
> #define UART_FREQ 11059200
> -#define SDRAM_NR_BANKS 4
>
> /* The SoC could also handle 4 GiB but firmware does not work with that. */
> /* Maybe it overflows a signed 32 bit number somewhere? */
> @@ -274,9 +273,7 @@ static void sam460ex_init(MachineState *machine)
> {
> MemoryRegion *address_space_mem = get_system_memory();
> MemoryRegion *isa = g_new(MemoryRegion, 1);
> - MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS);
> - hwaddr ram_bases[SDRAM_NR_BANKS] = {0};
> - hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
> + Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank, 1);
> MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
> DeviceState *uic[4];
> int i;
> @@ -345,20 +342,18 @@ static void sam460ex_init(MachineState *machine)
> /* SDRAM controller */
> /* put all RAM on first bank because board has one slot
> * and firmware only checks that */
> - ppc4xx_sdram_banks(machine->ram, 1, ram_memories, ram_bases, ram_sizes,
> - ppc460ex_sdram_bank_sizes);
> + ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes);
>
> /* FIXME: does 460EX have ECC interrupts? */
> - ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
> - ram_bases, ram_sizes, 1);
> + ppc440_sdram_init(env, 1, ram_banks, 1);
>
> /* IIC controllers and devices */
> dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
> qdev_get_gpio_in(uic[0], 2));
> i2c = PPC4xx_I2C(dev)->bus;
> /* SPD EEPROM on RAM module */
> - spd_data = spd_data_generate(ram_sizes[0] < 128 * MiB ? DDR : DDR2,
> - ram_sizes[0]);
> + spd_data = spd_data_generate(ram_banks->size < 128 * MiB ? DDR : DDR2,
> + ram_banks->size);
> spd_data[20] = 4; /* SO-DIMM module */
> smbus_eeprom_init_one(i2c, 0x50, spd_data);
> /* RTC */
> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
> index a5e6c185af..5013b8bf3a 100644
> --- a/include/hw/ppc/ppc4xx.h
> +++ b/include/hw/ppc/ppc4xx.h
> @@ -43,14 +43,11 @@ enum {
> };
>
> void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
> - MemoryRegion ram_memories[],
> - hwaddr ram_bases[], hwaddr ram_sizes[],
> + Ppc4xxSdramBank ram_banks[],
> const ram_addr_t sdram_bank_sizes[]);
>
> -void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
> - MemoryRegion ram_memories[],
> - hwaddr *ram_bases,
> - hwaddr *ram_sizes);
> +void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
> + Ppc4xxSdramBank *ram_banks);
>
> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v3 05/20] ppc440_bamboo: Add missing 4 MiB valid memory size
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (3 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 04/20] ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks() BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 06/20] ppc4xx_sdram: Move size check to ppc4xx_sdram_init() BALATON Zoltan
` (15 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc440_bamboo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 2aac8a3fe9..2bd5e41140 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -51,7 +51,7 @@
#define PPC440EP_SDRAM_NR_BANKS 4
static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
- 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
+ 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
};
static hwaddr entry;
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v3 06/20] ppc4xx_sdram: Move size check to ppc4xx_sdram_init()
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (4 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 05/20] ppc440_bamboo: Add missing 4 MiB valid memory size BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-14 7:09 ` Cédric Le Goater
2022-09-13 19:52 ` [PATCH v3 07/20] ppc4xx_sdram: QOM'ify BALATON Zoltan
` (14 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Instead of checking if memory size is valid in board code move this
check to ppc4xx_sdram_init() as this is a restriction imposed by the
SDRAM controller.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc405.h | 2 --
hw/ppc/ppc405_boards.c | 10 ----------
hw/ppc/ppc405_uc.c | 11 ++---------
hw/ppc/ppc440_bamboo.c | 10 +---------
hw/ppc/ppc4xx_devs.c | 14 ++++++--------
include/hw/ppc/ppc4xx.h | 2 +-
6 files changed, 10 insertions(+), 39 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ca0972b88b..ad54dff542 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -167,9 +167,7 @@ struct Ppc405SoCState {
DeviceState parent_obj;
/* Public */
- Ppc4xxSdramBank ram_banks[2];
MemoryRegion *dram_mr;
- hwaddr ram_size;
PowerPCCPU cpu;
PPCUIC uic;
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index bf02a71c6d..cdd4e0cb4c 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -271,22 +271,12 @@ static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
static void ppc405_init(MachineState *machine)
{
Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
- MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
MemoryRegion *sysmem = get_system_memory();
CPUPPCState *env;
- if (machine->ram_size != mc->default_ram_size) {
- char *sz = size_to_str(mc->default_ram_size);
- error_report("Invalid RAM size, should be %s", sz);
- g_free(sz);
- exit(EXIT_FAILURE);
- }
-
object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
TYPE_PPC405_SOC);
- object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
- machine->ram_size, &error_fatal);
object_property_set_link(OBJECT(&ppc405->soc), "dram",
OBJECT(machine->ram), &error_abort);
object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index bcbf35bc14..e1c7188e61 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1073,15 +1073,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
- /* XXX 405EP has no ECC interrupt */
- s->ram_banks[0].base = 0;
- s->ram_banks[0].size = s->ram_size;
- memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s),
- "ppc405.sdram0", s->dram_mr,
- s->ram_banks[0].base, s->ram_banks[0].size);
-
+ /* XXX 405EP has no ECC interrupt */
ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->ram_banks);
+ s->dram_mr);
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
@@ -1159,7 +1153,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
static Property ppc405_soc_properties[] = {
DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
MemoryRegion *),
- DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 2bd5e41140..9b456f1819 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -50,10 +50,6 @@
#define PPC440EP_SDRAM_NR_BANKS 4
-static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
- 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
-};
-
static hwaddr entry;
static int bamboo_load_device_tree(hwaddr addr,
@@ -168,8 +164,6 @@ static void bamboo_init(MachineState *machine)
unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
- Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank,
- PPC440EP_SDRAM_NR_BANKS);
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
@@ -204,11 +198,9 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
- ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks,
- ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
- PPC440EP_SDRAM_NR_BANKS, ram_banks);
+ PPC440EP_SDRAM_NR_BANKS, machine->ram);
/* Enable SDRAM memory regions, this should be done by the firmware */
if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 7bdcbd6fac..eb3aa97b16 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -41,7 +41,7 @@
typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
struct ppc4xx_sdram_t {
uint32_t addr;
- int nbanks;
+ int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
Ppc4xxSdramBank bank[4];
uint32_t besr0;
uint32_t besr1;
@@ -343,19 +343,17 @@ static void sdram_reset(void *opaque)
}
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- Ppc4xxSdramBank *ram_banks)
+ MemoryRegion *ram)
{
ppc4xx_sdram_t *sdram;
- int i;
+ const ram_addr_t valid_bank_sizes[] = {
+ 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
+ };
sdram = g_new0(ppc4xx_sdram_t, 1);
sdram->irq = irq;
sdram->nbanks = nbanks;
- for (i = 0; i < nbanks; i++) {
- sdram->bank[i].ram = ram_banks[i].ram;
- sdram->bank[i].base = ram_banks[i].base;
- sdram->bank[i].size = ram_banks[i].size;
- }
+ ppc4xx_sdram_banks(ram, sdram->nbanks, sdram->bank, valid_bank_sizes);
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 5013b8bf3a..6007a8dd04 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -47,7 +47,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
const ram_addr_t sdram_bank_sizes[]);
void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- Ppc4xxSdramBank *ram_banks);
+ MemoryRegion *ram);
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v3 06/20] ppc4xx_sdram: Move size check to ppc4xx_sdram_init()
2022-09-13 19:52 ` [PATCH v3 06/20] ppc4xx_sdram: Move size check to ppc4xx_sdram_init() BALATON Zoltan
@ 2022-09-14 7:09 ` Cédric Le Goater
2022-09-14 11:37 ` BALATON Zoltan
0 siblings, 1 reply; 41+ messages in thread
From: Cédric Le Goater @ 2022-09-14 7:09 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 9/13/22 21:52, BALATON Zoltan wrote:
> Instead of checking if memory size is valid in board code move this
> check to ppc4xx_sdram_init() as this is a restriction imposed by the
> SDRAM controller.
So, we are relying on ppc4xx_sdram_banks() to check the RAM size
and report the error. The problem is the exit.
You also need to change the prototypes of some routine to take an
"Error **errp" parameter as realize routines do.
qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc4xx_sdram_init()
ppc4xx_sdram_banks()
at least, ppc4xx_sdram_banks() should be changed. The next patch
doing the QOMification takes care of ppc4xx_sdram_init()
Thanks,
C.
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/ppc405.h | 2 --
> hw/ppc/ppc405_boards.c | 10 ----------
> hw/ppc/ppc405_uc.c | 11 ++---------
> hw/ppc/ppc440_bamboo.c | 10 +---------
> hw/ppc/ppc4xx_devs.c | 14 ++++++--------
> include/hw/ppc/ppc4xx.h | 2 +-
> 6 files changed, 10 insertions(+), 39 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index ca0972b88b..ad54dff542 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -167,9 +167,7 @@ struct Ppc405SoCState {
> DeviceState parent_obj;
>
> /* Public */
> - Ppc4xxSdramBank ram_banks[2];
> MemoryRegion *dram_mr;
> - hwaddr ram_size;
>
> PowerPCCPU cpu;
> PPCUIC uic;
> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
> index bf02a71c6d..cdd4e0cb4c 100644
> --- a/hw/ppc/ppc405_boards.c
> +++ b/hw/ppc/ppc405_boards.c
> @@ -271,22 +271,12 @@ static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
> static void ppc405_init(MachineState *machine)
> {
> Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
> - MachineClass *mc = MACHINE_GET_CLASS(machine);
> const char *kernel_filename = machine->kernel_filename;
> MemoryRegion *sysmem = get_system_memory();
> CPUPPCState *env;
>
> - if (machine->ram_size != mc->default_ram_size) {
> - char *sz = size_to_str(mc->default_ram_size);
> - error_report("Invalid RAM size, should be %s", sz);
> - g_free(sz);
> - exit(EXIT_FAILURE);
> - }
> -
> object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
> TYPE_PPC405_SOC);
> - object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
> - machine->ram_size, &error_fatal);
> object_property_set_link(OBJECT(&ppc405->soc), "dram",
> OBJECT(machine->ram), &error_abort);
> object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index bcbf35bc14..e1c7188e61 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1073,15 +1073,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
>
> /* SDRAM controller */
> - /* XXX 405EP has no ECC interrupt */
> - s->ram_banks[0].base = 0;
> - s->ram_banks[0].size = s->ram_size;
> - memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s),
> - "ppc405.sdram0", s->dram_mr,
> - s->ram_banks[0].base, s->ram_banks[0].size);
> -
> + /* XXX 405EP has no ECC interrupt */
> ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
> - s->ram_banks);
> + s->dram_mr);
>
> /* External bus controller */
> if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
> @@ -1159,7 +1153,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> static Property ppc405_soc_properties[] = {
> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
> MemoryRegion *),
> - DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
> index 2bd5e41140..9b456f1819 100644
> --- a/hw/ppc/ppc440_bamboo.c
> +++ b/hw/ppc/ppc440_bamboo.c
> @@ -50,10 +50,6 @@
>
> #define PPC440EP_SDRAM_NR_BANKS 4
>
> -static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
> - 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
> -};
> -
> static hwaddr entry;
>
> static int bamboo_load_device_tree(hwaddr addr,
> @@ -168,8 +164,6 @@ static void bamboo_init(MachineState *machine)
> unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
> MemoryRegion *address_space_mem = get_system_memory();
> MemoryRegion *isa = g_new(MemoryRegion, 1);
> - Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank,
> - PPC440EP_SDRAM_NR_BANKS);
> PCIBus *pcibus;
> PowerPCCPU *cpu;
> CPUPPCState *env;
> @@ -204,11 +198,9 @@ static void bamboo_init(MachineState *machine)
> qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
>
> /* SDRAM controller */
> - ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks,
> - ppc440ep_sdram_bank_sizes);
> /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
> ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
> - PPC440EP_SDRAM_NR_BANKS, ram_banks);
> + PPC440EP_SDRAM_NR_BANKS, machine->ram);
> /* Enable SDRAM memory regions, this should be done by the firmware */
> if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
> ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index 7bdcbd6fac..eb3aa97b16 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -41,7 +41,7 @@
> typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
> struct ppc4xx_sdram_t {
> uint32_t addr;
> - int nbanks;
> + int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
> Ppc4xxSdramBank bank[4];
> uint32_t besr0;
> uint32_t besr1;
> @@ -343,19 +343,17 @@ static void sdram_reset(void *opaque)
> }
>
> void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
> - Ppc4xxSdramBank *ram_banks)
> + MemoryRegion *ram)
> {
> ppc4xx_sdram_t *sdram;
> - int i;
> + const ram_addr_t valid_bank_sizes[] = {
> + 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
> + };
>
> sdram = g_new0(ppc4xx_sdram_t, 1);
> sdram->irq = irq;
> sdram->nbanks = nbanks;
> - for (i = 0; i < nbanks; i++) {
> - sdram->bank[i].ram = ram_banks[i].ram;
> - sdram->bank[i].base = ram_banks[i].base;
> - sdram->bank[i].size = ram_banks[i].size;
> - }
> + ppc4xx_sdram_banks(ram, sdram->nbanks, sdram->bank, valid_bank_sizes);
> qemu_register_reset(&sdram_reset, sdram);
> ppc_dcr_register(env, SDRAM0_CFGADDR,
> sdram, &dcr_read_sdram, &dcr_write_sdram);
> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
> index 5013b8bf3a..6007a8dd04 100644
> --- a/include/hw/ppc/ppc4xx.h
> +++ b/include/hw/ppc/ppc4xx.h
> @@ -47,7 +47,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
> const ram_addr_t sdram_bank_sizes[]);
>
> void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
> - Ppc4xxSdramBank *ram_banks);
> + MemoryRegion *ram);
>
> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v3 06/20] ppc4xx_sdram: Move size check to ppc4xx_sdram_init()
2022-09-14 7:09 ` Cédric Le Goater
@ 2022-09-14 11:37 ` BALATON Zoltan
0 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-14 11:37 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 8343 bytes --]
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
> On 9/13/22 21:52, BALATON Zoltan wrote:
>> Instead of checking if memory size is valid in board code move this
>> check to ppc4xx_sdram_init() as this is a restriction imposed by the
>> SDRAM controller.
>
>
> So, we are relying on ppc4xx_sdram_banks() to check the RAM size
> and report the error. The problem is the exit.
>
> You also need to change the prototypes of some routine to take an
> "Error **errp" parameter as realize routines do.
>
> qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
> ppc405_soc_realize(DeviceState *dev, Error **errp)
> ppc4xx_sdram_init()
> ppc4xx_sdram_banks()
>
> at least, ppc4xx_sdram_banks() should be changed. The next patch
> doing the QOMification takes care of ppc4xx_sdram_init()
I thought about changing ppc4xx_sdram_banks to use Error but did not do it
first because of how the message is formatted. I had to look up docs on
how to do this with Error, added a patch in v4 to do this conversion.
Regards,
BALATON Zoltan
> Thanks,
>
> C.
>
>
>
>
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> hw/ppc/ppc405.h | 2 --
>> hw/ppc/ppc405_boards.c | 10 ----------
>> hw/ppc/ppc405_uc.c | 11 ++---------
>> hw/ppc/ppc440_bamboo.c | 10 +---------
>> hw/ppc/ppc4xx_devs.c | 14 ++++++--------
>> include/hw/ppc/ppc4xx.h | 2 +-
>> 6 files changed, 10 insertions(+), 39 deletions(-)
>>
>> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
>> index ca0972b88b..ad54dff542 100644
>> --- a/hw/ppc/ppc405.h
>> +++ b/hw/ppc/ppc405.h
>> @@ -167,9 +167,7 @@ struct Ppc405SoCState {
>> DeviceState parent_obj;
>> /* Public */
>> - Ppc4xxSdramBank ram_banks[2];
>> MemoryRegion *dram_mr;
>> - hwaddr ram_size;
>> PowerPCCPU cpu;
>> PPCUIC uic;
>> diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
>> index bf02a71c6d..cdd4e0cb4c 100644
>> --- a/hw/ppc/ppc405_boards.c
>> +++ b/hw/ppc/ppc405_boards.c
>> @@ -271,22 +271,12 @@ static void boot_from_kernel(MachineState *machine,
>> PowerPCCPU *cpu)
>> static void ppc405_init(MachineState *machine)
>> {
>> Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
>> - MachineClass *mc = MACHINE_GET_CLASS(machine);
>> const char *kernel_filename = machine->kernel_filename;
>> MemoryRegion *sysmem = get_system_memory();
>> CPUPPCState *env;
>> - if (machine->ram_size != mc->default_ram_size) {
>> - char *sz = size_to_str(mc->default_ram_size);
>> - error_report("Invalid RAM size, should be %s", sz);
>> - g_free(sz);
>> - exit(EXIT_FAILURE);
>> - }
>> -
>> object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
>> TYPE_PPC405_SOC);
>> - object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
>> - machine->ram_size, &error_fatal);
>> object_property_set_link(OBJECT(&ppc405->soc), "dram",
>> OBJECT(machine->ram), &error_abort);
>> object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
>> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
>> index bcbf35bc14..e1c7188e61 100644
>> --- a/hw/ppc/ppc405_uc.c
>> +++ b/hw/ppc/ppc405_uc.c
>> @@ -1073,15 +1073,9 @@ static void ppc405_soc_realize(DeviceState *dev,
>> Error **errp)
>> qdev_get_gpio_in(DEVICE(&s->cpu),
>> PPC40x_INPUT_CINT));
>> /* SDRAM controller */
>> - /* XXX 405EP has no ECC interrupt */
>> - s->ram_banks[0].base = 0;
>> - s->ram_banks[0].size = s->ram_size;
>> - memory_region_init_alias(&s->ram_banks[0].ram, OBJECT(s),
>> - "ppc405.sdram0", s->dram_mr,
>> - s->ram_banks[0].base, s->ram_banks[0].size);
>> -
>> + /* XXX 405EP has no ECC interrupt */
>> ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
>> - s->ram_banks);
>> + s->dram_mr);
>> /* External bus controller */
>> if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
>> @@ -1159,7 +1153,6 @@ static void ppc405_soc_realize(DeviceState *dev,
>> Error **errp)
>> static Property ppc405_soc_properties[] = {
>> DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
>> MemoryRegion *),
>> - DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
>> DEFINE_PROP_END_OF_LIST(),
>> };
>> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
>> index 2bd5e41140..9b456f1819 100644
>> --- a/hw/ppc/ppc440_bamboo.c
>> +++ b/hw/ppc/ppc440_bamboo.c
>> @@ -50,10 +50,6 @@
>> #define PPC440EP_SDRAM_NR_BANKS 4
>> -static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
>> - 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB,
>> 0
>> -};
>> -
>> static hwaddr entry;
>> static int bamboo_load_device_tree(hwaddr addr,
>> @@ -168,8 +164,6 @@ static void bamboo_init(MachineState *machine)
>> unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
>> MemoryRegion *address_space_mem = get_system_memory();
>> MemoryRegion *isa = g_new(MemoryRegion, 1);
>> - Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank,
>> - PPC440EP_SDRAM_NR_BANKS);
>> PCIBus *pcibus;
>> PowerPCCPU *cpu;
>> CPUPPCState *env;
>> @@ -204,11 +198,9 @@ static void bamboo_init(MachineState *machine)
>> qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
>> /* SDRAM controller */
>> - ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_banks,
>> - ppc440ep_sdram_bank_sizes);
>> /* XXX 440EP's ECC interrupts are on UIC1, but we've only created
>> UIC0. */
>> ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
>> - PPC440EP_SDRAM_NR_BANKS, ram_banks);
>> + PPC440EP_SDRAM_NR_BANKS, machine->ram);
>> /* Enable SDRAM memory regions, this should be done by the firmware
>> */
>> if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
>> ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
>> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
>> index 7bdcbd6fac..eb3aa97b16 100644
>> --- a/hw/ppc/ppc4xx_devs.c
>> +++ b/hw/ppc/ppc4xx_devs.c
>> @@ -41,7 +41,7 @@
>> typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
>> struct ppc4xx_sdram_t {
>> uint32_t addr;
>> - int nbanks;
>> + int nbanks; /* Banks to use from the 4, e.g. when board has less slots
>> */
>> Ppc4xxSdramBank bank[4];
>> uint32_t besr0;
>> uint32_t besr1;
>> @@ -343,19 +343,17 @@ static void sdram_reset(void *opaque)
>> }
>> void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
>> - Ppc4xxSdramBank *ram_banks)
>> + MemoryRegion *ram)
>> {
>> ppc4xx_sdram_t *sdram;
>> - int i;
>> + const ram_addr_t valid_bank_sizes[] = {
>> + 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 *
>> MiB, 0
>> + };
>> sdram = g_new0(ppc4xx_sdram_t, 1);
>> sdram->irq = irq;
>> sdram->nbanks = nbanks;
>> - for (i = 0; i < nbanks; i++) {
>> - sdram->bank[i].ram = ram_banks[i].ram;
>> - sdram->bank[i].base = ram_banks[i].base;
>> - sdram->bank[i].size = ram_banks[i].size;
>> - }
>> + ppc4xx_sdram_banks(ram, sdram->nbanks, sdram->bank, valid_bank_sizes);
>> qemu_register_reset(&sdram_reset, sdram);
>> ppc_dcr_register(env, SDRAM0_CFGADDR,
>> sdram, &dcr_read_sdram, &dcr_write_sdram);
>> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
>> index 5013b8bf3a..6007a8dd04 100644
>> --- a/include/hw/ppc/ppc4xx.h
>> +++ b/include/hw/ppc/ppc4xx.h
>> @@ -47,7 +47,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
>> const ram_addr_t sdram_bank_sizes[]);
>> void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
>> - Ppc4xxSdramBank *ram_banks);
>> + MemoryRegion *ram);
>> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>>
>
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v3 07/20] ppc4xx_sdram: QOM'ify
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (5 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 06/20] ppc4xx_sdram: Move size check to ppc4xx_sdram_init() BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-14 7:11 ` Cédric Le Goater
2022-09-13 19:52 ` [PATCH v3 08/20] ppc4xx_sdram: Drop extra zeros for readability BALATON Zoltan
` (13 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Change the ppc4xx_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly
modelling the DDR SDRAM controller found in the 440EP (used on the
bamboo board) but also backward compatible with the older DDR
controllers on some 405 SoCs so we also use it for those now. This
likely does not cause problems for guests we run as the new features
are just not accessed but to model 405 SoC accurately some features
may have to be disabled or the model split between 440 and older.
Newer SoCs (regardless of their PPC core, e.g. 405EX) may have an
updated DDR2 SDRAM controller implemented by the ppc440_sdram model
(only partially, enough for the 460EX on the sam460ex) that is not yet
QOM'ified in this patch. That is intended to become ppc4xx-sdram-ddr2
when QOM'ified later.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405.h | 3 +-
hw/ppc/ppc405_uc.c | 22 +++++----
hw/ppc/ppc440_bamboo.c | 10 +++--
hw/ppc/ppc4xx_devs.c | 99 ++++++++++++++++++++++-------------------
include/hw/ppc/ppc4xx.h | 27 +++++++++--
5 files changed, 98 insertions(+), 63 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ad54dff542..9a4312691e 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -167,8 +167,6 @@ struct Ppc405SoCState {
DeviceState parent_obj;
/* Public */
- MemoryRegion *dram_mr;
-
PowerPCCPU cpu;
PPCUIC uic;
Ppc405CpcState cpc;
@@ -182,6 +180,7 @@ struct Ppc405SoCState {
Ppc405PobState pob;
Ppc4xxPlbState plb;
Ppc4xxMalState mal;
+ Ppc4xxSdramDdrState sdram;
};
#endif /* PPC405_H */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index e1c7188e61..c973cfb04e 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -1016,6 +1016,9 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "plb", &s->plb, TYPE_PPC4xx_PLB);
object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL);
+
+ object_initialize_child(obj, "sdram", &s->sdram, TYPE_PPC4xx_SDRAM_DDR);
+ object_property_add_alias(obj, "dram", OBJECT(&s->sdram), "dram");
}
static void ppc405_reset(void *opaque)
@@ -1073,9 +1076,17 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
+ /*
+ * We use the 440 DDR SDRAM controller which has more regs and features
+ * but it's compatible enough for now
+ */
+ object_property_set_int(OBJECT(&s->sdram), "nbanks", 2, &error_abort);
+ if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->sdram), &s->cpu, errp)) {
+ return;
+ }
/* XXX 405EP has no ECC interrupt */
- ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
- s->dram_mr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdram), 0,
+ qdev_get_gpio_in(DEVICE(&s->uic), 17));
/* External bus controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
@@ -1150,12 +1161,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
/* Uses UIC IRQs 9, 15, 17 */
}
-static Property ppc405_soc_properties[] = {
- DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
- MemoryRegion *),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void ppc405_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -1163,7 +1168,6 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
dc->realize = ppc405_soc_realize;
/* Reason: only works as part of a ppc405 board/machine */
dc->user_creatable = false;
- device_class_set_props(dc, ppc405_soc_properties);
}
static const TypeInfo ppc405_types[] = {
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 9b456f1819..6052d3a2e0 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -48,8 +48,6 @@
#define PPC440EP_PCI_IO 0xe8000000
#define PPC440EP_PCI_IOLEN 0x00010000
-#define PPC440EP_SDRAM_NR_BANKS 4
-
static hwaddr entry;
static int bamboo_load_device_tree(hwaddr addr,
@@ -198,9 +196,13 @@ static void bamboo_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
/* SDRAM controller */
+ dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR);
+ object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
+ &error_abort);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
- ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
- PPC440EP_SDRAM_NR_BANKS, machine->ram);
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(uicdev, 14));
/* Enable SDRAM memory regions, this should be done by the firmware */
if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index eb3aa97b16..375834a52b 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -38,30 +38,12 @@
/*****************************************************************************/
/* SDRAM controller */
-typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
-struct ppc4xx_sdram_t {
- uint32_t addr;
- int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
- Ppc4xxSdramBank bank[4];
- uint32_t besr0;
- uint32_t besr1;
- uint32_t bear;
- uint32_t cfg;
- uint32_t status;
- uint32_t rtr;
- uint32_t pmit;
- uint32_t tr;
- uint32_t ecccfg;
- uint32_t eccesr;
- qemu_irq irq;
-};
-
/*
* XXX: TOFIX: some patches have made this code become inconsistent:
* there are type inconsistencies, mixing hwaddr, target_ulong
* and uint32_t
*/
-static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
+static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -119,7 +101,7 @@ static target_ulong sdram_size(uint32_t bcr)
return size;
}
-static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
+static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 0x00000001) {
@@ -145,21 +127,21 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
}
}
-static void sdram_map_bcr(ppc4xx_sdram_t *sdram)
+static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size != 0) {
- sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
+ sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
} else {
sdram_set_bcr(sdram, i, 0x00000000, 0);
}
}
}
-static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram)
+static void sdram_unmap_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
@@ -171,12 +153,11 @@ static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram)
}
}
-static uint32_t dcr_read_sdram(void *opaque, int dcrn)
+static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
{
- ppc4xx_sdram_t *sdram;
+ Ppc4xxSdramDdrState *sdram = opaque;
uint32_t ret;
- sdram = opaque;
switch (dcrn) {
case SDRAM0_CFGADDR:
ret = sdram->addr;
@@ -239,11 +220,10 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
return ret;
}
-static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
+static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
{
- ppc4xx_sdram_t *sdram;
+ Ppc4xxSdramDdrState *sdram = opaque;
- sdram = opaque;
switch (dcrn) {
case SDRAM0_CFGADDR:
sdram->addr = val;
@@ -322,11 +302,10 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
}
}
-static void sdram_reset(void *opaque)
+static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
{
- ppc4xx_sdram_t *sdram;
+ Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
- sdram = opaque;
sdram->addr = 0x00000000;
sdram->bear = 0x00000000;
sdram->besr0 = 0x00000000; /* No error */
@@ -342,23 +321,48 @@ static void sdram_reset(void *opaque)
sdram->cfg = 0x00800000;
}
-void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- MemoryRegion *ram)
+static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
{
- ppc4xx_sdram_t *sdram;
+ Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
const ram_addr_t valid_bank_sizes[] = {
256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
};
- sdram = g_new0(ppc4xx_sdram_t, 1);
- sdram->irq = irq;
- sdram->nbanks = nbanks;
- ppc4xx_sdram_banks(ram, sdram->nbanks, sdram->bank, valid_bank_sizes);
- qemu_register_reset(&sdram_reset, sdram);
- ppc_dcr_register(env, SDRAM0_CFGADDR,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
- ppc_dcr_register(env, SDRAM0_CFGDATA,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ if (s->nbanks < 1 || s->nbanks > 4) {
+ error_setg(errp, "Invalid number of RAM banks");
+ return;
+ }
+ if (!s->dram_mr) {
+ error_setg(errp, "Missing dram memory region");
+ return;
+ }
+ ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
+
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
+ s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
+ s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
+}
+
+static Property ppc4xx_sdram_ddr_props[] = {
+ DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_sdram_ddr_realize;
+ dc->reset = ppc4xx_sdram_ddr_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc4xx_sdram_ddr_props);
}
/*
@@ -948,6 +952,11 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc4xx_types[] = {
{
+ .name = TYPE_PPC4xx_SDRAM_DDR,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc4xxSdramDdrState),
+ .class_init = ppc4xx_sdram_ddr_class_init,
+ }, {
.name = TYPE_PPC4xx_MAL,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc4xxMalState),
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 6007a8dd04..20d0cdde8a 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -46,9 +46,6 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
Ppc4xxSdramBank ram_banks[],
const ram_addr_t sdram_bank_sizes[]);
-void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
- MemoryRegion *ram);
-
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
/*
@@ -118,4 +115,28 @@ struct Ppc4xxEbcState {
uint32_t cfg;
};
+/* SDRAM DDR controller */
+#define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR);
+struct Ppc4xxSdramDdrState {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ MemoryRegion *dram_mr;
+ uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */
+ Ppc4xxSdramBank bank[4];
+ qemu_irq irq;
+
+ uint32_t addr;
+ uint32_t besr0;
+ uint32_t besr1;
+ uint32_t bear;
+ uint32_t cfg;
+ uint32_t status;
+ uint32_t rtr;
+ uint32_t pmit;
+ uint32_t tr;
+ uint32_t ecccfg;
+ uint32_t eccesr;
+};
+
#endif /* PPC4XX_H */
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v3 07/20] ppc4xx_sdram: QOM'ify
2022-09-13 19:52 ` [PATCH v3 07/20] ppc4xx_sdram: QOM'ify BALATON Zoltan
@ 2022-09-14 7:11 ` Cédric Le Goater
0 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-09-14 7:11 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 9/13/22 21:52, BALATON Zoltan wrote:
> Change the ppc4xx_sdram model to a QOM class derived from the
> PPC4xx-dcr-device and name it ppc4xx-sdram-ddr. This is mostly
> modelling the DDR SDRAM controller found in the 440EP (used on the
> bamboo board) but also backward compatible with the older DDR
> controllers on some 405 SoCs so we also use it for those now. This
> likely does not cause problems for guests we run as the new features
> are just not accessed but to model 405 SoC accurately some features
> may have to be disabled or the model split between 440 and older.
>
> Newer SoCs (regardless of their PPC core, e.g. 405EX) may have an
> updated DDR2 SDRAM controller implemented by the ppc440_sdram model
> (only partially, enough for the 460EX on the sam460ex) that is not yet
> QOM'ified in this patch. That is intended to become ppc4xx-sdram-ddr2
> when QOM'ified later.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/ppc405.h | 3 +-
> hw/ppc/ppc405_uc.c | 22 +++++----
> hw/ppc/ppc440_bamboo.c | 10 +++--
> hw/ppc/ppc4xx_devs.c | 99 ++++++++++++++++++++++-------------------
> include/hw/ppc/ppc4xx.h | 27 +++++++++--
> 5 files changed, 98 insertions(+), 63 deletions(-)
>
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index ad54dff542..9a4312691e 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -167,8 +167,6 @@ struct Ppc405SoCState {
> DeviceState parent_obj;
>
> /* Public */
> - MemoryRegion *dram_mr;
> -
> PowerPCCPU cpu;
> PPCUIC uic;
> Ppc405CpcState cpc;
> @@ -182,6 +180,7 @@ struct Ppc405SoCState {
> Ppc405PobState pob;
> Ppc4xxPlbState plb;
> Ppc4xxMalState mal;
> + Ppc4xxSdramDdrState sdram;
> };
>
> #endif /* PPC405_H */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index e1c7188e61..c973cfb04e 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -1016,6 +1016,9 @@ static void ppc405_soc_instance_init(Object *obj)
> object_initialize_child(obj, "plb", &s->plb, TYPE_PPC4xx_PLB);
>
> object_initialize_child(obj, "mal", &s->mal, TYPE_PPC4xx_MAL);
> +
> + object_initialize_child(obj, "sdram", &s->sdram, TYPE_PPC4xx_SDRAM_DDR);
> + object_property_add_alias(obj, "dram", OBJECT(&s->sdram), "dram");
> }
>
> static void ppc405_reset(void *opaque)
> @@ -1073,9 +1076,17 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> qdev_get_gpio_in(DEVICE(&s->cpu), PPC40x_INPUT_CINT));
>
> /* SDRAM controller */
> + /*
> + * We use the 440 DDR SDRAM controller which has more regs and features
> + * but it's compatible enough for now
> + */
> + object_property_set_int(OBJECT(&s->sdram), "nbanks", 2, &error_abort);
> + if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->sdram), &s->cpu, errp)) {
> + return;
> + }
> /* XXX 405EP has no ECC interrupt */
> - ppc4xx_sdram_init(env, qdev_get_gpio_in(DEVICE(&s->uic), 17), 1,
> - s->dram_mr);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdram), 0,
> + qdev_get_gpio_in(DEVICE(&s->uic), 17));
>
> /* External bus controller */
> if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
> @@ -1150,12 +1161,6 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> /* Uses UIC IRQs 9, 15, 17 */
> }
>
> -static Property ppc405_soc_properties[] = {
> - DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
> - MemoryRegion *),
> - DEFINE_PROP_END_OF_LIST(),
> -};
> -
> static void ppc405_soc_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -1163,7 +1168,6 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
> dc->realize = ppc405_soc_realize;
> /* Reason: only works as part of a ppc405 board/machine */
> dc->user_creatable = false;
> - device_class_set_props(dc, ppc405_soc_properties);
> }
>
> static const TypeInfo ppc405_types[] = {
> diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
> index 9b456f1819..6052d3a2e0 100644
> --- a/hw/ppc/ppc440_bamboo.c
> +++ b/hw/ppc/ppc440_bamboo.c
> @@ -48,8 +48,6 @@
> #define PPC440EP_PCI_IO 0xe8000000
> #define PPC440EP_PCI_IOLEN 0x00010000
>
> -#define PPC440EP_SDRAM_NR_BANKS 4
> -
> static hwaddr entry;
>
> static int bamboo_load_device_tree(hwaddr addr,
> @@ -198,9 +196,13 @@ static void bamboo_init(MachineState *machine)
> qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
>
> /* SDRAM controller */
> + dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR);
> + object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
> + &error_abort);
> + ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
> + object_unref(OBJECT(dev));
> /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
> - ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 14),
> - PPC440EP_SDRAM_NR_BANKS, machine->ram);
> + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(uicdev, 14));
> /* Enable SDRAM memory regions, this should be done by the firmware */
> if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20) ||
> ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000)) {
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index eb3aa97b16..375834a52b 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -38,30 +38,12 @@
>
> /*****************************************************************************/
> /* SDRAM controller */
> -typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
> -struct ppc4xx_sdram_t {
> - uint32_t addr;
> - int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
> - Ppc4xxSdramBank bank[4];
> - uint32_t besr0;
> - uint32_t besr1;
> - uint32_t bear;
> - uint32_t cfg;
> - uint32_t status;
> - uint32_t rtr;
> - uint32_t pmit;
> - uint32_t tr;
> - uint32_t ecccfg;
> - uint32_t eccesr;
> - qemu_irq irq;
> -};
> -
> /*
> * XXX: TOFIX: some patches have made this code become inconsistent:
> * there are type inconsistencies, mixing hwaddr, target_ulong
> * and uint32_t
> */
> -static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
> +static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
> {
> uint32_t bcr;
>
> @@ -119,7 +101,7 @@ static target_ulong sdram_size(uint32_t bcr)
> return size;
> }
>
> -static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
> +static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
> uint32_t bcr, int enabled)
> {
> if (sdram->bank[i].bcr & 0x00000001) {
> @@ -145,21 +127,21 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
> }
> }
>
> -static void sdram_map_bcr(ppc4xx_sdram_t *sdram)
> +static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
> {
> int i;
>
> for (i = 0; i < sdram->nbanks; i++) {
> if (sdram->bank[i].size != 0) {
> - sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
> - sdram->bank[i].size), 1);
> + sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
> + sdram->bank[i].size), 1);
> } else {
> sdram_set_bcr(sdram, i, 0x00000000, 0);
> }
> }
> }
>
> -static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram)
> +static void sdram_unmap_bcr(Ppc4xxSdramDdrState *sdram)
> {
> int i;
>
> @@ -171,12 +153,11 @@ static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram)
> }
> }
>
> -static uint32_t dcr_read_sdram(void *opaque, int dcrn)
> +static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
> {
> - ppc4xx_sdram_t *sdram;
> + Ppc4xxSdramDdrState *sdram = opaque;
> uint32_t ret;
>
> - sdram = opaque;
> switch (dcrn) {
> case SDRAM0_CFGADDR:
> ret = sdram->addr;
> @@ -239,11 +220,10 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
> return ret;
> }
>
> -static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
> +static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
> {
> - ppc4xx_sdram_t *sdram;
> + Ppc4xxSdramDdrState *sdram = opaque;
>
> - sdram = opaque;
> switch (dcrn) {
> case SDRAM0_CFGADDR:
> sdram->addr = val;
> @@ -322,11 +302,10 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
> }
> }
>
> -static void sdram_reset(void *opaque)
> +static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
> {
> - ppc4xx_sdram_t *sdram;
> + Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
>
> - sdram = opaque;
> sdram->addr = 0x00000000;
> sdram->bear = 0x00000000;
> sdram->besr0 = 0x00000000; /* No error */
> @@ -342,23 +321,48 @@ static void sdram_reset(void *opaque)
> sdram->cfg = 0x00800000;
> }
>
> -void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
> - MemoryRegion *ram)
> +static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
> {
> - ppc4xx_sdram_t *sdram;
> + Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
> + Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
> const ram_addr_t valid_bank_sizes[] = {
> 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
> };
>
> - sdram = g_new0(ppc4xx_sdram_t, 1);
> - sdram->irq = irq;
> - sdram->nbanks = nbanks;
> - ppc4xx_sdram_banks(ram, sdram->nbanks, sdram->bank, valid_bank_sizes);
> - qemu_register_reset(&sdram_reset, sdram);
> - ppc_dcr_register(env, SDRAM0_CFGADDR,
> - sdram, &dcr_read_sdram, &dcr_write_sdram);
> - ppc_dcr_register(env, SDRAM0_CFGDATA,
> - sdram, &dcr_read_sdram, &dcr_write_sdram);
> + if (s->nbanks < 1 || s->nbanks > 4) {
> + error_setg(errp, "Invalid number of RAM banks");
> + return;
> + }
> + if (!s->dram_mr) {
> + error_setg(errp, "Missing dram memory region");
> + return;
> + }
> + ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
As said previously, ppc4xx_sdram_banks should a take "Error **errp" and
propagate the error.
Thanks,
C.
> +
> + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
> +
> + ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
> + s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
> + ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
> + s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
> +}
> +
> +static Property ppc4xx_sdram_ddr_props[] = {
> + DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION,
> + MemoryRegion *),
> + DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = ppc4xx_sdram_ddr_realize;
> + dc->reset = ppc4xx_sdram_ddr_reset;
> + /* Reason: only works as function of a ppc4xx SoC */
> + dc->user_creatable = false;
> + device_class_set_props(dc, ppc4xx_sdram_ddr_props);
> }
>
> /*
> @@ -948,6 +952,11 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
>
> static const TypeInfo ppc4xx_types[] = {
> {
> + .name = TYPE_PPC4xx_SDRAM_DDR,
> + .parent = TYPE_PPC4xx_DCR_DEVICE,
> + .instance_size = sizeof(Ppc4xxSdramDdrState),
> + .class_init = ppc4xx_sdram_ddr_class_init,
> + }, {
> .name = TYPE_PPC4xx_MAL,
> .parent = TYPE_PPC4xx_DCR_DEVICE,
> .instance_size = sizeof(Ppc4xxMalState),
> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
> index 6007a8dd04..20d0cdde8a 100644
> --- a/include/hw/ppc/ppc4xx.h
> +++ b/include/hw/ppc/ppc4xx.h
> @@ -46,9 +46,6 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
> Ppc4xxSdramBank ram_banks[],
> const ram_addr_t sdram_bank_sizes[]);
>
> -void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
> - MemoryRegion *ram);
> -
> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>
> /*
> @@ -118,4 +115,28 @@ struct Ppc4xxEbcState {
> uint32_t cfg;
> };
>
> +/* SDRAM DDR controller */
> +#define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR);
> +struct Ppc4xxSdramDdrState {
> + Ppc4xxDcrDeviceState parent_obj;
> +
> + MemoryRegion *dram_mr;
> + uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */
> + Ppc4xxSdramBank bank[4];
> + qemu_irq irq;
> +
> + uint32_t addr;
> + uint32_t besr0;
> + uint32_t besr1;
> + uint32_t bear;
> + uint32_t cfg;
> + uint32_t status;
> + uint32_t rtr;
> + uint32_t pmit;
> + uint32_t tr;
> + uint32_t ecccfg;
> + uint32_t eccesr;
> +};
> +
> #endif /* PPC4XX_H */
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v3 08/20] ppc4xx_sdram: Drop extra zeros for readability
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (6 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 07/20] ppc4xx_sdram: QOM'ify BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 09/20] ppc440_sdram: Split off map/unmap of sdram banks for later reuse BALATON Zoltan
` (12 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Constants that are written zero padded for no good reason are hard to
read, it's easier to see what is meant if it's just 0 or 1 instead.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc4xx_devs.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 375834a52b..bfe7b2d3a6 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -49,31 +49,31 @@ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
switch (ram_size) {
case 4 * MiB:
- bcr = 0x00000000;
+ bcr = 0;
break;
case 8 * MiB:
- bcr = 0x00020000;
+ bcr = 0x20000;
break;
case 16 * MiB:
- bcr = 0x00040000;
+ bcr = 0x40000;
break;
case 32 * MiB:
- bcr = 0x00060000;
+ bcr = 0x60000;
break;
case 64 * MiB:
- bcr = 0x00080000;
+ bcr = 0x80000;
break;
case 128 * MiB:
- bcr = 0x000A0000;
+ bcr = 0xA0000;
break;
case 256 * MiB:
- bcr = 0x000C0000;
+ bcr = 0xC0000;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
ram_size);
- return 0x00000000;
+ return 0;
}
bcr |= ram_base & 0xFF800000;
bcr |= 1;
@@ -104,7 +104,7 @@ static target_ulong sdram_size(uint32_t bcr)
static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
uint32_t bcr, int enabled)
{
- if (sdram->bank[i].bcr & 0x00000001) {
+ if (sdram->bank[i].bcr & 1) {
/* Unmap RAM */
trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
sdram_size(sdram->bank[i].bcr));
@@ -115,7 +115,7 @@ static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
object_unparent(OBJECT(&sdram->bank[i].container));
}
sdram->bank[i].bcr = bcr & 0xFFDEE001;
- if (enabled && (bcr & 0x00000001)) {
+ if (enabled && (bcr & 1)) {
trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
sdram_size(bcr));
@@ -136,7 +136,7 @@ static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
- sdram_set_bcr(sdram, i, 0x00000000, 0);
+ sdram_set_bcr(sdram, i, 0, 0);
}
}
}
@@ -213,7 +213,7 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
break;
default:
/* Avoid gcc warning */
- ret = 0x00000000;
+ ret = 0;
break;
}
@@ -306,18 +306,18 @@ static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
{
Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
- sdram->addr = 0x00000000;
- sdram->bear = 0x00000000;
- sdram->besr0 = 0x00000000; /* No error */
- sdram->besr1 = 0x00000000; /* No error */
- sdram->cfg = 0x00000000;
- sdram->ecccfg = 0x00000000; /* No ECC */
- sdram->eccesr = 0x00000000; /* No error */
+ sdram->addr = 0;
+ sdram->bear = 0;
+ sdram->besr0 = 0; /* No error */
+ sdram->besr1 = 0; /* No error */
+ sdram->cfg = 0;
+ sdram->ecccfg = 0; /* No ECC */
+ sdram->eccesr = 0; /* No error */
sdram->pmit = 0x07C00000;
sdram->rtr = 0x05F00000;
sdram->tr = 0x00854009;
/* We pre-initialize RAM banks */
- sdram->status = 0x00000000;
+ sdram->status = 0;
sdram->cfg = 0x00800000;
}
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v3 09/20] ppc440_sdram: Split off map/unmap of sdram banks for later reuse
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (7 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 08/20] ppc4xx_sdram: Drop extra zeros for readability BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-14 7:14 ` Cédric Le Goater
2022-09-13 19:52 ` [PATCH v3 10/20] ppc440_sdram: Implement enable bit in the DDR2 SDRAM BALATON Zoltan
` (11 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc440_uc.c | 31 +++++++++++++++++++------------
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 5db59d1190..01184e717b 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -561,26 +561,33 @@ static uint64_t sdram_size(uint32_t bcr)
return size;
}
+static void sdram_bank_map(Ppc4xxSdramBank *bank)
+{
+ memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
+ memory_region_add_subregion(&bank->container, 0, &bank->ram);
+ memory_region_add_subregion(get_system_memory(), bank->base,
+ &bank->container);
+}
+
+static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
+{
+ memory_region_del_subregion(get_system_memory(), &bank->container);
+ memory_region_del_subregion(&bank->container, &bank->ram);
+ object_unparent(OBJECT(&bank->container));
+}
+
static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
- memory_region_del_subregion(get_system_memory(),
- &sdram->bank[i].container);
- memory_region_del_subregion(&sdram->bank[i].container,
- &sdram->bank[i].ram);
- object_unparent(OBJECT(&sdram->bank[i].container));
+ sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
+ sdram->bank[i].base = sdram_base(bcr);
+ sdram->bank[i].size = sdram_size(bcr);
if (enabled && (bcr & 1)) {
- memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
- sdram_size(bcr));
- memory_region_add_subregion(&sdram->bank[i].container, 0,
- &sdram->bank[i].ram);
- memory_region_add_subregion(get_system_memory(),
- sdram_base(bcr),
- &sdram->bank[i].container);
+ sdram_bank_map(&sdram->bank[i]);
}
}
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v3 09/20] ppc440_sdram: Split off map/unmap of sdram banks for later reuse
2022-09-13 19:52 ` [PATCH v3 09/20] ppc440_sdram: Split off map/unmap of sdram banks for later reuse BALATON Zoltan
@ 2022-09-14 7:14 ` Cédric Le Goater
2022-09-14 11:50 ` BALATON Zoltan
0 siblings, 1 reply; 41+ messages in thread
From: Cédric Le Goater @ 2022-09-14 7:14 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 9/13/22 21:52, BALATON Zoltan wrote:
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ppc/ppc440_uc.c | 31 +++++++++++++++++++------------
> 1 file changed, 19 insertions(+), 12 deletions(-)
>
> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
> index 5db59d1190..01184e717b 100644
> --- a/hw/ppc/ppc440_uc.c
> +++ b/hw/ppc/ppc440_uc.c
> @@ -561,26 +561,33 @@ static uint64_t sdram_size(uint32_t bcr)
> return size;
> }
>
> +static void sdram_bank_map(Ppc4xxSdramBank *bank)
> +{
> + memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
This init belongs to the realize routine.
It is a oneliner. I think you can do it now without risks.
Thanks,
C.
> + memory_region_add_subregion(&bank->container, 0, &bank->ram);
> + memory_region_add_subregion(get_system_memory(), bank->base,
> + &bank->container);
> +}
> +
> +static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
> +{
> + memory_region_del_subregion(get_system_memory(), &bank->container);
> + memory_region_del_subregion(&bank->container, &bank->ram);
> + object_unparent(OBJECT(&bank->container));
> +}
> +
> static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
> uint32_t bcr, int enabled)
> {
> if (sdram->bank[i].bcr & 1) {
> /* First unmap RAM if enabled */
> - memory_region_del_subregion(get_system_memory(),
> - &sdram->bank[i].container);
> - memory_region_del_subregion(&sdram->bank[i].container,
> - &sdram->bank[i].ram);
> - object_unparent(OBJECT(&sdram->bank[i].container));
> + sdram_bank_unmap(&sdram->bank[i]);
> }
> sdram->bank[i].bcr = bcr & 0xffe0ffc1;
> + sdram->bank[i].base = sdram_base(bcr);
> + sdram->bank[i].size = sdram_size(bcr);
> if (enabled && (bcr & 1)) {
> - memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
> - sdram_size(bcr));
> - memory_region_add_subregion(&sdram->bank[i].container, 0,
> - &sdram->bank[i].ram);
> - memory_region_add_subregion(get_system_memory(),
> - sdram_base(bcr),
> - &sdram->bank[i].container);
> + sdram_bank_map(&sdram->bank[i]);
> }
> }
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v3 09/20] ppc440_sdram: Split off map/unmap of sdram banks for later reuse
2022-09-14 7:14 ` Cédric Le Goater
@ 2022-09-14 11:50 ` BALATON Zoltan
0 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-14 11:50 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 3189 bytes --]
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
> On 9/13/22 21:52, BALATON Zoltan wrote:
>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>> ---
>> hw/ppc/ppc440_uc.c | 31 +++++++++++++++++++------------
>> 1 file changed, 19 insertions(+), 12 deletions(-)
>>
>> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
>> index 5db59d1190..01184e717b 100644
>> --- a/hw/ppc/ppc440_uc.c
>> +++ b/hw/ppc/ppc440_uc.c
>> @@ -561,26 +561,33 @@ static uint64_t sdram_size(uint32_t bcr)
>> return size;
>> }
>> +static void sdram_bank_map(Ppc4xxSdramBank *bank)
>> +{
>> + memory_region_init(&bank->container, NULL, "sdram-container",
>> bank->size);
>
> This init belongs to the realize routine.
>
> It is a oneliner. I think you can do it now without risks.
Not in this patch for sure as this is just moving this out from the write
callback here. What you suggest is a separate clean up that could be
considered as a followup after this series. I'm not sure which way is best
as one could argue that we don't need this container region and could just
create the ram region alias with the right size and offset but that may
need to store more info or understand the register values better. Since I
may not understand it completely I chose to not break it more and just
leave it as it is for now. You could think about changing it afterwards
separately.
Regards,
BALATON Zoltan
> Thanks,
>
> C.
>
>> + memory_region_add_subregion(&bank->container, 0, &bank->ram);
>> + memory_region_add_subregion(get_system_memory(), bank->base,
>> + &bank->container);
>> +}
>> +
>> +static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
>> +{
>> + memory_region_del_subregion(get_system_memory(), &bank->container);
>> + memory_region_del_subregion(&bank->container, &bank->ram);
>> + object_unparent(OBJECT(&bank->container));
>> +}
>> +
>> static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
>> uint32_t bcr, int enabled)
>> {
>> if (sdram->bank[i].bcr & 1) {
>> /* First unmap RAM if enabled */
>> - memory_region_del_subregion(get_system_memory(),
>> - &sdram->bank[i].container);
>> - memory_region_del_subregion(&sdram->bank[i].container,
>> - &sdram->bank[i].ram);
>> - object_unparent(OBJECT(&sdram->bank[i].container));
>> + sdram_bank_unmap(&sdram->bank[i]);
>> }
>> sdram->bank[i].bcr = bcr & 0xffe0ffc1;
>> + sdram->bank[i].base = sdram_base(bcr);
>> + sdram->bank[i].size = sdram_size(bcr);
>> if (enabled && (bcr & 1)) {
>> - memory_region_init(&sdram->bank[i].container, NULL,
>> "sdram-container",
>> - sdram_size(bcr));
>> - memory_region_add_subregion(&sdram->bank[i].container, 0,
>> - &sdram->bank[i].ram);
>> - memory_region_add_subregion(get_system_memory(),
>> - sdram_base(bcr),
>> - &sdram->bank[i].container);
>> + sdram_bank_map(&sdram->bank[i]);
>> }
>> }
>>
>
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v3 10/20] ppc440_sdram: Implement enable bit in the DDR2 SDRAM
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (8 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 09/20] ppc440_sdram: Split off map/unmap of sdram banks for later reuse BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-14 7:20 ` Cédric Le Goater
2022-09-13 19:52 ` [PATCH v3 11/20] ppc440_sdram: Get rid of the init RAM hack BALATON Zoltan
` (10 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
To allow removing the do_init hack we need to improve the DDR2 SDRAM
controller model to handle the enable/disable bit that it ignored so
far.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
v2: replace 0x08000000 with BIT(27)
hw/ppc/ppc440_uc.c | 34 ++++++++++++++++++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 01184e717b..3c442eaecc 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -23,6 +23,7 @@
#include "sysemu/reset.h"
#include "ppc440.h"
#include "qom/object.h"
+#include "trace.h"
/*****************************************************************************/
/* L2 Cache as SRAM */
@@ -484,6 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
/* SDRAM controller */
typedef struct ppc440_sdram_t {
uint32_t addr;
+ uint32_t mcopt2;
int nbanks;
Ppc4xxSdramBank bank[4];
} ppc440_sdram_t;
@@ -581,12 +583,15 @@ static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
+ trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
+ sdram_size(sdram->bank[i].bcr));
sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
sdram->bank[i].base = sdram_base(bcr);
sdram->bank[i].size = sdram_size(bcr);
if (enabled && (bcr & 1)) {
+ trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
sdram_bank_map(&sdram->bank[i]);
}
}
@@ -596,7 +601,7 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
int i;
for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size != 0) {
+ if (sdram->bank[i].size) {
sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
@@ -605,6 +610,17 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
}
}
+static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
+{
+ int i;
+
+ for (i = 0; i < sdram->nbanks; i++) {
+ if (sdram->bank[i].size) {
+ sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
+ }
+ }
+}
+
static uint32_t dcr_read_sdram(void *opaque, int dcrn)
{
ppc440_sdram_t *sdram = opaque;
@@ -636,7 +652,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
ret = 0x80000000;
break;
case 0x21: /* SDRAM_MCOPT2 */
- ret = 0x08000000;
+ ret = sdram->mcopt2;
break;
case 0x40: /* SDRAM_MB0CF */
ret = 0x00008001;
@@ -680,6 +696,19 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
switch (sdram->addr) {
case 0x00: /* B0CR */
break;
+ case 0x21: /* SDRAM_MCOPT2 */
+ if (!(sdram->mcopt2 & BIT(27)) && (val & BIT(27))) {
+ trace_ppc4xx_sdram_enable("enable");
+ /* validate all RAM mappings */
+ sdram_map_bcr(sdram);
+ sdram->mcopt2 |= BIT(27);
+ } else if ((sdram->mcopt2 & BIT(27)) && !(val & BIT(27))) {
+ trace_ppc4xx_sdram_enable("disable");
+ /* invalidate all RAM mappings */
+ sdram_unmap_bcr(sdram);
+ sdram->mcopt2 &= ~BIT(27);
+ }
+ break;
default:
break;
}
@@ -694,6 +723,7 @@ static void sdram_reset(void *opaque)
ppc440_sdram_t *sdram = opaque;
sdram->addr = 0;
+ sdram->mcopt2 = BIT(27);
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v3 10/20] ppc440_sdram: Implement enable bit in the DDR2 SDRAM
2022-09-13 19:52 ` [PATCH v3 10/20] ppc440_sdram: Implement enable bit in the DDR2 SDRAM BALATON Zoltan
@ 2022-09-14 7:20 ` Cédric Le Goater
0 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-09-14 7:20 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 9/13/22 21:52, BALATON Zoltan wrote:
> To allow removing the do_init hack we need to improve the DDR2 SDRAM
> controller model to handle the enable/disable bit that it ignored so
> far.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Please consider adding a define instead.
Thanks,
C.
> ---
> v2: replace 0x08000000 with BIT(27)
>
> hw/ppc/ppc440_uc.c | 34 ++++++++++++++++++++++++++++++++--
> 1 file changed, 32 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
> index 01184e717b..3c442eaecc 100644
> --- a/hw/ppc/ppc440_uc.c
> +++ b/hw/ppc/ppc440_uc.c
> @@ -23,6 +23,7 @@
> #include "sysemu/reset.h"
> #include "ppc440.h"
> #include "qom/object.h"
> +#include "trace.h"
>
> /*****************************************************************************/
> /* L2 Cache as SRAM */
> @@ -484,6 +485,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
> /* SDRAM controller */
> typedef struct ppc440_sdram_t {
> uint32_t addr;
> + uint32_t mcopt2;
> int nbanks;
> Ppc4xxSdramBank bank[4];
> } ppc440_sdram_t;
> @@ -581,12 +583,15 @@ static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
> {
> if (sdram->bank[i].bcr & 1) {
> /* First unmap RAM if enabled */
> + trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
> + sdram_size(sdram->bank[i].bcr));
> sdram_bank_unmap(&sdram->bank[i]);
> }
> sdram->bank[i].bcr = bcr & 0xffe0ffc1;
> sdram->bank[i].base = sdram_base(bcr);
> sdram->bank[i].size = sdram_size(bcr);
> if (enabled && (bcr & 1)) {
> + trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
> sdram_bank_map(&sdram->bank[i]);
> }
> }
> @@ -596,7 +601,7 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
> int i;
>
> for (i = 0; i < sdram->nbanks; i++) {
> - if (sdram->bank[i].size != 0) {
> + if (sdram->bank[i].size) {
> sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
> sdram->bank[i].size), 1);
> } else {
> @@ -605,6 +610,17 @@ static void sdram_map_bcr(ppc440_sdram_t *sdram)
> }
> }
>
> +static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
> +{
> + int i;
> +
> + for (i = 0; i < sdram->nbanks; i++) {
> + if (sdram->bank[i].size) {
> + sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
> + }
> + }
> +}
> +
> static uint32_t dcr_read_sdram(void *opaque, int dcrn)
> {
> ppc440_sdram_t *sdram = opaque;
> @@ -636,7 +652,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
> ret = 0x80000000;
> break;
> case 0x21: /* SDRAM_MCOPT2 */
> - ret = 0x08000000;
> + ret = sdram->mcopt2;
> break;
> case 0x40: /* SDRAM_MB0CF */
> ret = 0x00008001;
> @@ -680,6 +696,19 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
> switch (sdram->addr) {
> case 0x00: /* B0CR */
> break;
> + case 0x21: /* SDRAM_MCOPT2 */
> + if (!(sdram->mcopt2 & BIT(27)) && (val & BIT(27))) {
> + trace_ppc4xx_sdram_enable("enable");
> + /* validate all RAM mappings */
> + sdram_map_bcr(sdram);
> + sdram->mcopt2 |= BIT(27);
> + } else if ((sdram->mcopt2 & BIT(27)) && !(val & BIT(27))) {
> + trace_ppc4xx_sdram_enable("disable");
> + /* invalidate all RAM mappings */
> + sdram_unmap_bcr(sdram);
> + sdram->mcopt2 &= ~BIT(27);
> + }
> + break;
> default:
> break;
> }
> @@ -694,6 +723,7 @@ static void sdram_reset(void *opaque)
> ppc440_sdram_t *sdram = opaque;
>
> sdram->addr = 0;
> + sdram->mcopt2 = BIT(27);
> }
>
> void ppc440_sdram_init(CPUPPCState *env, int nbanks,
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v3 11/20] ppc440_sdram: Get rid of the init RAM hack
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (9 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 10/20] ppc440_sdram: Implement enable bit in the DDR2 SDRAM BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 12/20] ppc440_sdram: Rename local variable for readibility BALATON Zoltan
` (9 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Remove the do_init parameter of ppc440_sdram_init and enable SDRAM
controller from the board via DCR access instead. Firmware does this
so it may not be needed when booting firmware only with -kernel but we
enable it unconditionally to preserve previous behaviour.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
v2: replace 0x08000000 with BIT(27)
hw/ppc/ppc440.h | 3 +--
hw/ppc/ppc440_uc.c | 8 ++------
hw/ppc/sam460ex.c | 8 +++++++-
3 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index e6c905b7d6..01d76b8000 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -17,8 +17,7 @@ void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks,
- int do_init);
+ Ppc4xxSdramBank *ram_banks);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 3c442eaecc..b3f56c49b5 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -723,12 +723,11 @@ static void sdram_reset(void *opaque)
ppc440_sdram_t *sdram = opaque;
sdram->addr = 0;
- sdram->mcopt2 = BIT(27);
+ sdram->mcopt2 = 0;
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks,
- int do_init)
+ Ppc4xxSdramBank *ram_banks)
{
ppc440_sdram_t *sdram;
int i;
@@ -745,9 +744,6 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
sdram, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
sdram, &dcr_read_sdram, &dcr_write_sdram);
- if (do_init) {
- sdram_map_bcr(sdram);
- }
ppc_dcr_register(env, SDRAM_R0BAS,
sdram, &dcr_read_sdram, &dcr_write_sdram);
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index f4c2a693fb..dac329d482 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -345,7 +345,13 @@ static void sam460ex_init(MachineState *machine)
ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes);
/* FIXME: does 460EX have ECC interrupts? */
- ppc440_sdram_init(env, 1, ram_banks, 1);
+ ppc440_sdram_init(env, 1, ram_banks);
+ /* Enable SDRAM memory regions as we may boot without firmware */
+ if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21) ||
+ ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000)) {
+ error_report("Couldn't enable memory regions");
+ exit(1);
+ }
/* IIC controllers and devices */
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v3 12/20] ppc440_sdram: Rename local variable for readibility
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (10 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 11/20] ppc440_sdram: Get rid of the init RAM hack BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-14 7:20 ` Cédric Le Goater
2022-09-13 19:52 ` [PATCH v3 13/20] ppc4xx_sdram: Rename functions to prevent name clashes BALATON Zoltan
` (8 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Rename local sdram variable in ppc440_sdram_init to s for readibility.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc440_uc.c | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index b3f56c49b5..d8a7947196 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -729,40 +729,40 @@ static void sdram_reset(void *opaque)
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
Ppc4xxSdramBank *ram_banks)
{
- ppc440_sdram_t *sdram;
+ ppc440_sdram_t *s;
int i;
- sdram = g_malloc0(sizeof(*sdram));
- sdram->nbanks = nbanks;
+ s = g_malloc0(sizeof(*s));
+ s->nbanks = nbanks;
for (i = 0; i < nbanks; i++) {
- sdram->bank[i].ram = ram_banks[i].ram;
- sdram->bank[i].base = ram_banks[i].base;
- sdram->bank[i].size = ram_banks[i].size;
+ s->bank[i].ram = ram_banks[i].ram;
+ s->bank[i].base = ram_banks[i].base;
+ s->bank[i].size = ram_banks[i].size;
}
- qemu_register_reset(&sdram_reset, sdram);
+ qemu_register_reset(&sdram_reset, s);
ppc_dcr_register(env, SDRAM0_CFGADDR,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM0_CFGDATA,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R0BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R1BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R2BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_R3BAS,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_CONF1HB,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_PLBADDULL,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_CONF1LL,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_CONFPATHB,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
ppc_dcr_register(env, SDRAM_PLBADDUHB,
- sdram, &dcr_read_sdram, &dcr_write_sdram);
+ s, &dcr_read_sdram, &dcr_write_sdram);
}
/*****************************************************************************/
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v3 12/20] ppc440_sdram: Rename local variable for readibility
2022-09-13 19:52 ` [PATCH v3 12/20] ppc440_sdram: Rename local variable for readibility BALATON Zoltan
@ 2022-09-14 7:20 ` Cédric Le Goater
0 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-09-14 7:20 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 9/13/22 21:52, BALATON Zoltan wrote:
> Rename local sdram variable in ppc440_sdram_init to s for readibility.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/ppc/ppc440_uc.c | 36 ++++++++++++++++++------------------
> 1 file changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
> index b3f56c49b5..d8a7947196 100644
> --- a/hw/ppc/ppc440_uc.c
> +++ b/hw/ppc/ppc440_uc.c
> @@ -729,40 +729,40 @@ static void sdram_reset(void *opaque)
> void ppc440_sdram_init(CPUPPCState *env, int nbanks,
> Ppc4xxSdramBank *ram_banks)
> {
> - ppc440_sdram_t *sdram;
> + ppc440_sdram_t *s;
> int i;
>
> - sdram = g_malloc0(sizeof(*sdram));
> - sdram->nbanks = nbanks;
> + s = g_malloc0(sizeof(*s));
> + s->nbanks = nbanks;
> for (i = 0; i < nbanks; i++) {
> - sdram->bank[i].ram = ram_banks[i].ram;
> - sdram->bank[i].base = ram_banks[i].base;
> - sdram->bank[i].size = ram_banks[i].size;
> + s->bank[i].ram = ram_banks[i].ram;
> + s->bank[i].base = ram_banks[i].base;
> + s->bank[i].size = ram_banks[i].size;
> }
> - qemu_register_reset(&sdram_reset, sdram);
> + qemu_register_reset(&sdram_reset, s);
> ppc_dcr_register(env, SDRAM0_CFGADDR,
> - sdram, &dcr_read_sdram, &dcr_write_sdram);
> + s, &dcr_read_sdram, &dcr_write_sdram);
> ppc_dcr_register(env, SDRAM0_CFGDATA,
> - sdram, &dcr_read_sdram, &dcr_write_sdram);
> + s, &dcr_read_sdram, &dcr_write_sdram);
>
> ppc_dcr_register(env, SDRAM_R0BAS,
> - sdram, &dcr_read_sdram, &dcr_write_sdram);
> + s, &dcr_read_sdram, &dcr_write_sdram);
> ppc_dcr_register(env, SDRAM_R1BAS,
> - sdram, &dcr_read_sdram, &dcr_write_sdram);
> + s, &dcr_read_sdram, &dcr_write_sdram);
> ppc_dcr_register(env, SDRAM_R2BAS,
> - sdram, &dcr_read_sdram, &dcr_write_sdram);
> + s, &dcr_read_sdram, &dcr_write_sdram);
> ppc_dcr_register(env, SDRAM_R3BAS,
> - sdram, &dcr_read_sdram, &dcr_write_sdram);
> + s, &dcr_read_sdram, &dcr_write_sdram);
> ppc_dcr_register(env, SDRAM_CONF1HB,
> - sdram, &dcr_read_sdram, &dcr_write_sdram);
> + s, &dcr_read_sdram, &dcr_write_sdram);
> ppc_dcr_register(env, SDRAM_PLBADDULL,
> - sdram, &dcr_read_sdram, &dcr_write_sdram);
> + s, &dcr_read_sdram, &dcr_write_sdram);
> ppc_dcr_register(env, SDRAM_CONF1LL,
> - sdram, &dcr_read_sdram, &dcr_write_sdram);
> + s, &dcr_read_sdram, &dcr_write_sdram);
> ppc_dcr_register(env, SDRAM_CONFPATHB,
> - sdram, &dcr_read_sdram, &dcr_write_sdram);
> + s, &dcr_read_sdram, &dcr_write_sdram);
> ppc_dcr_register(env, SDRAM_PLBADDUHB,
> - sdram, &dcr_read_sdram, &dcr_write_sdram);
> + s, &dcr_read_sdram, &dcr_write_sdram);
> }
>
> /*****************************************************************************/
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH v3 13/20] ppc4xx_sdram: Rename functions to prevent name clashes
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (11 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 12/20] ppc440_sdram: Rename local variable for readibility BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 14/20] ppc440_sdram: Move RAM size check to ppc440_sdram_init BALATON Zoltan
` (7 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Rename functions to avoid name clashes when moving the DDR2 controller
model currently called ppc440_sdram to ppc4xx_devs. This also more
clearly shows which function belongs to which model.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc440_uc.c | 69 ++++++++++++++++++++++----------------------
hw/ppc/ppc4xx_devs.c | 44 ++++++++++++++--------------
2 files changed, 57 insertions(+), 56 deletions(-)
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index d8a7947196..565bfffc22 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -502,7 +502,7 @@ enum {
SDRAM_PLBADDUHB = 0x50,
};
-static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
+static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -547,12 +547,12 @@ static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
return bcr;
}
-static inline hwaddr sdram_base(uint32_t bcr)
+static inline hwaddr sdram_ddr2_base(uint32_t bcr)
{
return (bcr & 0xffe00000) << 2;
}
-static uint64_t sdram_size(uint32_t bcr)
+static uint64_t sdram_ddr2_size(uint32_t bcr)
{
uint64_t size;
int sh;
@@ -578,50 +578,51 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
object_unparent(OBJECT(&bank->container));
}
-static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
- uint32_t bcr, int enabled)
+static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
+ uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* First unmap RAM if enabled */
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+ trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
+ sdram_ddr2_size(sdram->bank[i].bcr));
sdram_bank_unmap(&sdram->bank[i]);
}
sdram->bank[i].bcr = bcr & 0xffe0ffc1;
- sdram->bank[i].base = sdram_base(bcr);
- sdram->bank[i].size = sdram_size(bcr);
+ sdram->bank[i].base = sdram_ddr2_base(bcr);
+ sdram->bank[i].size = sdram_ddr2_size(bcr);
if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
+ trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr));
sdram_bank_map(&sdram->bank[i]);
}
}
-static void sdram_map_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size) {
- sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
+ sdram_ddr2_set_bcr(sdram, i,
+ sdram_ddr2_bcr(sdram->bank[i].base,
sdram->bank[i].size), 1);
} else {
- sdram_set_bcr(sdram, i, 0, 0);
+ sdram_ddr2_set_bcr(sdram, i, 0, 0);
}
}
}
-static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size) {
- sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
+ sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
}
}
}
-static uint32_t dcr_read_sdram(void *opaque, int dcrn)
+static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
ppc440_sdram_t *sdram = opaque;
uint32_t ret = 0;
@@ -632,8 +633,8 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
case SDRAM_R2BAS:
case SDRAM_R3BAS:
if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
- ret = sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
- sdram->bank[dcrn - SDRAM_R0BAS].size);
+ ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
+ sdram->bank[dcrn - SDRAM_R0BAS].size);
}
break;
case SDRAM_CONF1HB:
@@ -674,7 +675,7 @@ static uint32_t dcr_read_sdram(void *opaque, int dcrn)
return ret;
}
-static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
+static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
ppc440_sdram_t *sdram = opaque;
@@ -700,12 +701,12 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
if (!(sdram->mcopt2 & BIT(27)) && (val & BIT(27))) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_map_bcr(sdram);
+ sdram_ddr2_map_bcr(sdram);
sdram->mcopt2 |= BIT(27);
} else if ((sdram->mcopt2 & BIT(27)) && !(val & BIT(27))) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_unmap_bcr(sdram);
+ sdram_ddr2_unmap_bcr(sdram);
sdram->mcopt2 &= ~BIT(27);
}
break;
@@ -718,7 +719,7 @@ static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
}
}
-static void sdram_reset(void *opaque)
+static void sdram_ddr2_reset(void *opaque)
{
ppc440_sdram_t *sdram = opaque;
@@ -739,30 +740,30 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
s->bank[i].base = ram_banks[i].base;
s->bank[i].size = ram_banks[i].size;
}
- qemu_register_reset(&sdram_reset, s);
+ qemu_register_reset(&sdram_ddr2_reset, s);
ppc_dcr_register(env, SDRAM0_CFGADDR,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM0_CFGDATA,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R0BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R1BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R2BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_R3BAS,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_CONF1HB,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_PLBADDULL,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_CONF1LL,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_CONFPATHB,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
ppc_dcr_register(env, SDRAM_PLBADDUHB,
- s, &dcr_read_sdram, &dcr_write_sdram);
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
}
/*****************************************************************************/
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index bfe7b2d3a6..7655967351 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -81,12 +81,12 @@ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
return bcr;
}
-static inline hwaddr sdram_base(uint32_t bcr)
+static inline hwaddr sdram_ddr_base(uint32_t bcr)
{
return bcr & 0xFF800000;
}
-static target_ulong sdram_size(uint32_t bcr)
+static target_ulong sdram_ddr_size(uint32_t bcr)
{
target_ulong size;
int sh;
@@ -101,13 +101,13 @@ static target_ulong sdram_size(uint32_t bcr)
return size;
}
-static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
- uint32_t bcr, int enabled)
+static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
+ uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
/* Unmap RAM */
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+ trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
+ sdram_ddr_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
&sdram->bank[i].container);
memory_region_del_subregion(&sdram->bank[i].container,
@@ -116,38 +116,38 @@ static void sdram_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
}
sdram->bank[i].bcr = bcr & 0xFFDEE001;
if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
+ trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr));
memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
- sdram_size(bcr));
+ sdram_ddr_size(bcr));
memory_region_add_subregion(&sdram->bank[i].container, 0,
&sdram->bank[i].ram);
memory_region_add_subregion(get_system_memory(),
- sdram_base(bcr),
+ sdram_ddr_base(bcr),
&sdram->bank[i].container);
}
}
-static void sdram_map_bcr(Ppc4xxSdramDdrState *sdram)
+static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
if (sdram->bank[i].size != 0) {
- sdram_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
+ sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
} else {
- sdram_set_bcr(sdram, i, 0, 0);
+ sdram_ddr_set_bcr(sdram, i, 0, 0);
}
}
}
-static void sdram_unmap_bcr(Ppc4xxSdramDdrState *sdram)
+static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
{
int i;
for (i = 0; i < sdram->nbanks; i++) {
- trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
- sdram_size(sdram->bank[i].bcr));
+ trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
+ sdram_ddr_size(sdram->bank[i].bcr));
memory_region_del_subregion(get_system_memory(),
&sdram->bank[i].ram);
}
@@ -244,12 +244,12 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_map_bcr(sdram);
+ sdram_ddr_map_bcr(sdram);
sdram->status &= ~0x80000000;
} else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_unmap_bcr(sdram);
+ sdram_ddr_unmap_bcr(sdram);
sdram->status |= 0x80000000;
}
if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) {
@@ -269,16 +269,16 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
sdram->pmit = (val & 0xF8000000) | 0x07C00000;
break;
case 0x40: /* SDRAM_B0CR */
- sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
break;
case 0x44: /* SDRAM_B1CR */
- sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
break;
case 0x48: /* SDRAM_B2CR */
- sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
break;
case 0x4C: /* SDRAM_B3CR */
- sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
break;
case 0x80: /* SDRAM_TR */
sdram->tr = val & 0x018FC01F;
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v3 14/20] ppc440_sdram: Move RAM size check to ppc440_sdram_init
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (12 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 13/20] ppc4xx_sdram: Rename functions to prevent name clashes BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 15/20] ppc440_sdram: QOM'ify BALATON Zoltan
` (6 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Move the check for valid memory sizes from board to sdram controller
init. Board now only checks for additional restrictions imposed by
firmware then sdram init checks for valid sizes for SoC.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc440.h | 4 ++--
hw/ppc/ppc440_uc.c | 15 +++++++--------
hw/ppc/sam460ex.c | 32 +++++++++++++++++---------------
3 files changed, 26 insertions(+), 25 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index 01d76b8000..29f6f14ed7 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -11,13 +11,13 @@
#ifndef PPC440_H
#define PPC440_H
-#include "hw/ppc/ppc4xx.h"
+#include "hw/ppc/ppc.h"
void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks);
+ MemoryRegion *ram);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 565bfffc22..f48eba215a 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -486,7 +486,7 @@ void ppc4xx_sdr_init(CPUPPCState *env)
typedef struct ppc440_sdram_t {
uint32_t addr;
uint32_t mcopt2;
- int nbanks;
+ int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
Ppc4xxSdramBank bank[4];
} ppc440_sdram_t;
@@ -728,18 +728,17 @@ static void sdram_ddr2_reset(void *opaque)
}
void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- Ppc4xxSdramBank *ram_banks)
+ MemoryRegion *ram)
{
ppc440_sdram_t *s;
- int i;
+ const ram_addr_t valid_bank_sizes[] = {
+ 4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
+ 32 * MiB, 16 * MiB, 8 * MiB, 0
+ };
s = g_malloc0(sizeof(*s));
s->nbanks = nbanks;
- for (i = 0; i < nbanks; i++) {
- s->bank[i].ram = ram_banks[i].ram;
- s->bank[i].base = ram_banks[i].base;
- s->bank[i].size = ram_banks[i].size;
- }
+ ppc4xx_sdram_banks(ram, s->nbanks, s->bank, valid_bank_sizes);
qemu_register_reset(&sdram_ddr2_reset, s);
ppc_dcr_register(env, SDRAM0_CFGADDR,
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index dac329d482..9b850808a3 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -74,13 +74,6 @@
#define EBC_FREQ 115000000
#define UART_FREQ 11059200
-/* The SoC could also handle 4 GiB but firmware does not work with that. */
-/* Maybe it overflows a signed 32 bit number somewhere? */
-static const ram_addr_t ppc460ex_sdram_bank_sizes[] = {
- 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
- 32 * MiB, 0
-};
-
struct boot_info {
uint32_t dt_base;
uint32_t dt_size;
@@ -273,7 +266,6 @@ static void sam460ex_init(MachineState *machine)
{
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
- Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank, 1);
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
DeviceState *uic[4];
int i;
@@ -340,12 +332,22 @@ static void sam460ex_init(MachineState *machine)
}
/* SDRAM controller */
- /* put all RAM on first bank because board has one slot
- * and firmware only checks that */
- ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes);
-
+ /* The SoC could also handle 4 GiB but firmware does not work with that. */
+ if (machine->ram_size > 2 * GiB) {
+ error_report("Memory over 2 GiB is not supported");
+ exit(1);
+ }
+ /* Firmware needs at least 64 MiB */
+ if (machine->ram_size < 64 * MiB) {
+ error_report("Memory below 64 MiB is not supported");
+ exit(1);
+ }
+ /*
+ * Put all RAM on first bank because board has one slot
+ * and firmware only checks that
+ */
+ ppc440_sdram_init(env, 1, machine->ram);
/* FIXME: does 460EX have ECC interrupts? */
- ppc440_sdram_init(env, 1, ram_banks);
/* Enable SDRAM memory regions as we may boot without firmware */
if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21) ||
ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000)) {
@@ -358,8 +360,8 @@ static void sam460ex_init(MachineState *machine)
qdev_get_gpio_in(uic[0], 2));
i2c = PPC4xx_I2C(dev)->bus;
/* SPD EEPROM on RAM module */
- spd_data = spd_data_generate(ram_banks->size < 128 * MiB ? DDR : DDR2,
- ram_banks->size);
+ spd_data = spd_data_generate(machine->ram_size < 128 * MiB ? DDR : DDR2,
+ machine->ram_size);
spd_data[20] = 4; /* SO-DIMM module */
smbus_eeprom_init_one(i2c, 0x50, spd_data);
/* RTC */
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v3 15/20] ppc440_sdram: QOM'ify
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (13 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 14/20] ppc440_sdram: Move RAM size check to ppc440_sdram_init BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 16/20] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together BALATON Zoltan
` (5 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Change the ppc440_sdram model to a QOM class derived from the
PPC4xx-dcr-device and name it ppc4xx-sdram-ddr2. This is mostly
modelling the DDR2 SDRAM controller found in the 460EX (used on the
sam460ex board). Newer SoCs (regardless of their PPC core, e.g. 405EX)
may have this controller but we only emulate enough of it for the
sam460ex u-boot firmware.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc440.h | 2 -
hw/ppc/ppc440_uc.c | 115 +++++++++++++++++++++++++---------------
hw/ppc/sam460ex.c | 7 ++-
include/hw/ppc/ppc4xx.h | 14 +++++
4 files changed, 91 insertions(+), 47 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index 29f6f14ed7..7c24db8504 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -16,8 +16,6 @@
void ppc4xx_l2sram_init(CPUPPCState *env);
void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
-void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(CPUPPCState *env);
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index f48eba215a..114c1a1b1c 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -483,13 +483,6 @@ void ppc4xx_sdr_init(CPUPPCState *env)
/*****************************************************************************/
/* SDRAM controller */
-typedef struct ppc440_sdram_t {
- uint32_t addr;
- uint32_t mcopt2;
- int nbanks; /* Banks to use from the 4, e.g. when board has less slots */
- Ppc4xxSdramBank bank[4];
-} ppc440_sdram_t;
-
enum {
SDRAM_R0BAS = 0x40,
SDRAM_R1BAS,
@@ -578,7 +571,7 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
object_unparent(OBJECT(&bank->container));
}
-static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
+static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i,
uint32_t bcr, int enabled)
{
if (sdram->bank[i].bcr & 1) {
@@ -596,7 +589,7 @@ static void sdram_ddr2_set_bcr(ppc440_sdram_t *sdram, int i,
}
}
-static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram)
{
int i;
@@ -611,7 +604,7 @@ static void sdram_ddr2_map_bcr(ppc440_sdram_t *sdram)
}
}
-static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
+static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
{
int i;
@@ -624,7 +617,7 @@ static void sdram_ddr2_unmap_bcr(ppc440_sdram_t *sdram)
static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
- ppc440_sdram_t *sdram = opaque;
+ Ppc4xxSdramDdr2State *sdram = opaque;
uint32_t ret = 0;
switch (dcrn) {
@@ -677,7 +670,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
- ppc440_sdram_t *sdram = opaque;
+ Ppc4xxSdramDdr2State *sdram = opaque;
switch (dcrn) {
case SDRAM_R0BAS:
@@ -719,52 +712,86 @@ static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
}
}
-static void sdram_ddr2_reset(void *opaque)
+static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
{
- ppc440_sdram_t *sdram = opaque;
+ Ppc4xxSdramDdr2State *sdram = PPC4xx_SDRAM_DDR2(dev);
sdram->addr = 0;
sdram->mcopt2 = 0;
}
-void ppc440_sdram_init(CPUPPCState *env, int nbanks,
- MemoryRegion *ram)
+static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
{
- ppc440_sdram_t *s;
+ Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
const ram_addr_t valid_bank_sizes[] = {
4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
32 * MiB, 16 * MiB, 8 * MiB, 0
};
- s = g_malloc0(sizeof(*s));
- s->nbanks = nbanks;
- ppc4xx_sdram_banks(ram, s->nbanks, s->bank, valid_bank_sizes);
- qemu_register_reset(&sdram_ddr2_reset, s);
- ppc_dcr_register(env, SDRAM0_CFGADDR,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM0_CFGDATA,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
-
- ppc_dcr_register(env, SDRAM_R0BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_R1BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_R2BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_R3BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_CONF1HB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_PLBADDULL,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_CONF1LL,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_CONFPATHB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc_dcr_register(env, SDRAM_PLBADDUHB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ if (s->nbanks < 1 || s->nbanks > 4) {
+ error_setg(errp, "Invalid number of RAM banks");
+ return;
+ }
+ if (!s->dram_mr) {
+ error_setg(errp, "Missing dram memory region");
+ return;
+ }
+ ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+
+ ppc4xx_dcr_register(dcr, SDRAM_R0BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R1BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R2BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R3BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONF1HB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONF1LL,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+}
+
+static Property ppc4xx_sdram_ddr2_props[] = {
+ DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_sdram_ddr2_realize;
+ dc->reset = ppc4xx_sdram_ddr2_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc4xx_sdram_ddr2_props);
}
+static const TypeInfo ppc4xx_types[] = {
+ {
+ .name = TYPE_PPC4xx_SDRAM_DDR2,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc4xxSdramDdr2State),
+ .class_init = ppc4xx_sdram_ddr2_class_init,
+ }
+};
+DEFINE_TYPES(ppc4xx_types)
+
/*****************************************************************************/
/* PLB to AHB bridge */
enum {
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 9b850808a3..ea06b099b2 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -342,11 +342,16 @@ static void sam460ex_init(MachineState *machine)
error_report("Memory below 64 MiB is not supported");
exit(1);
}
+ dev = qdev_new(TYPE_PPC4xx_SDRAM_DDR2);
+ object_property_set_link(OBJECT(dev), "dram", OBJECT(machine->ram),
+ &error_abort);
/*
* Put all RAM on first bank because board has one slot
* and firmware only checks that
*/
- ppc440_sdram_init(env, 1, machine->ram);
+ object_property_set_int(OBJECT(dev), "nbanks", 1, &error_abort);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
/* FIXME: does 460EX have ECC interrupts? */
/* Enable SDRAM memory regions as we may boot without firmware */
if (ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21) ||
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 20d0cdde8a..7d3cfa7ad6 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -139,4 +139,18 @@ struct Ppc4xxSdramDdrState {
uint32_t eccesr;
};
+/* SDRAM DDR2 controller */
+#define TYPE_PPC4xx_SDRAM_DDR2 "ppc4xx-sdram-ddr2"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdr2State, PPC4xx_SDRAM_DDR2);
+struct Ppc4xxSdramDdr2State {
+ Ppc4xxDcrDeviceState parent_obj;
+
+ MemoryRegion *dram_mr;
+ uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */
+ Ppc4xxSdramBank bank[4];
+
+ uint32_t addr;
+ uint32_t mcopt2;
+};
+
#endif /* PPC4XX_H */
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v3 16/20] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (14 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 15/20] ppc440_sdram: QOM'ify BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 17/20] ppc4xx_sdram: Use hwaddr for memory bank size BALATON Zoltan
` (4 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Move the PPC4xx DDR and DDR2 SDRAM contrller models into a new file
called ppc4xx_sdram to separate from other device models and put them
in one place allowing sharing some code between them.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/meson.build | 3 +-
hw/ppc/ppc440_uc.c | 321 -----------------
hw/ppc/ppc4xx_devs.c | 403 ---------------------
hw/ppc/ppc4xx_sdram.c | 752 ++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/ppc4xx.h | 34 +-
5 files changed, 771 insertions(+), 742 deletions(-)
create mode 100644 hw/ppc/ppc4xx_sdram.c
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index 62801923f3..74720dd1e1 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -59,8 +59,9 @@ ppc_ss.add(when: 'CONFIG_PPC440', if_true: files(
'ppc440_bamboo.c',
'ppc440_pcix.c', 'ppc440_uc.c'))
ppc_ss.add(when: 'CONFIG_PPC4XX', if_true: files(
+ 'ppc4xx_devs.c',
'ppc4xx_pci.c',
- 'ppc4xx_devs.c'))
+ 'ppc4xx_sdram.c'))
ppc_ss.add(when: 'CONFIG_SAM460EX', if_true: files('sam460ex.c'))
# PReP
ppc_ss.add(when: 'CONFIG_PREP', if_true: files('prep.c'))
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 114c1a1b1c..651263926e 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -10,20 +10,14 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
-#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qemu/log.h"
-#include "qemu/module.h"
#include "hw/irq.h"
-#include "exec/memory.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/qdev-properties.h"
#include "hw/pci/pci.h"
-#include "sysemu/block-backend.h"
#include "sysemu/reset.h"
#include "ppc440.h"
-#include "qom/object.h"
-#include "trace.h"
/*****************************************************************************/
/* L2 Cache as SRAM */
@@ -379,10 +373,6 @@ enum {
PESDR1_RSTSTA = 0x365,
};
-#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29)
-#define SDR0_DDR0_DDRM_DDR1 0x20000000
-#define SDR0_DDR0_DDRM_DDR2 0x40000000
-
static uint32_t dcr_read_sdr(void *opaque, int dcrn)
{
ppc4xx_sdr_t *sdr = opaque;
@@ -481,317 +471,6 @@ void ppc4xx_sdr_init(CPUPPCState *env)
sdr, &dcr_read_sdr, &dcr_write_sdr);
}
-/*****************************************************************************/
-/* SDRAM controller */
-enum {
- SDRAM_R0BAS = 0x40,
- SDRAM_R1BAS,
- SDRAM_R2BAS,
- SDRAM_R3BAS,
- SDRAM_CONF1HB = 0x45,
- SDRAM_PLBADDULL = 0x4a,
- SDRAM_CONF1LL = 0x4b,
- SDRAM_CONFPATHB = 0x4f,
- SDRAM_PLBADDUHB = 0x50,
-};
-
-static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
-{
- uint32_t bcr;
-
- switch (ram_size) {
- case (8 * MiB):
- bcr = 0xffc0;
- break;
- case (16 * MiB):
- bcr = 0xff80;
- break;
- case (32 * MiB):
- bcr = 0xff00;
- break;
- case (64 * MiB):
- bcr = 0xfe00;
- break;
- case (128 * MiB):
- bcr = 0xfc00;
- break;
- case (256 * MiB):
- bcr = 0xf800;
- break;
- case (512 * MiB):
- bcr = 0xf000;
- break;
- case (1 * GiB):
- bcr = 0xe000;
- break;
- case (2 * GiB):
- bcr = 0xc000;
- break;
- case (4 * GiB):
- bcr = 0x8000;
- break;
- default:
- error_report("invalid RAM size " TARGET_FMT_plx, ram_size);
- return 0;
- }
- bcr |= ram_base >> 2 & 0xffe00000;
- bcr |= 1;
-
- return bcr;
-}
-
-static inline hwaddr sdram_ddr2_base(uint32_t bcr)
-{
- return (bcr & 0xffe00000) << 2;
-}
-
-static uint64_t sdram_ddr2_size(uint32_t bcr)
-{
- uint64_t size;
- int sh;
-
- sh = 1024 - ((bcr >> 6) & 0x3ff);
- size = 8 * MiB * sh;
-
- return size;
-}
-
-static void sdram_bank_map(Ppc4xxSdramBank *bank)
-{
- memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
- memory_region_add_subregion(&bank->container, 0, &bank->ram);
- memory_region_add_subregion(get_system_memory(), bank->base,
- &bank->container);
-}
-
-static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
-{
- memory_region_del_subregion(get_system_memory(), &bank->container);
- memory_region_del_subregion(&bank->container, &bank->ram);
- object_unparent(OBJECT(&bank->container));
-}
-
-static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i,
- uint32_t bcr, int enabled)
-{
- if (sdram->bank[i].bcr & 1) {
- /* First unmap RAM if enabled */
- trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
- sdram_ddr2_size(sdram->bank[i].bcr));
- sdram_bank_unmap(&sdram->bank[i]);
- }
- sdram->bank[i].bcr = bcr & 0xffe0ffc1;
- sdram->bank[i].base = sdram_ddr2_base(bcr);
- sdram->bank[i].size = sdram_ddr2_size(bcr);
- if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr));
- sdram_bank_map(&sdram->bank[i]);
- }
-}
-
-static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size) {
- sdram_ddr2_set_bcr(sdram, i,
- sdram_ddr2_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
- } else {
- sdram_ddr2_set_bcr(sdram, i, 0, 0);
- }
- }
-}
-
-static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size) {
- sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
- }
- }
-}
-
-static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
-{
- Ppc4xxSdramDdr2State *sdram = opaque;
- uint32_t ret = 0;
-
- switch (dcrn) {
- case SDRAM_R0BAS:
- case SDRAM_R1BAS:
- case SDRAM_R2BAS:
- case SDRAM_R3BAS:
- if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
- ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
- sdram->bank[dcrn - SDRAM_R0BAS].size);
- }
- break;
- case SDRAM_CONF1HB:
- case SDRAM_CONF1LL:
- case SDRAM_CONFPATHB:
- case SDRAM_PLBADDULL:
- case SDRAM_PLBADDUHB:
- break;
- case SDRAM0_CFGADDR:
- ret = sdram->addr;
- break;
- case SDRAM0_CFGDATA:
- switch (sdram->addr) {
- case 0x14: /* SDRAM_MCSTAT (405EX) */
- case 0x1F:
- ret = 0x80000000;
- break;
- case 0x21: /* SDRAM_MCOPT2 */
- ret = sdram->mcopt2;
- break;
- case 0x40: /* SDRAM_MB0CF */
- ret = 0x00008001;
- break;
- case 0x7A: /* SDRAM_DLCR */
- ret = 0x02000000;
- break;
- case 0xE1: /* SDR0_DDR0 */
- ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
-
- return ret;
-}
-
-static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
-{
- Ppc4xxSdramDdr2State *sdram = opaque;
-
- switch (dcrn) {
- case SDRAM_R0BAS:
- case SDRAM_R1BAS:
- case SDRAM_R2BAS:
- case SDRAM_R3BAS:
- case SDRAM_CONF1HB:
- case SDRAM_CONF1LL:
- case SDRAM_CONFPATHB:
- case SDRAM_PLBADDULL:
- case SDRAM_PLBADDUHB:
- break;
- case SDRAM0_CFGADDR:
- sdram->addr = val;
- break;
- case SDRAM0_CFGDATA:
- switch (sdram->addr) {
- case 0x00: /* B0CR */
- break;
- case 0x21: /* SDRAM_MCOPT2 */
- if (!(sdram->mcopt2 & BIT(27)) && (val & BIT(27))) {
- trace_ppc4xx_sdram_enable("enable");
- /* validate all RAM mappings */
- sdram_ddr2_map_bcr(sdram);
- sdram->mcopt2 |= BIT(27);
- } else if ((sdram->mcopt2 & BIT(27)) && !(val & BIT(27))) {
- trace_ppc4xx_sdram_enable("disable");
- /* invalidate all RAM mappings */
- sdram_ddr2_unmap_bcr(sdram);
- sdram->mcopt2 &= ~BIT(27);
- }
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
-}
-
-static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
-{
- Ppc4xxSdramDdr2State *sdram = PPC4xx_SDRAM_DDR2(dev);
-
- sdram->addr = 0;
- sdram->mcopt2 = 0;
-}
-
-static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
-{
- Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
- Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
- const ram_addr_t valid_bank_sizes[] = {
- 4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
- 32 * MiB, 16 * MiB, 8 * MiB, 0
- };
-
- if (s->nbanks < 1 || s->nbanks > 4) {
- error_setg(errp, "Invalid number of RAM banks");
- return;
- }
- if (!s->dram_mr) {
- error_setg(errp, "Missing dram memory region");
- return;
- }
- ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
-
- ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
-
- ppc4xx_dcr_register(dcr, SDRAM_R0BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_R1BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_R2BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_R3BAS,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_CONF1HB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_CONF1LL,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB,
- s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
-}
-
-static Property ppc4xx_sdram_ddr2_props[] = {
- DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION,
- MemoryRegion *),
- DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4),
- DEFINE_PROP_END_OF_LIST(),
-};
-
-static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc4xx_sdram_ddr2_realize;
- dc->reset = ppc4xx_sdram_ddr2_reset;
- /* Reason: only works as function of a ppc4xx SoC */
- dc->user_creatable = false;
- device_class_set_props(dc, ppc4xx_sdram_ddr2_props);
-}
-
-static const TypeInfo ppc4xx_types[] = {
- {
- .name = TYPE_PPC4xx_SDRAM_DDR2,
- .parent = TYPE_PPC4xx_DCR_DEVICE,
- .instance_size = sizeof(Ppc4xxSdramDdr2State),
- .class_init = ppc4xx_sdram_ddr2_class_init,
- }
-};
-DEFINE_TYPES(ppc4xx_types)
-
/*****************************************************************************/
/* PLB to AHB bridge */
enum {
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 7655967351..c1d111465d 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -23,408 +23,10 @@
*/
#include "qemu/osdep.h"
-#include "qemu/units.h"
-#include "sysemu/reset.h"
#include "cpu.h"
-#include "hw/irq.h"
-#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/qdev-properties.h"
-#include "qemu/log.h"
-#include "exec/address-spaces.h"
-#include "qemu/error-report.h"
#include "qapi/error.h"
-#include "trace.h"
-
-/*****************************************************************************/
-/* SDRAM controller */
-/*
- * XXX: TOFIX: some patches have made this code become inconsistent:
- * there are type inconsistencies, mixing hwaddr, target_ulong
- * and uint32_t
- */
-static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
-{
- uint32_t bcr;
-
- switch (ram_size) {
- case 4 * MiB:
- bcr = 0;
- break;
- case 8 * MiB:
- bcr = 0x20000;
- break;
- case 16 * MiB:
- bcr = 0x40000;
- break;
- case 32 * MiB:
- bcr = 0x60000;
- break;
- case 64 * MiB:
- bcr = 0x80000;
- break;
- case 128 * MiB:
- bcr = 0xA0000;
- break;
- case 256 * MiB:
- bcr = 0xC0000;
- break;
- default:
- qemu_log_mask(LOG_GUEST_ERROR,
- "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
- ram_size);
- return 0;
- }
- bcr |= ram_base & 0xFF800000;
- bcr |= 1;
-
- return bcr;
-}
-
-static inline hwaddr sdram_ddr_base(uint32_t bcr)
-{
- return bcr & 0xFF800000;
-}
-
-static target_ulong sdram_ddr_size(uint32_t bcr)
-{
- target_ulong size;
- int sh;
-
- sh = (bcr >> 17) & 0x7;
- if (sh == 7) {
- size = -1;
- } else {
- size = (4 * MiB) << sh;
- }
-
- return size;
-}
-
-static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
- uint32_t bcr, int enabled)
-{
- if (sdram->bank[i].bcr & 1) {
- /* Unmap RAM */
- trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
- sdram_ddr_size(sdram->bank[i].bcr));
- memory_region_del_subregion(get_system_memory(),
- &sdram->bank[i].container);
- memory_region_del_subregion(&sdram->bank[i].container,
- &sdram->bank[i].ram);
- object_unparent(OBJECT(&sdram->bank[i].container));
- }
- sdram->bank[i].bcr = bcr & 0xFFDEE001;
- if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr));
- memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
- sdram_ddr_size(bcr));
- memory_region_add_subregion(&sdram->bank[i].container, 0,
- &sdram->bank[i].ram);
- memory_region_add_subregion(get_system_memory(),
- sdram_ddr_base(bcr),
- &sdram->bank[i].container);
- }
-}
-
-static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size != 0) {
- sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
- } else {
- sdram_ddr_set_bcr(sdram, i, 0, 0);
- }
- }
-}
-
-static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
- sdram_ddr_size(sdram->bank[i].bcr));
- memory_region_del_subregion(get_system_memory(),
- &sdram->bank[i].ram);
- }
-}
-
-static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
-{
- Ppc4xxSdramDdrState *sdram = opaque;
- uint32_t ret;
-
- switch (dcrn) {
- case SDRAM0_CFGADDR:
- ret = sdram->addr;
- break;
- case SDRAM0_CFGDATA:
- switch (sdram->addr) {
- case 0x00: /* SDRAM_BESR0 */
- ret = sdram->besr0;
- break;
- case 0x08: /* SDRAM_BESR1 */
- ret = sdram->besr1;
- break;
- case 0x10: /* SDRAM_BEAR */
- ret = sdram->bear;
- break;
- case 0x20: /* SDRAM_CFG */
- ret = sdram->cfg;
- break;
- case 0x24: /* SDRAM_STATUS */
- ret = sdram->status;
- break;
- case 0x30: /* SDRAM_RTR */
- ret = sdram->rtr;
- break;
- case 0x34: /* SDRAM_PMIT */
- ret = sdram->pmit;
- break;
- case 0x40: /* SDRAM_B0CR */
- ret = sdram->bank[0].bcr;
- break;
- case 0x44: /* SDRAM_B1CR */
- ret = sdram->bank[1].bcr;
- break;
- case 0x48: /* SDRAM_B2CR */
- ret = sdram->bank[2].bcr;
- break;
- case 0x4C: /* SDRAM_B3CR */
- ret = sdram->bank[3].bcr;
- break;
- case 0x80: /* SDRAM_TR */
- ret = -1; /* ? */
- break;
- case 0x94: /* SDRAM_ECCCFG */
- ret = sdram->ecccfg;
- break;
- case 0x98: /* SDRAM_ECCESR */
- ret = sdram->eccesr;
- break;
- default: /* Error */
- ret = -1;
- break;
- }
- break;
- default:
- /* Avoid gcc warning */
- ret = 0;
- break;
- }
-
- return ret;
-}
-
-static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
-{
- Ppc4xxSdramDdrState *sdram = opaque;
-
- switch (dcrn) {
- case SDRAM0_CFGADDR:
- sdram->addr = val;
- break;
- case SDRAM0_CFGDATA:
- switch (sdram->addr) {
- case 0x00: /* SDRAM_BESR0 */
- sdram->besr0 &= ~val;
- break;
- case 0x08: /* SDRAM_BESR1 */
- sdram->besr1 &= ~val;
- break;
- case 0x10: /* SDRAM_BEAR */
- sdram->bear = val;
- break;
- case 0x20: /* SDRAM_CFG */
- val &= 0xFFE00000;
- if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
- trace_ppc4xx_sdram_enable("enable");
- /* validate all RAM mappings */
- sdram_ddr_map_bcr(sdram);
- sdram->status &= ~0x80000000;
- } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
- trace_ppc4xx_sdram_enable("disable");
- /* invalidate all RAM mappings */
- sdram_ddr_unmap_bcr(sdram);
- sdram->status |= 0x80000000;
- }
- if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) {
- sdram->status |= 0x40000000;
- } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) {
- sdram->status &= ~0x40000000;
- }
- sdram->cfg = val;
- break;
- case 0x24: /* SDRAM_STATUS */
- /* Read-only register */
- break;
- case 0x30: /* SDRAM_RTR */
- sdram->rtr = val & 0x3FF80000;
- break;
- case 0x34: /* SDRAM_PMIT */
- sdram->pmit = (val & 0xF8000000) | 0x07C00000;
- break;
- case 0x40: /* SDRAM_B0CR */
- sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
- break;
- case 0x44: /* SDRAM_B1CR */
- sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
- break;
- case 0x48: /* SDRAM_B2CR */
- sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
- break;
- case 0x4C: /* SDRAM_B3CR */
- sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
- break;
- case 0x80: /* SDRAM_TR */
- sdram->tr = val & 0x018FC01F;
- break;
- case 0x94: /* SDRAM_ECCCFG */
- sdram->ecccfg = val & 0x00F00000;
- break;
- case 0x98: /* SDRAM_ECCESR */
- val &= 0xFFF0F000;
- if (sdram->eccesr == 0 && val != 0) {
- qemu_irq_raise(sdram->irq);
- } else if (sdram->eccesr != 0 && val == 0) {
- qemu_irq_lower(sdram->irq);
- }
- sdram->eccesr = val;
- break;
- default: /* Error */
- break;
- }
- break;
- }
-}
-
-static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
-{
- Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
-
- sdram->addr = 0;
- sdram->bear = 0;
- sdram->besr0 = 0; /* No error */
- sdram->besr1 = 0; /* No error */
- sdram->cfg = 0;
- sdram->ecccfg = 0; /* No ECC */
- sdram->eccesr = 0; /* No error */
- sdram->pmit = 0x07C00000;
- sdram->rtr = 0x05F00000;
- sdram->tr = 0x00854009;
- /* We pre-initialize RAM banks */
- sdram->status = 0;
- sdram->cfg = 0x00800000;
-}
-
-static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
-{
- Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
- Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
- const ram_addr_t valid_bank_sizes[] = {
- 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
- };
-
- if (s->nbanks < 1 || s->nbanks > 4) {
- error_setg(errp, "Invalid number of RAM banks");
- return;
- }
- if (!s->dram_mr) {
- error_setg(errp, "Missing dram memory region");
- return;
- }
- ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
-
- sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
-
- ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
- s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
- ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
- s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
-}
-
-static Property ppc4xx_sdram_ddr_props[] = {
- DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION,
- MemoryRegion *),
- DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4),
- DEFINE_PROP_END_OF_LIST(),
-};
-
-static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = ppc4xx_sdram_ddr_realize;
- dc->reset = ppc4xx_sdram_ddr_reset;
- /* Reason: only works as function of a ppc4xx SoC */
- dc->user_creatable = false;
- device_class_set_props(dc, ppc4xx_sdram_ddr_props);
-}
-
-/*
- * Split RAM between SDRAM banks.
- *
- * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
- * and must be 0-terminated.
- *
- * The 4xx SDRAM controller supports a small number of banks, and each bank
- * must be one of a small set of sizes. The number of banks and the supported
- * sizes varies by SoC.
- */
-void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
- Ppc4xxSdramBank ram_banks[],
- const ram_addr_t sdram_bank_sizes[])
-{
- ram_addr_t size_left = memory_region_size(ram);
- ram_addr_t base = 0;
- ram_addr_t bank_size;
- int i;
- int j;
-
- for (i = 0; i < nr_banks; i++) {
- for (j = 0; sdram_bank_sizes[j] != 0; j++) {
- bank_size = sdram_bank_sizes[j];
- if (bank_size <= size_left) {
- char name[32];
-
- ram_banks[i].base = base;
- ram_banks[i].size = bank_size;
- base += bank_size;
- size_left -= bank_size;
- snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
- memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram,
- ram_banks[i].base, ram_banks[i].size);
- break;
- }
- }
- if (!size_left) {
- /* No need to use the remaining banks. */
- break;
- }
- }
-
- if (size_left) {
- ram_addr_t used_size = memory_region_size(ram) - size_left;
- GString *s = g_string_new(NULL);
-
- for (i = 0; sdram_bank_sizes[i]; i++) {
- g_string_append_printf(s, "%" PRIi64 "%s",
- sdram_bank_sizes[i] / MiB,
- sdram_bank_sizes[i + 1] ? ", " : "");
- }
- error_report("at most %d bank%s of %s MiB each supported",
- nr_banks, nr_banks == 1 ? "" : "s", s->str);
- error_printf("Possible valid RAM size: %" PRIi64 " MiB\n",
- used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
-
- g_string_free(s, true);
- exit(EXIT_FAILURE);
- }
-}
/*****************************************************************************/
/* MAL */
@@ -952,11 +554,6 @@ static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc4xx_types[] = {
{
- .name = TYPE_PPC4xx_SDRAM_DDR,
- .parent = TYPE_PPC4xx_DCR_DEVICE,
- .instance_size = sizeof(Ppc4xxSdramDdrState),
- .class_init = ppc4xx_sdram_ddr_class_init,
- }, {
.name = TYPE_PPC4xx_MAL,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc4xxMalState),
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
new file mode 100644
index 0000000000..bc28d69a26
--- /dev/null
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -0,0 +1,752 @@
+/*
+ * QEMU PowerPC 4xx embedded processors SDRAM controller emulation
+ *
+ * DDR SDRAM controller:
+ * Copyright (c) 2007 Jocelyn Mayer
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * DDR2 SDRAM controller:
+ * Copyright (c) 2012 François Revol
+ * Copyright (c) 2016-2019 BALATON Zoltan
+ *
+ * This work is licensed under the GNU GPL license version 2 or later.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "exec/address-spaces.h" /* get_system_memory() */
+#include "exec/cpu-defs.h" /* target_ulong */
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "hw/ppc/ppc4xx.h"
+#include "trace.h"
+
+/*****************************************************************************/
+/* Shared functions */
+
+/*
+ * Split RAM between SDRAM banks.
+ *
+ * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
+ * and must be 0-terminated.
+ *
+ * The 4xx SDRAM controller supports a small number of banks, and each bank
+ * must be one of a small set of sizes. The number of banks and the supported
+ * sizes varies by SoC.
+ */
+static void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
+ Ppc4xxSdramBank ram_banks[],
+ const ram_addr_t sdram_bank_sizes[])
+{
+ ram_addr_t size_left = memory_region_size(ram);
+ ram_addr_t base = 0;
+ ram_addr_t bank_size;
+ int i;
+ int j;
+
+ for (i = 0; i < nr_banks; i++) {
+ for (j = 0; sdram_bank_sizes[j] != 0; j++) {
+ bank_size = sdram_bank_sizes[j];
+ if (bank_size <= size_left) {
+ char name[32];
+
+ ram_banks[i].base = base;
+ ram_banks[i].size = bank_size;
+ base += bank_size;
+ size_left -= bank_size;
+ snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
+ memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram,
+ ram_banks[i].base, ram_banks[i].size);
+ break;
+ }
+ }
+ if (!size_left) {
+ /* No need to use the remaining banks. */
+ break;
+ }
+ }
+
+ if (size_left) {
+ ram_addr_t used_size = memory_region_size(ram) - size_left;
+ GString *s = g_string_new(NULL);
+
+ for (i = 0; sdram_bank_sizes[i]; i++) {
+ g_string_append_printf(s, "%" PRIi64 "%s",
+ sdram_bank_sizes[i] / MiB,
+ sdram_bank_sizes[i + 1] ? ", " : "");
+ }
+ error_report("at most %d bank%s of %s MiB each supported",
+ nr_banks, nr_banks == 1 ? "" : "s", s->str);
+ error_printf("Possible valid RAM size: %" PRIi64 " MiB\n",
+ used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
+
+ g_string_free(s, true);
+ exit(EXIT_FAILURE);
+ }
+}
+
+static void sdram_bank_map(Ppc4xxSdramBank *bank)
+{
+ memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
+ memory_region_add_subregion(&bank->container, 0, &bank->ram);
+ memory_region_add_subregion(get_system_memory(), bank->base,
+ &bank->container);
+}
+
+static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
+{
+ memory_region_del_subregion(get_system_memory(), &bank->container);
+ memory_region_del_subregion(&bank->container, &bank->ram);
+ object_unparent(OBJECT(&bank->container));
+}
+
+/*****************************************************************************/
+/* DDR SDRAM controller */
+/*
+ * XXX: TOFIX: some patches have made this code become inconsistent:
+ * there are type inconsistencies, mixing hwaddr, target_ulong
+ * and uint32_t
+ */
+static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
+{
+ uint32_t bcr;
+
+ switch (ram_size) {
+ case 4 * MiB:
+ bcr = 0;
+ break;
+ case 8 * MiB:
+ bcr = 0x20000;
+ break;
+ case 16 * MiB:
+ bcr = 0x40000;
+ break;
+ case 32 * MiB:
+ bcr = 0x60000;
+ break;
+ case 64 * MiB:
+ bcr = 0x80000;
+ break;
+ case 128 * MiB:
+ bcr = 0xA0000;
+ break;
+ case 256 * MiB:
+ bcr = 0xC0000;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
+ ram_size);
+ return 0;
+ }
+ bcr |= ram_base & 0xFF800000;
+ bcr |= 1;
+
+ return bcr;
+}
+
+static inline hwaddr sdram_ddr_base(uint32_t bcr)
+{
+ return bcr & 0xFF800000;
+}
+
+static target_ulong sdram_ddr_size(uint32_t bcr)
+{
+ target_ulong size;
+ int sh;
+
+ sh = (bcr >> 17) & 0x7;
+ if (sh == 7) {
+ size = -1;
+ } else {
+ size = (4 * MiB) << sh;
+ }
+
+ return size;
+}
+
+static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
+ uint32_t bcr, int enabled)
+{
+ if (sdram->bank[i].bcr & 1) {
+ /* Unmap RAM */
+ trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
+ sdram_ddr_size(sdram->bank[i].bcr));
+ memory_region_del_subregion(get_system_memory(),
+ &sdram->bank[i].container);
+ memory_region_del_subregion(&sdram->bank[i].container,
+ &sdram->bank[i].ram);
+ object_unparent(OBJECT(&sdram->bank[i].container));
+ }
+ sdram->bank[i].bcr = bcr & 0xFFDEE001;
+ if (enabled && (bcr & 1)) {
+ trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr));
+ memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
+ sdram_ddr_size(bcr));
+ memory_region_add_subregion(&sdram->bank[i].container, 0,
+ &sdram->bank[i].ram);
+ memory_region_add_subregion(get_system_memory(),
+ sdram_ddr_base(bcr),
+ &sdram->bank[i].container);
+ }
+}
+
+static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram)
+{
+ int i;
+
+ for (i = 0; i < sdram->nbanks; i++) {
+ if (sdram->bank[i].size != 0) {
+ sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
+ } else {
+ sdram_ddr_set_bcr(sdram, i, 0, 0);
+ }
+ }
+}
+
+static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
+{
+ int i;
+
+ for (i = 0; i < sdram->nbanks; i++) {
+ trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
+ sdram_ddr_size(sdram->bank[i].bcr));
+ memory_region_del_subregion(get_system_memory(),
+ &sdram->bank[i].ram);
+ }
+}
+
+static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
+{
+ Ppc4xxSdramDdrState *sdram = opaque;
+ uint32_t ret;
+
+ switch (dcrn) {
+ case SDRAM0_CFGADDR:
+ ret = sdram->addr;
+ break;
+ case SDRAM0_CFGDATA:
+ switch (sdram->addr) {
+ case 0x00: /* SDRAM_BESR0 */
+ ret = sdram->besr0;
+ break;
+ case 0x08: /* SDRAM_BESR1 */
+ ret = sdram->besr1;
+ break;
+ case 0x10: /* SDRAM_BEAR */
+ ret = sdram->bear;
+ break;
+ case 0x20: /* SDRAM_CFG */
+ ret = sdram->cfg;
+ break;
+ case 0x24: /* SDRAM_STATUS */
+ ret = sdram->status;
+ break;
+ case 0x30: /* SDRAM_RTR */
+ ret = sdram->rtr;
+ break;
+ case 0x34: /* SDRAM_PMIT */
+ ret = sdram->pmit;
+ break;
+ case 0x40: /* SDRAM_B0CR */
+ ret = sdram->bank[0].bcr;
+ break;
+ case 0x44: /* SDRAM_B1CR */
+ ret = sdram->bank[1].bcr;
+ break;
+ case 0x48: /* SDRAM_B2CR */
+ ret = sdram->bank[2].bcr;
+ break;
+ case 0x4C: /* SDRAM_B3CR */
+ ret = sdram->bank[3].bcr;
+ break;
+ case 0x80: /* SDRAM_TR */
+ ret = -1; /* ? */
+ break;
+ case 0x94: /* SDRAM_ECCCFG */
+ ret = sdram->ecccfg;
+ break;
+ case 0x98: /* SDRAM_ECCESR */
+ ret = sdram->eccesr;
+ break;
+ default: /* Error */
+ ret = -1;
+ break;
+ }
+ break;
+ default:
+ /* Avoid gcc warning */
+ ret = 0;
+ break;
+ }
+
+ return ret;
+}
+
+static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
+{
+ Ppc4xxSdramDdrState *sdram = opaque;
+
+ switch (dcrn) {
+ case SDRAM0_CFGADDR:
+ sdram->addr = val;
+ break;
+ case SDRAM0_CFGDATA:
+ switch (sdram->addr) {
+ case 0x00: /* SDRAM_BESR0 */
+ sdram->besr0 &= ~val;
+ break;
+ case 0x08: /* SDRAM_BESR1 */
+ sdram->besr1 &= ~val;
+ break;
+ case 0x10: /* SDRAM_BEAR */
+ sdram->bear = val;
+ break;
+ case 0x20: /* SDRAM_CFG */
+ val &= 0xFFE00000;
+ if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
+ trace_ppc4xx_sdram_enable("enable");
+ /* validate all RAM mappings */
+ sdram_ddr_map_bcr(sdram);
+ sdram->status &= ~0x80000000;
+ } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
+ trace_ppc4xx_sdram_enable("disable");
+ /* invalidate all RAM mappings */
+ sdram_ddr_unmap_bcr(sdram);
+ sdram->status |= 0x80000000;
+ }
+ if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) {
+ sdram->status |= 0x40000000;
+ } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) {
+ sdram->status &= ~0x40000000;
+ }
+ sdram->cfg = val;
+ break;
+ case 0x24: /* SDRAM_STATUS */
+ /* Read-only register */
+ break;
+ case 0x30: /* SDRAM_RTR */
+ sdram->rtr = val & 0x3FF80000;
+ break;
+ case 0x34: /* SDRAM_PMIT */
+ sdram->pmit = (val & 0xF8000000) | 0x07C00000;
+ break;
+ case 0x40: /* SDRAM_B0CR */
+ sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
+ break;
+ case 0x44: /* SDRAM_B1CR */
+ sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
+ break;
+ case 0x48: /* SDRAM_B2CR */
+ sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
+ break;
+ case 0x4C: /* SDRAM_B3CR */
+ sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
+ break;
+ case 0x80: /* SDRAM_TR */
+ sdram->tr = val & 0x018FC01F;
+ break;
+ case 0x94: /* SDRAM_ECCCFG */
+ sdram->ecccfg = val & 0x00F00000;
+ break;
+ case 0x98: /* SDRAM_ECCESR */
+ val &= 0xFFF0F000;
+ if (sdram->eccesr == 0 && val != 0) {
+ qemu_irq_raise(sdram->irq);
+ } else if (sdram->eccesr != 0 && val == 0) {
+ qemu_irq_lower(sdram->irq);
+ }
+ sdram->eccesr = val;
+ break;
+ default: /* Error */
+ break;
+ }
+ break;
+ }
+}
+
+static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
+{
+ Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
+
+ sdram->addr = 0;
+ sdram->bear = 0;
+ sdram->besr0 = 0; /* No error */
+ sdram->besr1 = 0; /* No error */
+ sdram->cfg = 0;
+ sdram->ecccfg = 0; /* No ECC */
+ sdram->eccesr = 0; /* No error */
+ sdram->pmit = 0x07C00000;
+ sdram->rtr = 0x05F00000;
+ sdram->tr = 0x00854009;
+ /* We pre-initialize RAM banks */
+ sdram->status = 0;
+ sdram->cfg = 0x00800000;
+}
+
+static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
+{
+ Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+ const ram_addr_t valid_bank_sizes[] = {
+ 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
+ };
+
+ if (s->nbanks < 1 || s->nbanks > 4) {
+ error_setg(errp, "Invalid number of RAM banks");
+ return;
+ }
+ if (!s->dram_mr) {
+ error_setg(errp, "Missing dram memory region");
+ return;
+ }
+ ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
+
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
+ s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
+ s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
+}
+
+static Property ppc4xx_sdram_ddr_props[] = {
+ DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_sdram_ddr_realize;
+ dc->reset = ppc4xx_sdram_ddr_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc4xx_sdram_ddr_props);
+}
+
+/*****************************************************************************/
+/* DDR2 SDRAM controller */
+enum {
+ SDRAM_R0BAS = 0x40,
+ SDRAM_R1BAS,
+ SDRAM_R2BAS,
+ SDRAM_R3BAS,
+ SDRAM_CONF1HB = 0x45,
+ SDRAM_PLBADDULL = 0x4a,
+ SDRAM_CONF1LL = 0x4b,
+ SDRAM_CONFPATHB = 0x4f,
+ SDRAM_PLBADDUHB = 0x50,
+};
+
+static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
+{
+ uint32_t bcr;
+
+ switch (ram_size) {
+ case 8 * MiB:
+ bcr = 0xffc0;
+ break;
+ case 16 * MiB:
+ bcr = 0xff80;
+ break;
+ case 32 * MiB:
+ bcr = 0xff00;
+ break;
+ case 64 * MiB:
+ bcr = 0xfe00;
+ break;
+ case 128 * MiB:
+ bcr = 0xfc00;
+ break;
+ case 256 * MiB:
+ bcr = 0xf800;
+ break;
+ case 512 * MiB:
+ bcr = 0xf000;
+ break;
+ case 1 * GiB:
+ bcr = 0xe000;
+ break;
+ case 2 * GiB:
+ bcr = 0xc000;
+ break;
+ case 4 * GiB:
+ bcr = 0x8000;
+ break;
+ default:
+ error_report("invalid RAM size " TARGET_FMT_plx, ram_size);
+ return 0;
+ }
+ bcr |= ram_base >> 2 & 0xffe00000;
+ bcr |= 1;
+
+ return bcr;
+}
+
+static inline hwaddr sdram_ddr2_base(uint32_t bcr)
+{
+ return (bcr & 0xffe00000) << 2;
+}
+
+static uint64_t sdram_ddr2_size(uint32_t bcr)
+{
+ uint64_t size;
+ int sh;
+
+ sh = 1024 - ((bcr >> 6) & 0x3ff);
+ size = 8 * MiB * sh;
+
+ return size;
+}
+
+static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i,
+ uint32_t bcr, int enabled)
+{
+ if (sdram->bank[i].bcr & 1) {
+ /* First unmap RAM if enabled */
+ trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
+ sdram_ddr2_size(sdram->bank[i].bcr));
+ sdram_bank_unmap(&sdram->bank[i]);
+ }
+ sdram->bank[i].bcr = bcr & 0xffe0ffc1;
+ sdram->bank[i].base = sdram_ddr2_base(bcr);
+ sdram->bank[i].size = sdram_ddr2_size(bcr);
+ if (enabled && (bcr & 1)) {
+ trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr));
+ sdram_bank_map(&sdram->bank[i]);
+ }
+}
+
+static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram)
+{
+ int i;
+
+ for (i = 0; i < sdram->nbanks; i++) {
+ if (sdram->bank[i].size) {
+ sdram_ddr2_set_bcr(sdram, i,
+ sdram_ddr2_bcr(sdram->bank[i].base,
+ sdram->bank[i].size), 1);
+ } else {
+ sdram_ddr2_set_bcr(sdram, i, 0, 0);
+ }
+ }
+}
+
+static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
+{
+ int i;
+
+ for (i = 0; i < sdram->nbanks; i++) {
+ if (sdram->bank[i].size) {
+ sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
+ }
+ }
+}
+
+static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
+{
+ Ppc4xxSdramDdr2State *sdram = opaque;
+ uint32_t ret = 0;
+
+ switch (dcrn) {
+ case SDRAM_R0BAS:
+ case SDRAM_R1BAS:
+ case SDRAM_R2BAS:
+ case SDRAM_R3BAS:
+ if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
+ ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
+ sdram->bank[dcrn - SDRAM_R0BAS].size);
+ }
+ break;
+ case SDRAM_CONF1HB:
+ case SDRAM_CONF1LL:
+ case SDRAM_CONFPATHB:
+ case SDRAM_PLBADDULL:
+ case SDRAM_PLBADDUHB:
+ break;
+ case SDRAM0_CFGADDR:
+ ret = sdram->addr;
+ break;
+ case SDRAM0_CFGDATA:
+ switch (sdram->addr) {
+ case 0x14: /* SDRAM_MCSTAT (405EX) */
+ case 0x1F:
+ ret = 0x80000000;
+ break;
+ case 0x21: /* SDRAM_MCOPT2 */
+ ret = sdram->mcopt2;
+ break;
+ case 0x40: /* SDRAM_MB0CF */
+ ret = 0x00008001;
+ break;
+ case 0x7A: /* SDRAM_DLCR */
+ ret = 0x02000000;
+ break;
+ case 0xE1: /* SDR0_DDR0 */
+ ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
+{
+ Ppc4xxSdramDdr2State *sdram = opaque;
+
+ switch (dcrn) {
+ case SDRAM_R0BAS:
+ case SDRAM_R1BAS:
+ case SDRAM_R2BAS:
+ case SDRAM_R3BAS:
+ case SDRAM_CONF1HB:
+ case SDRAM_CONF1LL:
+ case SDRAM_CONFPATHB:
+ case SDRAM_PLBADDULL:
+ case SDRAM_PLBADDUHB:
+ break;
+ case SDRAM0_CFGADDR:
+ sdram->addr = val;
+ break;
+ case SDRAM0_CFGDATA:
+ switch (sdram->addr) {
+ case 0x00: /* B0CR */
+ break;
+ case 0x21: /* SDRAM_MCOPT2 */
+ if (!(sdram->mcopt2 & BIT(27)) && (val & BIT(27))) {
+ trace_ppc4xx_sdram_enable("enable");
+ /* validate all RAM mappings */
+ sdram_ddr2_map_bcr(sdram);
+ sdram->mcopt2 |= BIT(27);
+ } else if ((sdram->mcopt2 & BIT(27)) && !(val & BIT(27))) {
+ trace_ppc4xx_sdram_enable("disable");
+ /* invalidate all RAM mappings */
+ sdram_ddr2_unmap_bcr(sdram);
+ sdram->mcopt2 &= ~BIT(27);
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
+{
+ Ppc4xxSdramDdr2State *sdram = PPC4xx_SDRAM_DDR2(dev);
+
+ sdram->addr = 0;
+ sdram->mcopt2 = 0;
+}
+
+static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
+{
+ Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
+ Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
+ const ram_addr_t valid_bank_sizes[] = {
+ 4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
+ 32 * MiB, 16 * MiB, 8 * MiB, 0
+ };
+
+ if (s->nbanks < 1 || s->nbanks > 4) {
+ error_setg(errp, "Invalid number of RAM banks");
+ return;
+ }
+ if (!s->dram_mr) {
+ error_setg(errp, "Missing dram memory region");
+ return;
+ }
+ ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+
+ ppc4xx_dcr_register(dcr, SDRAM_R0BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R1BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R2BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_R3BAS,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONF1HB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONF1LL,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+ ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB,
+ s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
+}
+
+static Property ppc4xx_sdram_ddr2_props[] = {
+ DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc4xx_sdram_ddr2_realize;
+ dc->reset = ppc4xx_sdram_ddr2_reset;
+ /* Reason: only works as function of a ppc4xx SoC */
+ dc->user_creatable = false;
+ device_class_set_props(dc, ppc4xx_sdram_ddr2_props);
+}
+
+static const TypeInfo ppc4xx_sdram_types[] = {
+ {
+ .name = TYPE_PPC4xx_SDRAM_DDR,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc4xxSdramDdrState),
+ .class_init = ppc4xx_sdram_ddr_class_init,
+ }, {
+ .name = TYPE_PPC4xx_SDRAM_DDR2,
+ .parent = TYPE_PPC4xx_DCR_DEVICE,
+ .instance_size = sizeof(Ppc4xxSdramDdr2State),
+ .class_init = ppc4xx_sdram_ddr2_class_init,
+ }
+};
+
+DEFINE_TYPES(ppc4xx_sdram_types)
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 7d3cfa7ad6..7216d62882 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -29,23 +29,6 @@
#include "exec/memory.h"
#include "hw/sysbus.h"
-typedef struct {
- MemoryRegion ram;
- MemoryRegion container; /* used for clipping */
- hwaddr base;
- hwaddr size;
- uint32_t bcr;
-} Ppc4xxSdramBank;
-
-enum {
- SDRAM0_CFGADDR = 0x010,
- SDRAM0_CFGDATA = 0x011,
-};
-
-void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
- Ppc4xxSdramBank ram_banks[],
- const ram_addr_t sdram_bank_sizes[]);
-
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
/*
@@ -116,6 +99,23 @@ struct Ppc4xxEbcState {
};
/* SDRAM DDR controller */
+typedef struct {
+ MemoryRegion ram;
+ MemoryRegion container; /* used for clipping */
+ hwaddr base;
+ hwaddr size;
+ uint32_t bcr;
+} Ppc4xxSdramBank;
+
+enum {
+ SDRAM0_CFGADDR = 0x010,
+ SDRAM0_CFGDATA = 0x011,
+};
+
+#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29)
+#define SDR0_DDR0_DDRM_DDR1 0x20000000
+#define SDR0_DDR0_DDRM_DDR2 0x40000000
+
#define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR);
struct Ppc4xxSdramDdrState {
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v3 17/20] ppc4xx_sdram: Use hwaddr for memory bank size
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (15 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 16/20] ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models together BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 18/20] ppc4xx_sdram: Rename local state variable for brevity BALATON Zoltan
` (3 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
This resolves the target_ulong dependency that's clearly wrong and was
also noted in a fixme comment.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/ppc/ppc4xx_sdram.c | 14 ++++----------
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
index bc28d69a26..242e2f4c6e 100644
--- a/hw/ppc/ppc4xx_sdram.c
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -34,7 +34,6 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "exec/address-spaces.h" /* get_system_memory() */
-#include "exec/cpu-defs.h" /* target_ulong */
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "qapi/error.h"
@@ -122,11 +121,6 @@ static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
/*****************************************************************************/
/* DDR SDRAM controller */
-/*
- * XXX: TOFIX: some patches have made this code become inconsistent:
- * there are type inconsistencies, mixing hwaddr, target_ulong
- * and uint32_t
- */
static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -170,9 +164,9 @@ static inline hwaddr sdram_ddr_base(uint32_t bcr)
return bcr & 0xFF800000;
}
-static target_ulong sdram_ddr_size(uint32_t bcr)
+static hwaddr sdram_ddr_size(uint32_t bcr)
{
- target_ulong size;
+ hwaddr size;
int sh;
sh = (bcr >> 17) & 0x7;
@@ -513,9 +507,9 @@ static inline hwaddr sdram_ddr2_base(uint32_t bcr)
return (bcr & 0xffe00000) << 2;
}
-static uint64_t sdram_ddr2_size(uint32_t bcr)
+static hwaddr sdram_ddr2_size(uint32_t bcr)
{
- uint64_t size;
+ hwaddr size;
int sh;
sh = 1024 - ((bcr >> 6) & 0x3ff);
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v3 18/20] ppc4xx_sdram: Rename local state variable for brevity
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (16 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 17/20] ppc4xx_sdram: Use hwaddr for memory bank size BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 19/20] ppc4xx_sdram: Generalise bank setup BALATON Zoltan
` (2 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Rename the sdram local state variable to s in dcr read/write functions
and reset methods for better readability and to match realize methods.
Other places not converted will be changed or removed in subsequent
patches.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc4xx_sdram.c | 158 +++++++++++++++++++++---------------------
1 file changed, 79 insertions(+), 79 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
index 242e2f4c6e..e36898a906 100644
--- a/hw/ppc/ppc4xx_sdram.c
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -233,56 +233,56 @@ static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
{
- Ppc4xxSdramDdrState *sdram = opaque;
+ Ppc4xxSdramDdrState *s = opaque;
uint32_t ret;
switch (dcrn) {
case SDRAM0_CFGADDR:
- ret = sdram->addr;
+ ret = s->addr;
break;
case SDRAM0_CFGDATA:
- switch (sdram->addr) {
+ switch (s->addr) {
case 0x00: /* SDRAM_BESR0 */
- ret = sdram->besr0;
+ ret = s->besr0;
break;
case 0x08: /* SDRAM_BESR1 */
- ret = sdram->besr1;
+ ret = s->besr1;
break;
case 0x10: /* SDRAM_BEAR */
- ret = sdram->bear;
+ ret = s->bear;
break;
case 0x20: /* SDRAM_CFG */
- ret = sdram->cfg;
+ ret = s->cfg;
break;
case 0x24: /* SDRAM_STATUS */
- ret = sdram->status;
+ ret = s->status;
break;
case 0x30: /* SDRAM_RTR */
- ret = sdram->rtr;
+ ret = s->rtr;
break;
case 0x34: /* SDRAM_PMIT */
- ret = sdram->pmit;
+ ret = s->pmit;
break;
case 0x40: /* SDRAM_B0CR */
- ret = sdram->bank[0].bcr;
+ ret = s->bank[0].bcr;
break;
case 0x44: /* SDRAM_B1CR */
- ret = sdram->bank[1].bcr;
+ ret = s->bank[1].bcr;
break;
case 0x48: /* SDRAM_B2CR */
- ret = sdram->bank[2].bcr;
+ ret = s->bank[2].bcr;
break;
case 0x4C: /* SDRAM_B3CR */
- ret = sdram->bank[3].bcr;
+ ret = s->bank[3].bcr;
break;
case 0x80: /* SDRAM_TR */
ret = -1; /* ? */
break;
case 0x94: /* SDRAM_ECCCFG */
- ret = sdram->ecccfg;
+ ret = s->ecccfg;
break;
case 0x98: /* SDRAM_ECCESR */
- ret = sdram->eccesr;
+ ret = s->eccesr;
break;
default: /* Error */
ret = -1;
@@ -300,78 +300,78 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
{
- Ppc4xxSdramDdrState *sdram = opaque;
+ Ppc4xxSdramDdrState *s = opaque;
switch (dcrn) {
case SDRAM0_CFGADDR:
- sdram->addr = val;
+ s->addr = val;
break;
case SDRAM0_CFGDATA:
- switch (sdram->addr) {
+ switch (s->addr) {
case 0x00: /* SDRAM_BESR0 */
- sdram->besr0 &= ~val;
+ s->besr0 &= ~val;
break;
case 0x08: /* SDRAM_BESR1 */
- sdram->besr1 &= ~val;
+ s->besr1 &= ~val;
break;
case 0x10: /* SDRAM_BEAR */
- sdram->bear = val;
+ s->bear = val;
break;
case 0x20: /* SDRAM_CFG */
val &= 0xFFE00000;
- if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
+ if (!(s->cfg & 0x80000000) && (val & 0x80000000)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_ddr_map_bcr(sdram);
- sdram->status &= ~0x80000000;
- } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
+ sdram_ddr_map_bcr(s);
+ s->status &= ~0x80000000;
+ } else if ((s->cfg & 0x80000000) && !(val & 0x80000000)) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_ddr_unmap_bcr(sdram);
- sdram->status |= 0x80000000;
+ sdram_ddr_unmap_bcr(s);
+ s->status |= 0x80000000;
}
- if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) {
- sdram->status |= 0x40000000;
- } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) {
- sdram->status &= ~0x40000000;
+ if (!(s->cfg & 0x40000000) && (val & 0x40000000)) {
+ s->status |= 0x40000000;
+ } else if ((s->cfg & 0x40000000) && !(val & 0x40000000)) {
+ s->status &= ~0x40000000;
}
- sdram->cfg = val;
+ s->cfg = val;
break;
case 0x24: /* SDRAM_STATUS */
/* Read-only register */
break;
case 0x30: /* SDRAM_RTR */
- sdram->rtr = val & 0x3FF80000;
+ s->rtr = val & 0x3FF80000;
break;
case 0x34: /* SDRAM_PMIT */
- sdram->pmit = (val & 0xF8000000) | 0x07C00000;
+ s->pmit = (val & 0xF8000000) | 0x07C00000;
break;
case 0x40: /* SDRAM_B0CR */
- sdram_ddr_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(s, 0, val, s->cfg & 0x80000000);
break;
case 0x44: /* SDRAM_B1CR */
- sdram_ddr_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(s, 1, val, s->cfg & 0x80000000);
break;
case 0x48: /* SDRAM_B2CR */
- sdram_ddr_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(s, 2, val, s->cfg & 0x80000000);
break;
case 0x4C: /* SDRAM_B3CR */
- sdram_ddr_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
+ sdram_ddr_set_bcr(s, 3, val, s->cfg & 0x80000000);
break;
case 0x80: /* SDRAM_TR */
- sdram->tr = val & 0x018FC01F;
+ s->tr = val & 0x018FC01F;
break;
case 0x94: /* SDRAM_ECCCFG */
- sdram->ecccfg = val & 0x00F00000;
+ s->ecccfg = val & 0x00F00000;
break;
case 0x98: /* SDRAM_ECCESR */
val &= 0xFFF0F000;
- if (sdram->eccesr == 0 && val != 0) {
- qemu_irq_raise(sdram->irq);
- } else if (sdram->eccesr != 0 && val == 0) {
- qemu_irq_lower(sdram->irq);
+ if (s->eccesr == 0 && val != 0) {
+ qemu_irq_raise(s->irq);
+ } else if (s->eccesr != 0 && val == 0) {
+ qemu_irq_lower(s->irq);
}
- sdram->eccesr = val;
+ s->eccesr = val;
break;
default: /* Error */
break;
@@ -382,21 +382,21 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
{
- Ppc4xxSdramDdrState *sdram = PPC4xx_SDRAM_DDR(dev);
-
- sdram->addr = 0;
- sdram->bear = 0;
- sdram->besr0 = 0; /* No error */
- sdram->besr1 = 0; /* No error */
- sdram->cfg = 0;
- sdram->ecccfg = 0; /* No ECC */
- sdram->eccesr = 0; /* No error */
- sdram->pmit = 0x07C00000;
- sdram->rtr = 0x05F00000;
- sdram->tr = 0x00854009;
+ Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
+
+ s->addr = 0;
+ s->bear = 0;
+ s->besr0 = 0; /* No error */
+ s->besr1 = 0; /* No error */
+ s->cfg = 0;
+ s->ecccfg = 0; /* No ECC */
+ s->eccesr = 0; /* No error */
+ s->pmit = 0x07C00000;
+ s->rtr = 0x05F00000;
+ s->tr = 0x00854009;
/* We pre-initialize RAM banks */
- sdram->status = 0;
- sdram->cfg = 0x00800000;
+ s->status = 0;
+ s->cfg = 0x00800000;
}
static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
@@ -564,7 +564,7 @@ static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
- Ppc4xxSdramDdr2State *sdram = opaque;
+ Ppc4xxSdramDdr2State *s = opaque;
uint32_t ret = 0;
switch (dcrn) {
@@ -572,9 +572,9 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
case SDRAM_R1BAS:
case SDRAM_R2BAS:
case SDRAM_R3BAS:
- if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
- ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
- sdram->bank[dcrn - SDRAM_R0BAS].size);
+ if (s->bank[dcrn - SDRAM_R0BAS].size) {
+ ret = sdram_ddr2_bcr(s->bank[dcrn - SDRAM_R0BAS].base,
+ s->bank[dcrn - SDRAM_R0BAS].size);
}
break;
case SDRAM_CONF1HB:
@@ -584,16 +584,16 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
case SDRAM_PLBADDUHB:
break;
case SDRAM0_CFGADDR:
- ret = sdram->addr;
+ ret = s->addr;
break;
case SDRAM0_CFGDATA:
- switch (sdram->addr) {
+ switch (s->addr) {
case 0x14: /* SDRAM_MCSTAT (405EX) */
case 0x1F:
ret = 0x80000000;
break;
case 0x21: /* SDRAM_MCOPT2 */
- ret = sdram->mcopt2;
+ ret = s->mcopt2;
break;
case 0x40: /* SDRAM_MB0CF */
ret = 0x00008001;
@@ -617,7 +617,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
- Ppc4xxSdramDdr2State *sdram = opaque;
+ Ppc4xxSdramDdr2State *s = opaque;
switch (dcrn) {
case SDRAM_R0BAS:
@@ -631,23 +631,23 @@ static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
case SDRAM_PLBADDUHB:
break;
case SDRAM0_CFGADDR:
- sdram->addr = val;
+ s->addr = val;
break;
case SDRAM0_CFGDATA:
- switch (sdram->addr) {
+ switch (s->addr) {
case 0x00: /* B0CR */
break;
case 0x21: /* SDRAM_MCOPT2 */
- if (!(sdram->mcopt2 & BIT(27)) && (val & BIT(27))) {
+ if (!(s->mcopt2 & BIT(27)) && (val & BIT(27))) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_ddr2_map_bcr(sdram);
- sdram->mcopt2 |= BIT(27);
- } else if ((sdram->mcopt2 & BIT(27)) && !(val & BIT(27))) {
+ sdram_ddr2_map_bcr(s);
+ s->mcopt2 |= BIT(27);
+ } else if ((s->mcopt2 & BIT(27)) && !(val & BIT(27))) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_ddr2_unmap_bcr(sdram);
- sdram->mcopt2 &= ~BIT(27);
+ sdram_ddr2_unmap_bcr(s);
+ s->mcopt2 &= ~BIT(27);
}
break;
default:
@@ -661,10 +661,10 @@ static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
{
- Ppc4xxSdramDdr2State *sdram = PPC4xx_SDRAM_DDR2(dev);
+ Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
- sdram->addr = 0;
- sdram->mcopt2 = 0;
+ s->addr = 0;
+ s->mcopt2 = 0;
}
static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v3 19/20] ppc4xx_sdram: Generalise bank setup
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (17 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 18/20] ppc4xx_sdram: Rename local state variable for brevity BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-13 19:52 ` [PATCH v3 20/20] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling BALATON Zoltan
2022-09-14 7:29 ` [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups Cédric Le Goater
20 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Currently only base and size are set on initial bank creation and bcr
value is computed on mapping the region. Set bcr at init so the bcr
encoding method becomes local to the controller model and mapping and
unmapping can operate on the bank so it can be shared between
different controller models. This patch converts the DDR2 controller.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc4xx_sdram.c | 93 ++++++++++++++++++++++---------------------
hw/ppc/trace-events | 1 +
2 files changed, 48 insertions(+), 46 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
index e36898a906..79a9efce4b 100644
--- a/hw/ppc/ppc4xx_sdram.c
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -106,6 +106,7 @@ static void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
static void sdram_bank_map(Ppc4xxSdramBank *bank)
{
+ trace_ppc4xx_sdram_map(bank->base, bank->size);
memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
memory_region_add_subregion(&bank->container, 0, &bank->ram);
memory_region_add_subregion(get_system_memory(), bank->base,
@@ -114,11 +115,26 @@ static void sdram_bank_map(Ppc4xxSdramBank *bank)
static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
{
+ trace_ppc4xx_sdram_unmap(bank->base, bank->size);
memory_region_del_subregion(get_system_memory(), &bank->container);
memory_region_del_subregion(&bank->container, &bank->ram);
object_unparent(OBJECT(&bank->container));
}
+static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, uint32_t bcr,
+ hwaddr base, hwaddr size, int enabled)
+{
+ if (memory_region_is_mapped(&bank->container)) {
+ sdram_bank_unmap(bank);
+ }
+ bank->bcr = bcr;
+ bank->base = base;
+ bank->size = size;
+ if (enabled && (bcr & 1)) {
+ sdram_bank_map(bank);
+ }
+}
+
/*****************************************************************************/
/* DDR SDRAM controller */
static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
@@ -445,6 +461,8 @@ static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
/*****************************************************************************/
/* DDR2 SDRAM controller */
+#define SDRAM_DDR2_BCR_MASK 0xffe0ffc1
+
enum {
SDRAM_R0BAS = 0x40,
SDRAM_R1BAS,
@@ -518,50 +536,6 @@ static hwaddr sdram_ddr2_size(uint32_t bcr)
return size;
}
-static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i,
- uint32_t bcr, int enabled)
-{
- if (sdram->bank[i].bcr & 1) {
- /* First unmap RAM if enabled */
- trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
- sdram_ddr2_size(sdram->bank[i].bcr));
- sdram_bank_unmap(&sdram->bank[i]);
- }
- sdram->bank[i].bcr = bcr & 0xffe0ffc1;
- sdram->bank[i].base = sdram_ddr2_base(bcr);
- sdram->bank[i].size = sdram_ddr2_size(bcr);
- if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr));
- sdram_bank_map(&sdram->bank[i]);
- }
-}
-
-static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size) {
- sdram_ddr2_set_bcr(sdram, i,
- sdram_ddr2_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
- } else {
- sdram_ddr2_set_bcr(sdram, i, 0, 0);
- }
- }
-}
-
-static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size) {
- sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
- }
- }
-}
-
static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
{
Ppc4xxSdramDdr2State *s = opaque;
@@ -618,6 +592,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
{
Ppc4xxSdramDdr2State *s = opaque;
+ int i;
switch (dcrn) {
case SDRAM_R0BAS:
@@ -641,12 +616,24 @@ static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
if (!(s->mcopt2 & BIT(27)) && (val & BIT(27))) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_ddr2_map_bcr(s);
+ for (i = 0; i < s->nbanks; i++) {
+ if (s->bank[i].size) {
+ sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
+ s->bank[i].base, s->bank[i].size,
+ 1);
+ }
+ }
s->mcopt2 |= BIT(27);
} else if ((s->mcopt2 & BIT(27)) && !(val & BIT(27))) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_ddr2_unmap_bcr(s);
+ for (i = 0; i < s->nbanks; i++) {
+ if (s->bank[i].size) {
+ sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
+ s->bank[i].base, s->bank[i].size,
+ 0);
+ }
+ }
s->mcopt2 &= ~BIT(27);
}
break;
@@ -675,6 +662,7 @@ static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
32 * MiB, 16 * MiB, 8 * MiB, 0
};
+ int i;
if (s->nbanks < 1 || s->nbanks > 4) {
error_setg(errp, "Invalid number of RAM banks");
@@ -685,6 +673,19 @@ static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
return;
}
ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+ for (i = 0; i < s->nbanks; i++) {
+ if (s->bank[i].size) {
+ s->bank[i].bcr = sdram_ddr2_bcr(s->bank[i].base, s->bank[i].size);
+ s->bank[i].bcr &= SDRAM_DDR2_BCR_MASK;
+ sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
+ s->bank[i].base, s->bank[i].size, 0);
+ } else {
+ sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0);
+ }
+ trace_ppc4xx_sdram_init(sdram_ddr2_base(s->bank[i].bcr),
+ sdram_ddr2_size(s->bank[i].bcr),
+ s->bank[i].bcr);
+ }
ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index a07d5aca0f..3b3e4211d4 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -179,3 +179,4 @@ ppc405ep_clocks_setup(const char *trace) "%s"
ppc4xx_sdram_enable(const char *trace) "%s SDRAM controller"
ppc4xx_sdram_unmap(uint64_t addr, uint64_t size) "Unmap RAM area 0x%" PRIx64 " size 0x%" PRIx64
ppc4xx_sdram_map(uint64_t addr, uint64_t size) "Map RAM area 0x%" PRIx64 " size 0x%" PRIx64
+ppc4xx_sdram_init(uint64_t base, uint64_t size, uint32_t bcr) "Init RAM area 0x%" PRIx64 " size 0x%" PRIx64 " bcr 0x%x"
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PATCH v3 20/20] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (18 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 19/20] ppc4xx_sdram: Generalise bank setup BALATON Zoltan
@ 2022-09-13 19:52 ` BALATON Zoltan
2022-09-14 7:29 ` [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups Cédric Le Goater
20 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-13 19:52 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: clg, Daniel Henrique Barboza, Peter Maydell
Use the generic bank handling introduced in previous patch in the DDR
SDRAM controller too. This also fixes previously broken region unmap
due to sdram_ddr_unmap_bcr() ignoring container region so it crashed
with an assert when the guest tried to disable the controller.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ppc/ppc4xx_sdram.c | 98 ++++++++++++++++---------------------------
1 file changed, 37 insertions(+), 61 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c
index 79a9efce4b..c731012940 100644
--- a/hw/ppc/ppc4xx_sdram.c
+++ b/hw/ppc/ppc4xx_sdram.c
@@ -137,6 +137,8 @@ static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, uint32_t bcr,
/*****************************************************************************/
/* DDR SDRAM controller */
+#define SDRAM_DDR_BCR_MASK 0xFFDEE001
+
static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
{
uint32_t bcr;
@@ -195,58 +197,6 @@ static hwaddr sdram_ddr_size(uint32_t bcr)
return size;
}
-static void sdram_ddr_set_bcr(Ppc4xxSdramDdrState *sdram, int i,
- uint32_t bcr, int enabled)
-{
- if (sdram->bank[i].bcr & 1) {
- /* Unmap RAM */
- trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
- sdram_ddr_size(sdram->bank[i].bcr));
- memory_region_del_subregion(get_system_memory(),
- &sdram->bank[i].container);
- memory_region_del_subregion(&sdram->bank[i].container,
- &sdram->bank[i].ram);
- object_unparent(OBJECT(&sdram->bank[i].container));
- }
- sdram->bank[i].bcr = bcr & 0xFFDEE001;
- if (enabled && (bcr & 1)) {
- trace_ppc4xx_sdram_map(sdram_ddr_base(bcr), sdram_ddr_size(bcr));
- memory_region_init(&sdram->bank[i].container, NULL, "sdram-container",
- sdram_ddr_size(bcr));
- memory_region_add_subregion(&sdram->bank[i].container, 0,
- &sdram->bank[i].ram);
- memory_region_add_subregion(get_system_memory(),
- sdram_ddr_base(bcr),
- &sdram->bank[i].container);
- }
-}
-
-static void sdram_ddr_map_bcr(Ppc4xxSdramDdrState *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- if (sdram->bank[i].size != 0) {
- sdram_ddr_set_bcr(sdram, i, sdram_ddr_bcr(sdram->bank[i].base,
- sdram->bank[i].size), 1);
- } else {
- sdram_ddr_set_bcr(sdram, i, 0, 0);
- }
- }
-}
-
-static void sdram_ddr_unmap_bcr(Ppc4xxSdramDdrState *sdram)
-{
- int i;
-
- for (i = 0; i < sdram->nbanks; i++) {
- trace_ppc4xx_sdram_unmap(sdram_ddr_base(sdram->bank[i].bcr),
- sdram_ddr_size(sdram->bank[i].bcr));
- memory_region_del_subregion(get_system_memory(),
- &sdram->bank[i].ram);
- }
-}
-
static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
{
Ppc4xxSdramDdrState *s = opaque;
@@ -317,6 +267,7 @@ static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
{
Ppc4xxSdramDdrState *s = opaque;
+ int i;
switch (dcrn) {
case SDRAM0_CFGADDR:
@@ -338,12 +289,24 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
if (!(s->cfg & 0x80000000) && (val & 0x80000000)) {
trace_ppc4xx_sdram_enable("enable");
/* validate all RAM mappings */
- sdram_ddr_map_bcr(s);
+ for (i = 0; i < s->nbanks; i++) {
+ if (s->bank[i].size) {
+ sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
+ s->bank[i].base, s->bank[i].size,
+ 1);
+ }
+ }
s->status &= ~0x80000000;
} else if ((s->cfg & 0x80000000) && !(val & 0x80000000)) {
trace_ppc4xx_sdram_enable("disable");
/* invalidate all RAM mappings */
- sdram_ddr_unmap_bcr(s);
+ for (i = 0; i < s->nbanks; i++) {
+ if (s->bank[i].size) {
+ sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
+ s->bank[i].base, s->bank[i].size,
+ 0);
+ }
+ }
s->status |= 0x80000000;
}
if (!(s->cfg & 0x40000000) && (val & 0x40000000)) {
@@ -363,16 +326,16 @@ static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
s->pmit = (val & 0xF8000000) | 0x07C00000;
break;
case 0x40: /* SDRAM_B0CR */
- sdram_ddr_set_bcr(s, 0, val, s->cfg & 0x80000000);
- break;
case 0x44: /* SDRAM_B1CR */
- sdram_ddr_set_bcr(s, 1, val, s->cfg & 0x80000000);
- break;
case 0x48: /* SDRAM_B2CR */
- sdram_ddr_set_bcr(s, 2, val, s->cfg & 0x80000000);
- break;
case 0x4C: /* SDRAM_B3CR */
- sdram_ddr_set_bcr(s, 3, val, s->cfg & 0x80000000);
+ i = (s->addr - 0x40) / 4;
+ val &= SDRAM_DDR_BCR_MASK;
+ if (s->bank[i].size) {
+ sdram_bank_set_bcr(&s->bank[i], val,
+ sdram_ddr_base(val), sdram_ddr_size(val),
+ s->cfg & 0x80000000);
+ }
break;
case 0x80: /* SDRAM_TR */
s->tr = val & 0x018FC01F;
@@ -422,6 +385,7 @@ static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
const ram_addr_t valid_bank_sizes[] = {
256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
};
+ int i;
if (s->nbanks < 1 || s->nbanks > 4) {
error_setg(errp, "Invalid number of RAM banks");
@@ -432,6 +396,18 @@ static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
return;
}
ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
+ for (i = 0; i < s->nbanks; i++) {
+ if (s->bank[i].size) {
+ s->bank[i].bcr = sdram_ddr_bcr(s->bank[i].base, s->bank[i].size);
+ sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
+ s->bank[i].base, s->bank[i].size, 0);
+ } else {
+ sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0);
+ }
+ trace_ppc4xx_sdram_init(sdram_ddr_base(s->bank[i].bcr),
+ sdram_ddr_size(s->bank[i].bcr),
+ s->bank[i].bcr);
+ }
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
--
2.30.4
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups
2022-09-13 19:52 [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups BALATON Zoltan
` (19 preceding siblings ...)
2022-09-13 19:52 ` [PATCH v3 20/20] ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling BALATON Zoltan
@ 2022-09-14 7:29 ` Cédric Le Goater
2022-09-14 11:52 ` BALATON Zoltan
20 siblings, 1 reply; 41+ messages in thread
From: Cédric Le Goater @ 2022-09-14 7:29 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Daniel Henrique Barboza, Peter Maydell
On 9/13/22 21:52, BALATON Zoltan wrote:
> This is the end of the QOMify series started by Cédric. This series
> handles the SDRAM controller models to clean them up, QOMify and unify
> them and at least partially clean up the mess that has accumulated
> around these in the past. This includes the not yet merged patches
> from the last series and new ones that change the DDR2 version used by
> sam460ex.
I made comments on the first ~10 patches. Let's try to agree on these
first. We will see the remaining ones in a second patchset.
Thanks,
C.
> v3: Fix patches that got squashed during rebase
> v2: address some review comments and try to avoid compile problem with
> gcc 12.2 (untested)
>
> BALATON Zoltan (20):
> ppc440_bamboo: Remove unnecessary memsets
> ppc4xx: Introduce Ppc4xxSdramBank struct
> ppc4xx_sdram: Get rid of the init RAM hack
> ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()
> ppc440_bamboo: Add missing 4 MiB valid memory size
> ppc4xx_sdram: Move size check to ppc4xx_sdram_init()
> ppc4xx_sdram: QOM'ify
> ppc4xx_sdram: Drop extra zeros for readability
> ppc440_sdram: Split off map/unmap of sdram banks for later reuse
> ppc440_sdram: Implement enable bit in the DDR2 SDRAM
> ppc440_sdram: Get rid of the init RAM hack
> ppc440_sdram: Rename local variable for readibility
> ppc4xx_sdram: Rename functions to prevent name clashes
> ppc440_sdram: Move RAM size check to ppc440_sdram_init
> ppc440_sdram: QOM'ify
> ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models
> together
> ppc4xx_sdram: Use hwaddr for memory bank size
> ppc4xx_sdram: Rename local state variable for brevity
> ppc4xx_sdram: Generalise bank setup
> ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling
>
> hw/ppc/meson.build | 3 +-
> hw/ppc/ppc405.h | 8 +-
> hw/ppc/ppc405_boards.c | 22 +-
> hw/ppc/ppc405_uc.c | 33 +-
> hw/ppc/ppc440.h | 4 -
> hw/ppc/ppc440_bamboo.c | 29 +-
> hw/ppc/ppc440_uc.c | 267 +--------------
> hw/ppc/ppc4xx_devs.c | 413 -----------------------
> hw/ppc/ppc4xx_sdram.c | 723 ++++++++++++++++++++++++++++++++++++++++
> hw/ppc/sam460ex.c | 48 +--
> hw/ppc/trace-events | 1 +
> include/hw/ppc/ppc4xx.h | 66 +++-
> 12 files changed, 847 insertions(+), 770 deletions(-)
> create mode 100644 hw/ppc/ppc4xx_sdram.c
>
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups
2022-09-14 7:29 ` [PATCH v3 00/20] ppc4xx_sdram QOMify and clean ups Cédric Le Goater
@ 2022-09-14 11:52 ` BALATON Zoltan
0 siblings, 0 replies; 41+ messages in thread
From: BALATON Zoltan @ 2022-09-14 11:52 UTC (permalink / raw)
To: Cédric Le Goater
Cc: qemu-devel, qemu-ppc, Daniel Henrique Barboza, Peter Maydell
[-- Attachment #1: Type: text/plain, Size: 2730 bytes --]
On Wed, 14 Sep 2022, Cédric Le Goater wrote:
> On 9/13/22 21:52, BALATON Zoltan wrote:
>> This is the end of the QOMify series started by Cédric. This series
>> handles the SDRAM controller models to clean them up, QOMify and unify
>> them and at least partially clean up the mess that has accumulated
>> around these in the past. This includes the not yet merged patches
>> from the last series and new ones that change the DDR2 version used by
>> sam460ex.
>
>
> I made comments on the first ~10 patches. Let's try to agree on these
> first. We will see the remaining ones in a second patchset.
Patch 10 does not make much sense without 11 and the final unificatoin of
the two controllers is the real goal here so please try to review further
patches too.
Regards,
BALATON Zoltan
> Thanks,
>
> C.
>
>
>
>> v3: Fix patches that got squashed during rebase
>> v2: address some review comments and try to avoid compile problem with
>> gcc 12.2 (untested)
>>
>> BALATON Zoltan (20):
>> ppc440_bamboo: Remove unnecessary memsets
>> ppc4xx: Introduce Ppc4xxSdramBank struct
>> ppc4xx_sdram: Get rid of the init RAM hack
>> ppc4xx: Use Ppc4xxSdramBank in ppc4xx_sdram_banks()
>> ppc440_bamboo: Add missing 4 MiB valid memory size
>> ppc4xx_sdram: Move size check to ppc4xx_sdram_init()
>> ppc4xx_sdram: QOM'ify
>> ppc4xx_sdram: Drop extra zeros for readability
>> ppc440_sdram: Split off map/unmap of sdram banks for later reuse
>> ppc440_sdram: Implement enable bit in the DDR2 SDRAM
>> ppc440_sdram: Get rid of the init RAM hack
>> ppc440_sdram: Rename local variable for readibility
>> ppc4xx_sdram: Rename functions to prevent name clashes
>> ppc440_sdram: Move RAM size check to ppc440_sdram_init
>> ppc440_sdram: QOM'ify
>> ppc4xx_sdram: Move ppc4xx DDR and DDR2 SDRAM controller models
>> together
>> ppc4xx_sdram: Use hwaddr for memory bank size
>> ppc4xx_sdram: Rename local state variable for brevity
>> ppc4xx_sdram: Generalise bank setup
>> ppc4xx_sdram: Convert DDR SDRAM controller to new bank handling
>>
>> hw/ppc/meson.build | 3 +-
>> hw/ppc/ppc405.h | 8 +-
>> hw/ppc/ppc405_boards.c | 22 +-
>> hw/ppc/ppc405_uc.c | 33 +-
>> hw/ppc/ppc440.h | 4 -
>> hw/ppc/ppc440_bamboo.c | 29 +-
>> hw/ppc/ppc440_uc.c | 267 +--------------
>> hw/ppc/ppc4xx_devs.c | 413 -----------------------
>> hw/ppc/ppc4xx_sdram.c | 723 ++++++++++++++++++++++++++++++++++++++++
>> hw/ppc/sam460ex.c | 48 +--
>> hw/ppc/trace-events | 1 +
>> include/hw/ppc/ppc4xx.h | 66 +++-
>> 12 files changed, 847 insertions(+), 770 deletions(-)
>> create mode 100644 hw/ppc/ppc4xx_sdram.c
>>
>
>
>
^ permalink raw reply [flat|nested] 41+ messages in thread