* [PATCH 1/4] i386/cpu: Add RAS feature bits on EPYC CPU models
2024-06-12 19:12 [PATCH 0/4] i386/cpu: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model Babu Moger
@ 2024-06-12 19:12 ` Babu Moger
2024-06-13 6:49 ` Zhao Liu
2024-06-12 19:12 ` [PATCH 2/4] i386/cpu: Add PerfMonV2 feature bit Babu Moger
` (2 subsequent siblings)
3 siblings, 1 reply; 12+ messages in thread
From: Babu Moger @ 2024-06-12 19:12 UTC (permalink / raw)
To: pbonzini; +Cc: qemu-devel, babu.moger, kvm
Add the support for following RAS features bits on AMD guests.
SUCCOR: Software uncorrectable error containment and recovery capability.
The processor supports software containment of uncorrectable errors
through context synchronizing data poisoning and deferred error
interrupts.
McaOverflowRecov: MCA overflow recovery support.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
target/i386/cpu.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 165b982c8c..86a90b1405 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4939,6 +4939,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
},
.cache_info = &epyc_v4_cache_info
},
+ {
+ .version = 5,
+ .props = (PropValue[]) {
+ { "overflow-recov", "on" },
+ { "succor", "on" },
+ { "model-id",
+ "AMD EPYC-v5 Processor" },
+ { /* end of list */ }
+ },
+ },
{ /* end of list */ }
}
},
@@ -5077,6 +5087,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
},
},
+ {
+ .version = 5,
+ .props = (PropValue[]) {
+ { "overflow-recov", "on" },
+ { "succor", "on" },
+ { "model-id",
+ "AMD EPYC-Rome-v5 Processor" },
+ { /* end of list */ }
+ },
+ },
{ /* end of list */ }
}
},
@@ -5152,6 +5172,16 @@ static const X86CPUDefinition builtin_x86_defs[] = {
},
.cache_info = &epyc_milan_v2_cache_info
},
+ {
+ .version = 3,
+ .props = (PropValue[]) {
+ { "overflow-recov", "on" },
+ { "succor", "on" },
+ { "model-id",
+ "AMD EPYC-Milan-v3 Processor" },
+ { /* end of list */ }
+ },
+ },
{ /* end of list */ }
}
},
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 1/4] i386/cpu: Add RAS feature bits on EPYC CPU models
2024-06-12 19:12 ` [PATCH 1/4] i386/cpu: Add RAS feature bits on EPYC CPU models Babu Moger
@ 2024-06-13 6:49 ` Zhao Liu
0 siblings, 0 replies; 12+ messages in thread
From: Zhao Liu @ 2024-06-13 6:49 UTC (permalink / raw)
To: Babu Moger; +Cc: pbonzini, qemu-devel, kvm
On Wed, Jun 12, 2024 at 02:12:17PM -0500, Babu Moger wrote:
> Date: Wed, 12 Jun 2024 14:12:17 -0500
> From: Babu Moger <babu.moger@amd.com>
> Subject: [PATCH 1/4] i386/cpu: Add RAS feature bits on EPYC CPU models
> X-Mailer: git-send-email 2.34.1
>
> Add the support for following RAS features bits on AMD guests.
>
> SUCCOR: Software uncorrectable error containment and recovery capability.
> The processor supports software containment of uncorrectable errors
> through context synchronizing data poisoning and deferred error
> interrupts.
>
> McaOverflowRecov: MCA overflow recovery support.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> target/i386/cpu.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/4] i386/cpu: Add PerfMonV2 feature bit
2024-06-12 19:12 [PATCH 0/4] i386/cpu: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model Babu Moger
2024-06-12 19:12 ` [PATCH 1/4] i386/cpu: Add RAS feature bits on EPYC CPU models Babu Moger
@ 2024-06-12 19:12 ` Babu Moger
2024-06-13 7:06 ` Zhao Liu
2024-06-12 19:12 ` [PATCH 3/4] i386/cpu: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa Babu Moger
2024-06-12 19:12 ` [PATCH 4/4] i386/cpu: Add support for EPYC-Turin model Babu Moger
3 siblings, 1 reply; 12+ messages in thread
From: Babu Moger @ 2024-06-12 19:12 UTC (permalink / raw)
To: pbonzini; +Cc: qemu-devel, babu.moger, kvm
From: Sandipan Das <sandipan.das@amd.com>
CPUID leaf 0x80000022, i.e. ExtPerfMonAndDbg, advertises new performance
monitoring features for AMD processors. Bit 0 of EAX indicates support
for Performance Monitoring Version 2 (PerfMonV2) features. If found to
be set during PMU initialization, the EBX bits can be used to determine
the number of available counters for different PMUs. It also denotes the
availability of global control and status registers.
Add the required CPUID feature word and feature bit to allow guests to
make use of the PerfMonV2 features.
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
target/i386/cpu.c | 26 ++++++++++++++++++++++++++
target/i386/cpu.h | 4 ++++
2 files changed, 30 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 86a90b1405..7f1837cdc9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1228,6 +1228,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.tcg_features = 0,
.unmigratable_flags = 0,
},
+ [FEAT_8000_0022_EAX] = {
+ .type = CPUID_FEATURE_WORD,
+ .feat_names = {
+ "perfmon-v2", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .cpuid = { .eax = 0x80000022, .reg = R_EAX, },
+ .tcg_features = 0,
+ .unmigratable_flags = 0,
+ },
[FEAT_XSAVE] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
@@ -6998,6 +7014,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*edx = 0;
}
break;
+ case 0x80000022:
+ *eax = *ebx = *ecx = *edx = 0;
+ /* AMD Extended Performance Monitoring and Debug */
+ if (kvm_enabled() && cpu->enable_pmu &&
+ (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) {
+ *eax = CPUID_8000_0022_EAX_PERFMON_V2;
+ *ebx = kvm_arch_get_supported_cpuid(cs->kvm_state, index, count,
+ R_EBX) & 0xf;
+ }
+ break;
case 0xC0000000:
*eax = env->cpuid_xlevel2;
*ebx = 0;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index ba7f740392..03378da8fa 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -611,6 +611,7 @@ typedef enum FeatureWord {
FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */
+ FEAT_8000_0022_EAX, /* CPUID[8000_0022].EAX */
FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */
@@ -986,6 +987,9 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
/* Automatic IBRS */
#define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8)
+/* Performance Monitoring Version 2 */
+#define CPUID_8000_0022_EAX_PERFMON_V2 (1U << 0)
+
#define CPUID_XSAVE_XSAVEOPT (1U << 0)
#define CPUID_XSAVE_XSAVEC (1U << 1)
#define CPUID_XSAVE_XGETBV1 (1U << 2)
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 2/4] i386/cpu: Add PerfMonV2 feature bit
2024-06-12 19:12 ` [PATCH 2/4] i386/cpu: Add PerfMonV2 feature bit Babu Moger
@ 2024-06-13 7:06 ` Zhao Liu
2024-06-13 14:12 ` Moger, Babu
0 siblings, 1 reply; 12+ messages in thread
From: Zhao Liu @ 2024-06-13 7:06 UTC (permalink / raw)
To: Babu Moger; +Cc: pbonzini, qemu-devel, kvm
On Wed, Jun 12, 2024 at 02:12:18PM -0500, Babu Moger wrote:
> Date: Wed, 12 Jun 2024 14:12:18 -0500
> From: Babu Moger <babu.moger@amd.com>
> Subject: [PATCH 2/4] i386/cpu: Add PerfMonV2 feature bit
> X-Mailer: git-send-email 2.34.1
>
> From: Sandipan Das <sandipan.das@amd.com>
>
> CPUID leaf 0x80000022, i.e. ExtPerfMonAndDbg, advertises new performance
> monitoring features for AMD processors. Bit 0 of EAX indicates support
> for Performance Monitoring Version 2 (PerfMonV2) features. If found to
> be set during PMU initialization, the EBX bits can be used to determine
> the number of available counters for different PMUs. It also denotes the
> availability of global control and status registers.
>
> Add the required CPUID feature word and feature bit to allow guests to
> make use of the PerfMonV2 features.
>
> Signed-off-by: Sandipan Das <sandipan.das@amd.com>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> target/i386/cpu.c | 26 ++++++++++++++++++++++++++
> target/i386/cpu.h | 4 ++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 86a90b1405..7f1837cdc9 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -1228,6 +1228,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
> .tcg_features = 0,
> .unmigratable_flags = 0,
> },
> + [FEAT_8000_0022_EAX] = {
> + .type = CPUID_FEATURE_WORD,
> + .feat_names = {
> + "perfmon-v2", NULL, NULL, NULL,
> + NULL, NULL, NULL, NULL,
> + NULL, NULL, NULL, NULL,
> + NULL, NULL, NULL, NULL,
> + NULL, NULL, NULL, NULL,
> + NULL, NULL, NULL, NULL,
> + NULL, NULL, NULL, NULL,
> + NULL, NULL, NULL, NULL,
> + },
> + .cpuid = { .eax = 0x80000022, .reg = R_EAX, },
> + .tcg_features = 0,
> + .unmigratable_flags = 0,
> + },
> [FEAT_XSAVE] = {
> .type = CPUID_FEATURE_WORD,
> .feat_names = {
> @@ -6998,6 +7014,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
> *edx = 0;
> }
> break;
> + case 0x80000022:
> + *eax = *ebx = *ecx = *edx = 0;
> + /* AMD Extended Performance Monitoring and Debug */
> + if (kvm_enabled() && cpu->enable_pmu &&
> + (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) {
> + *eax = CPUID_8000_0022_EAX_PERFMON_V2;
> + *ebx = kvm_arch_get_supported_cpuid(cs->kvm_state, index, count,
> + R_EBX) & 0xf;
Although only EAX[bit 0] and EBX[bits 0-3] are supported right now, I
think it's better to use “|=” rather than just override the
original *eax and *ebx, which will prevent future mistakes or omissions.
Otherwise,
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/4] i386/cpu: Add PerfMonV2 feature bit
2024-06-13 7:06 ` Zhao Liu
@ 2024-06-13 14:12 ` Moger, Babu
0 siblings, 0 replies; 12+ messages in thread
From: Moger, Babu @ 2024-06-13 14:12 UTC (permalink / raw)
To: Zhao Liu; +Cc: pbonzini, qemu-devel, kvm
Hi Zhao,
On 6/13/24 02:06, Zhao Liu wrote:
> On Wed, Jun 12, 2024 at 02:12:18PM -0500, Babu Moger wrote:
>> Date: Wed, 12 Jun 2024 14:12:18 -0500
>> From: Babu Moger <babu.moger@amd.com>
>> Subject: [PATCH 2/4] i386/cpu: Add PerfMonV2 feature bit
>> X-Mailer: git-send-email 2.34.1
>>
>> From: Sandipan Das <sandipan.das@amd.com>
>>
>> CPUID leaf 0x80000022, i.e. ExtPerfMonAndDbg, advertises new performance
>> monitoring features for AMD processors. Bit 0 of EAX indicates support
>> for Performance Monitoring Version 2 (PerfMonV2) features. If found to
>> be set during PMU initialization, the EBX bits can be used to determine
>> the number of available counters for different PMUs. It also denotes the
>> availability of global control and status registers.
>>
>> Add the required CPUID feature word and feature bit to allow guests to
>> make use of the PerfMonV2 features.
>>
>> Signed-off-by: Sandipan Das <sandipan.das@amd.com>
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>> ---
>> target/i386/cpu.c | 26 ++++++++++++++++++++++++++
>> target/i386/cpu.h | 4 ++++
>> 2 files changed, 30 insertions(+)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 86a90b1405..7f1837cdc9 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -1228,6 +1228,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
>> .tcg_features = 0,
>> .unmigratable_flags = 0,
>> },
>> + [FEAT_8000_0022_EAX] = {
>> + .type = CPUID_FEATURE_WORD,
>> + .feat_names = {
>> + "perfmon-v2", NULL, NULL, NULL,
>> + NULL, NULL, NULL, NULL,
>> + NULL, NULL, NULL, NULL,
>> + NULL, NULL, NULL, NULL,
>> + NULL, NULL, NULL, NULL,
>> + NULL, NULL, NULL, NULL,
>> + NULL, NULL, NULL, NULL,
>> + NULL, NULL, NULL, NULL,
>> + },
>> + .cpuid = { .eax = 0x80000022, .reg = R_EAX, },
>> + .tcg_features = 0,
>> + .unmigratable_flags = 0,
>> + },
>> [FEAT_XSAVE] = {
>> .type = CPUID_FEATURE_WORD,
>> .feat_names = {
>> @@ -6998,6 +7014,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>> *edx = 0;
>> }
>> break;
>> + case 0x80000022:
>> + *eax = *ebx = *ecx = *edx = 0;
>> + /* AMD Extended Performance Monitoring and Debug */
>> + if (kvm_enabled() && cpu->enable_pmu &&
>> + (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) {
>> + *eax = CPUID_8000_0022_EAX_PERFMON_V2;
>> + *ebx = kvm_arch_get_supported_cpuid(cs->kvm_state, index, count,
>> + R_EBX) & 0xf;
>
> Although only EAX[bit 0] and EBX[bits 0-3] are supported right now, I
> think it's better to use “|=” rather than just override the
> original *eax and *ebx, which will prevent future mistakes or omissions.
Sure. Will do. Thanks for the review.
>
> Otherwise,
>
> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
>
--
Thanks
Babu Moger
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/4] i386/cpu: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa
2024-06-12 19:12 [PATCH 0/4] i386/cpu: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model Babu Moger
2024-06-12 19:12 ` [PATCH 1/4] i386/cpu: Add RAS feature bits on EPYC CPU models Babu Moger
2024-06-12 19:12 ` [PATCH 2/4] i386/cpu: Add PerfMonV2 feature bit Babu Moger
@ 2024-06-12 19:12 ` Babu Moger
2024-06-13 7:11 ` Zhao Liu
2024-06-12 19:12 ` [PATCH 4/4] i386/cpu: Add support for EPYC-Turin model Babu Moger
3 siblings, 1 reply; 12+ messages in thread
From: Babu Moger @ 2024-06-12 19:12 UTC (permalink / raw)
To: pbonzini; +Cc: qemu-devel, babu.moger, kvm
Following feature bits are added on EPYC-Genoa-v2 model.
perfmon-v2: Allows guests to make use of the PerfMonV2 features.
SUCCOR: Software uncorrectable error containment and recovery capability.
The processor supports software containment of uncorrectable errors
through context synchronizing data poisoning and deferred error
interrupts.
McaOverflowRecov: MCA overflow recovery support.
The feature details are available in APM listed below [1].
[1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
Publication # 24593 Revision 3.41.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
---
target/i386/cpu.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7f1837cdc9..64e6dc62e2 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5272,6 +5272,21 @@ static const X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x80000022,
.model_id = "AMD EPYC-Genoa Processor",
.cache_info = &epyc_genoa_cache_info,
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ .props = (PropValue[]) {
+ { "overflow-recov", "on" },
+ { "succor", "on" },
+ { "perfmon-v2", "on" },
+ { "model-id",
+ "AMD EPYC-Genoa-v2 Processor" },
+ { /* end of list */ }
+ },
+ },
+ { /* end of list */ }
+ }
},
};
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 3/4] i386/cpu: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa
2024-06-12 19:12 ` [PATCH 3/4] i386/cpu: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa Babu Moger
@ 2024-06-13 7:11 ` Zhao Liu
2024-06-13 14:13 ` Moger, Babu
0 siblings, 1 reply; 12+ messages in thread
From: Zhao Liu @ 2024-06-13 7:11 UTC (permalink / raw)
To: Babu Moger; +Cc: pbonzini, qemu-devel, kvm
On Wed, Jun 12, 2024 at 02:12:19PM -0500, Babu Moger wrote:
> Date: Wed, 12 Jun 2024 14:12:19 -0500
> From: Babu Moger <babu.moger@amd.com>
> Subject: [PATCH 3/4] i386/cpu: Enable perfmon-v2 and RAS feature bits on
> EPYC-Genoa
> X-Mailer: git-send-email 2.34.1
>
> Following feature bits are added on EPYC-Genoa-v2 model.
>
> perfmon-v2: Allows guests to make use of the PerfMonV2 features.
nit s/Allows/Allow/
> SUCCOR: Software uncorrectable error containment and recovery capability.
> The processor supports software containment of uncorrectable errors
> through context synchronizing data poisoning and deferred error
> interrupts.
>
> McaOverflowRecov: MCA overflow recovery support.
>
> The feature details are available in APM listed below [1].
> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
> Publication # 24593 Revision 3.41.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
> ---
> target/i386/cpu.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/4] i386/cpu: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa
2024-06-13 7:11 ` Zhao Liu
@ 2024-06-13 14:13 ` Moger, Babu
0 siblings, 0 replies; 12+ messages in thread
From: Moger, Babu @ 2024-06-13 14:13 UTC (permalink / raw)
To: Zhao Liu; +Cc: pbonzini, qemu-devel, kvm
On 6/13/24 02:11, Zhao Liu wrote:
> On Wed, Jun 12, 2024 at 02:12:19PM -0500, Babu Moger wrote:
>> Date: Wed, 12 Jun 2024 14:12:19 -0500
>> From: Babu Moger <babu.moger@amd.com>
>> Subject: [PATCH 3/4] i386/cpu: Enable perfmon-v2 and RAS feature bits on
>> EPYC-Genoa
>> X-Mailer: git-send-email 2.34.1
>>
>> Following feature bits are added on EPYC-Genoa-v2 model.
>>
>> perfmon-v2: Allows guests to make use of the PerfMonV2 features.
>
> nit s/Allows/Allow/
Sure.
>
>> SUCCOR: Software uncorrectable error containment and recovery capability.
>> The processor supports software containment of uncorrectable errors
>> through context synchronizing data poisoning and deferred error
>> interrupts.
>>
>> McaOverflowRecov: MCA overflow recovery support.
>>
>> The feature details are available in APM listed below [1].
>> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming
>> Publication # 24593 Revision 3.41.
>>
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
>> ---
>> target/i386/cpu.c | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>
> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
>
--
Thanks
Babu Moger
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/4] i386/cpu: Add support for EPYC-Turin model
2024-06-12 19:12 [PATCH 0/4] i386/cpu: Add support for perfmon-v2, RAS bits and EPYC-Turin CPU model Babu Moger
` (2 preceding siblings ...)
2024-06-12 19:12 ` [PATCH 3/4] i386/cpu: Enable perfmon-v2 and RAS feature bits on EPYC-Genoa Babu Moger
@ 2024-06-12 19:12 ` Babu Moger
2024-06-13 7:17 ` Zhao Liu
3 siblings, 1 reply; 12+ messages in thread
From: Babu Moger @ 2024-06-12 19:12 UTC (permalink / raw)
To: pbonzini; +Cc: qemu-devel, babu.moger, kvm
Adds the support for AMD EPYC zen 5 processors(EPYC-Turin).
Adds the following new feature bits on top of the feature bits from
the previous generation EPYC models.
movdiri : Move Doubleword as Direct Store Instruction
movdir64b : Move 64 Bytes as Direct Store Instruction
avx512-vp2intersect: AVX512 Vector Pair Intersection to a Pair
of Mask Register
avx-vnni : AVX VNNI Instruction
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
target/i386/cpu.c | 131 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 131 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 64e6dc62e2..213b5f12f0 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2370,6 +2370,60 @@ static const CPUCaches epyc_genoa_cache_info = {
},
};
+static const CPUCaches epyc_turin_cache_info = {
+ .l1d_cache = &(CPUCacheInfo) {
+ .type = DATA_CACHE,
+ .level = 1,
+ .size = 48 * KiB,
+ .line_size = 64,
+ .associativity = 12,
+ .partitions = 1,
+ .sets = 64,
+ .lines_per_tag = 1,
+ .self_init = 1,
+ .no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
+ },
+ .l1i_cache = &(CPUCacheInfo) {
+ .type = INSTRUCTION_CACHE,
+ .level = 1,
+ .size = 32 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .partitions = 1,
+ .sets = 64,
+ .lines_per_tag = 1,
+ .self_init = 1,
+ .no_invd_sharing = true,
+ .share_level = CPU_TOPO_LEVEL_CORE,
+ },
+ .l2_cache = &(CPUCacheInfo) {
+ .type = UNIFIED_CACHE,
+ .level = 2,
+ .size = 1 * MiB,
+ .line_size = 64,
+ .associativity = 16,
+ .partitions = 1,
+ .sets = 1024,
+ .lines_per_tag = 1,
+ .share_level = CPU_TOPO_LEVEL_CORE,
+ },
+ .l3_cache = &(CPUCacheInfo) {
+ .type = UNIFIED_CACHE,
+ .level = 3,
+ .size = 32 * MiB,
+ .line_size = 64,
+ .associativity = 16,
+ .partitions = 1,
+ .sets = 32768,
+ .lines_per_tag = 1,
+ .self_init = true,
+ .inclusive = true,
+ .complex_indexing = false,
+ .share_level = CPU_TOPO_LEVEL_DIE,
+ },
+};
+
/* The following VMX features are not supported by KVM and are left out in the
* CPU definitions:
*
@@ -5288,6 +5342,83 @@ static const X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
+ {
+ .name = "EPYC-Turin",
+ .level = 0xd,
+ .vendor = CPUID_VENDOR_AMD,
+ .family = 26,
+ .model = 0,
+ .stepping = 0,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
+ CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
+ CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+ CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA |
+ CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ |
+ CPUID_EXT_SSE3,
+ .features[FEAT_1_EDX] =
+ CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
+ CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
+ CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
+ CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
+ CPUID_VME | CPUID_FP87,
+ .features[FEAT_6_EAX] =
+ CPUID_6_EAX_ARAT,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
+ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
+ CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F |
+ CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA |
+ CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |
+ CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
+ .features[FEAT_7_0_ECX] =
+ CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
+ CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
+ CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
+ CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
+ CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
+ CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_MOVDIRI |
+ CPUID_7_0_ECX_MOVDIR64B,
+ .features[FEAT_7_0_EDX] =
+ CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_AVX512_VP2INTERSECT,
+ .features[FEAT_7_1_EAX] =
+ CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
+ CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
+ CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
+ CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
+ CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
+ CPUID_EXT2_SYSCALL,
+ .features[FEAT_8000_0007_EBX] =
+ CPUID_8000_0007_EBX_OVERFLOW_RECOV | CPUID_8000_0007_EBX_SUCCOR,
+ .features[FEAT_8000_0008_EBX] =
+ CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
+ CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
+ CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
+ CPUID_8000_0008_EBX_STIBP_ALWAYS_ON |
+ CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD,
+ .features[FEAT_8000_0021_EAX] =
+ CPUID_8000_0021_EAX_No_NESTED_DATA_BP |
+ CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING |
+ CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE |
+ CPUID_8000_0021_EAX_AUTO_IBRS,
+ .features[FEAT_8000_0022_EAX] =
+ CPUID_8000_0022_EAX_PERFMON_V2,
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+ CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
+ .features[FEAT_SVM] =
+ CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI |
+ CPUID_SVM_SVME_ADDR_CHK,
+ .xlevel = 0x80000022,
+ .model_id = "AMD EPYC-Turin Processor",
+ .cache_info = &epyc_turin_cache_info,
+ },
};
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 4/4] i386/cpu: Add support for EPYC-Turin model
2024-06-12 19:12 ` [PATCH 4/4] i386/cpu: Add support for EPYC-Turin model Babu Moger
@ 2024-06-13 7:17 ` Zhao Liu
2024-06-13 14:13 ` Moger, Babu
0 siblings, 1 reply; 12+ messages in thread
From: Zhao Liu @ 2024-06-13 7:17 UTC (permalink / raw)
To: Babu Moger; +Cc: pbonzini, qemu-devel, kvm
On Wed, Jun 12, 2024 at 02:12:20PM -0500, Babu Moger wrote:
> Date: Wed, 12 Jun 2024 14:12:20 -0500
> From: Babu Moger <babu.moger@amd.com>
> Subject: [PATCH 4/4] i386/cpu: Add support for EPYC-Turin model
> X-Mailer: git-send-email 2.34.1
>
> Adds the support for AMD EPYC zen 5 processors(EPYC-Turin).
nit s/Adds/Add
> Adds the following new feature bits on top of the feature bits from
s/Adds/Add/
> the previous generation EPYC models.
>
> movdiri : Move Doubleword as Direct Store Instruction
> movdir64b : Move 64 Bytes as Direct Store Instruction
> avx512-vp2intersect: AVX512 Vector Pair Intersection to a Pair
> of Mask Register
> avx-vnni : AVX VNNI Instruction
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> target/i386/cpu.c | 131 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 131 insertions(+)
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/4] i386/cpu: Add support for EPYC-Turin model
2024-06-13 7:17 ` Zhao Liu
@ 2024-06-13 14:13 ` Moger, Babu
0 siblings, 0 replies; 12+ messages in thread
From: Moger, Babu @ 2024-06-13 14:13 UTC (permalink / raw)
To: Zhao Liu; +Cc: pbonzini, qemu-devel, kvm
On 6/13/24 02:17, Zhao Liu wrote:
> On Wed, Jun 12, 2024 at 02:12:20PM -0500, Babu Moger wrote:
>> Date: Wed, 12 Jun 2024 14:12:20 -0500
>> From: Babu Moger <babu.moger@amd.com>
>> Subject: [PATCH 4/4] i386/cpu: Add support for EPYC-Turin model
>> X-Mailer: git-send-email 2.34.1
>>
>> Adds the support for AMD EPYC zen 5 processors(EPYC-Turin).
>
> nit s/Adds/Add
Sure.
>
>> Adds the following new feature bits on top of the feature bits from
>
> s/Adds/Add/
Sure.
>
>> the previous generation EPYC models.
>>
>> movdiri : Move Doubleword as Direct Store Instruction
>> movdir64b : Move 64 Bytes as Direct Store Instruction
>> avx512-vp2intersect: AVX512 Vector Pair Intersection to a Pair
>> of Mask Register
>> avx-vnni : AVX VNNI Instruction
>>
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>> ---
>> target/i386/cpu.c | 131 ++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 131 insertions(+)
>
> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
>
--
Thanks
Babu Moger
^ permalink raw reply [flat|nested] 12+ messages in thread