From: Chao Liu <lc00631@tecorigin.com> To: alistair23@gmail.com, palmer@dabbelt.com Cc: zhiwei_liu@linux.alibaba.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, lc00631@tecorigin.com, zqz00548@tecorigin.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v0 0/1] fix the way riscv_plic_hart_config_string() Date: Tue, 15 Apr 2025 17:53:57 +0800 [thread overview] Message-ID: <cover.1744709888.git.lc00631@tecorigin.com> (raw) Hi, all: When I was configuring multiple sockets using riscv virt Machine, I found that I could not set the PLIC correctly. By checking the code, I found that it was due to not traversing the CPUState correctly in the riscv_plic_hart_config_string() function. So I tried to fix this. -- Regards, Chao Chao Liu (1): hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly hw/riscv/boot.c | 4 ++-- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/riscv_hart.c | 1 + hw/riscv/sifive_u.c | 5 +++-- hw/riscv/virt.c | 2 +- include/hw/riscv/boot.h | 2 +- 6 files changed, 9 insertions(+), 7 deletions(-) -- 2.48.1
WARNING: multiple messages have this Message-ID (diff)
From: Chao Liu <lc00631@tecorigin.com> To: alistair23@gmail.com, palmer@dabbelt.com Cc: zhiwei_liu@linux.alibaba.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, lc00631@tecorigin.com, zqz00548@tecorigin.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 0/1] fix the way riscv_plic_hart_config_string() gets the CPUState Date: Tue, 15 Apr 2025 18:05:29 +0800 [thread overview] Message-ID: <cover.1744709888.git.lc00631@tecorigin.com> (raw) Message-ID: <20250415100529.zdA1KDJYG0BZXb6--FUi1wGYvG66-dU0eSPf05U8Ki0@z> (raw) Hi, all: When I was configuring multiple sockets using riscv virt Machine, I found that I could not set the PLIC correctly. By checking the code, I found that it was due to not traversing the CPUState correctly in the riscv_plic_hart_config_string() function. So I tried to fix this. PATCH v1 update commit message: "For non-numa or single-cluster machines, hartid_base should be 0." -- Regards, Chao Chao Liu (1): hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly hw/riscv/boot.c | 4 ++-- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/riscv_hart.c | 1 + hw/riscv/sifive_u.c | 5 +++-- hw/riscv/virt.c | 2 +- include/hw/riscv/boot.h | 2 +- 6 files changed, 9 insertions(+), 7 deletions(-) -- 2.48.1
next reply other threads:[~2025-04-15 9:57 UTC|newest] Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top 2025-04-15 9:53 Chao Liu [this message] 2025-04-15 9:53 ` [PATCH v0 1/1] hw/riscv: fix PLIC hart topology configuration string when not getting CPUState correctly Chao Liu 2025-04-15 10:05 ` [PATCH v1 " Chao Liu 2025-04-15 10:48 ` Philippe Mathieu-Daudé 2025-04-15 11:14 ` Chao Liu 2025-04-15 11:40 ` Philippe Mathieu-Daudé 2025-04-15 10:05 ` [PATCH v1 0/1] fix the way riscv_plic_hart_config_string() gets the CPUState Chao Liu
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